Mixed Signal Lecture PLL

Mixed signal systems
and integrated circuits
Akira Matsuzawa
Tokyo Institute of Technology
2005/5/10 A. Matsuzawa 1
PLL system
• Basic PLL system

• Basic circuit block
– Phase detector
• Analog mixer
• Digital 3 state Phase Frequency Detector
• Charge pump circuit
– Filter
– Voltage Controlled Oscillator
• Pull-in process
• System characteristics (frequency and time response)
– With 1st order filter
– With Lag-Lead filter
• Delay Locked Loop
• Clock recovery circuits
• Frequency synthesizer
Phase locked loop (PLL)
Application area
1. Internal clock generation in LSI locked to external clock
2. Frequency Synthesizer for communication systems
3. Clock recovery for communication systems and data storage systems
4. FM demodulation
Frequency Synthesizer
Fast settling and accurate frequency are required
Clock recovery
Basic Phase-Locked Loop (PLL) system
PLL is a feedback system to match the input signal phase and the output signal phase.
Through this process, frequencies of these signals become equal completely.
Higher frequency components

are attenuated
V PD = K p (θi − θo )
Vc ωvco ∝ Vc
Input signal
θi Phase Filter
Voltage
Controlled
Output signal
detector (LPF)
θo Oscillator
Basic construction of a PLL system
Frequency
Divider
Waveforms in PLL system
Analog phase detector (mixer type)
Suitable for high frequency application, but no ability as a frequency detector
sin (ω1t + θ1 ) Vout

A sin ((ω1 + ω2 )t + θ1 + θ 2 )
Vout Vout Filter out
B + sin ((ω1 − ω2 )t + θ1 − θ 2 )
cos (ω2 t + θ 2 )
A ≈ sin (θ1 − θ 2 ) ≈ θ1 − θ 2
Vout ≈ θ1 − θ 2
B
π π
−π −
2 2 π
Gilbert cell PD (Small signal) Δθ

Or EXOR
3 state Phase Frequency Detector
This 3 state phase detector is currently most widely used.
Because it has a ability for frequency detect.
“1” D Q Up A
A Clk
R B
Glitch
B R Up
Clk
Down Down
“1” D Q
Vout goes “High”, if rising edge comes earlier.
Frequency detector
State II State 0 State I Vout
B A
B
UP=0 UP=0 UP=1
A − 2π
Down=1 Down=0 Down=0
A B 2π Δθ
Works as an Up-Down counter
Dead zone in PFD
The most serious issue of PFD is dead zone at a small phase deviation.
This causes a large jitter and a phase noise.
Improved PDF
Id Insert delay circuits
Δθ
Dead zone
Narrow pulse effect
If the output pulse is very narrow, the pulse height can not
exceed the logic threshold voltage. This results in the missing data.
Finally, this makes the dead zone.
Charge pump circuit
The charge pump circuit can generate the averaged current of which the
value is proportional to the phase difference.
This circuit works as Digital to Analog Converter.

Ipump
up
IPD Vcont to VCO
F(s)
down Δθ
I PD = K PD ⋅ Δθ
Ipump
I pump 2π
K PD = ( A / rad )
2π
IPD :Effective average current
Actual charge pump circuit
Cascode: high impedance and small capacitance
Stable node voltage

Prevent large voltage change,
when not connected
Active filter
Voltage Controlled Oscillator
Design points Proper tuning range

Low jitter and phase noise
Low power supply noise and stability
High linearity for V to f characteristics
Vcntr is low
Vcntr VCO
ωout = ω fr + KVCO ⋅ Vcntr

Frequency
Vcntr is high
ωmax
ωfr
ωmin
Vcont
Vmin Vcenter Vmax
VCO
VCO act as a low pass filter to the control voltage signal
ωout = ω fr + K VCOVcntr
( ∫
y( t ) = A cos ω fr t + K VCO Vcntr dt )
For example : Vcntr ( t ) = Vm cos ωm t
⎛ K ⎞
y( t ) = A cos ⎜⎜ ω fr t + VCO Vm sin ωm t ⎟⎟
⎝ ωm ⎠
High frequency component in Vcntr can be suppressed Low frequency component in Vcntr can't be suppressed
Current starved Ring oscillator
This ring oscillator is widely used for the digital clock generator in LSI
Current sourse
IVCO
Ring Oscillator (Odd stages)
Vcntr
3
C tot = C out + C in = C ox ( L pW p + LnWn ) + C ox ( L pW p + LnWn )
2
5
= C ox ( L pW p + LnWn ) Merit: easy implementation on LSI
2
Issue: large jitter noise
I VCO
f osc =
N ⋅ C tot ⋅ VDD
VCO (Source coupled VCO)
VDD VDD
Sometime used for
Out VDD Out Low frequency oscillator
M1 M2 M1 M2
Off 2Io
X Y
VinVCO Discharge X Low frequency generation
Y
Differential signal
Io Io High noise tolerance
Io
M2 on M1 on M2 on M1 on M2 on
Out VDD
Out VDD-VTHN
Y
X
Time

Mixed Signal Lecture PLL

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Mixed Signal Lecture PLL

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Mixed signal systems

and integrated circuits

Tokyo Institute of Technology

• Basic PLL system

Fast settling and accurate frequency are required

Higher frequency components

Basic construction of a PLL system

sin (ω1t + θ1 ) Vout

Gilbert cell PD (Small signal) Δθ

Id Insert delay circuits

This circuit works as Digital to Analog Converter.

Cascode: high impedance and small capacitance

Stable node voltage

Design points Proper tuning range

ωout = ω fr + KVCO ⋅ Vcntr

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