INSTITUTO TECNOL

OGICO Y DE ESTUDIOS
SUPERIORES DE MONTERREY
CAMPUS MONTERREY
SCHOOL OF ENGINEERING
DIVISION OF MECHATRONICS AND INFORMATION
TECHNOLOGIES
GRADUATE PROGRAMS
MODELING OF A CMOS ACTIVE PIXEL IMAGE SENSOR
TOWARDS SENSOR INTEGRATION WITH MICROFLUIDIC DEVICES
THESIS
MASTER OF SCIENCE WITH MAJOR IN ELECTRONICS
ENGINEERING (ELECTRONCS SYSTEMS)
BY
MATIAS V

AZQUEZ PI

N

ON
MONTERREY, N.L. MAY, 2011
Modeling of a CMOS Active Pixel Image Sensor
Towards Sensor Integration with Microuidic Devices
by
Matias V azquez Pi n on
Thesis
School of Engineering
Division of Mechatronics and Information Technologies
Graduate Programs
Master of Science with Major in Electronics Engineering
(Electronics Systems)
Instituto Tecnol ogico y de Estudios Superiores de Monterrey
Campus Monterrey
Monterrey, N.L. May, 2011
Instituto Tecnol ogico y de Estudios Superiores de Monterrey
Campus Monterrey
Division of Mechatronics and Information Technologies
Graduate Programs
The committee members hereby recommend the thesis presented by Matias V azquez Pi n on
to be accepted as a partial fulllment of the requirements for the degree of Master in
Science with Major in Electronics Engineering (Electronics Systems).
Evaluation committee:
Prof. Sergio Omar Martnez Chapa, Ph.D.
Advisor
Prof. Graciano Dieck Assad, Ph.D.
Member
Prof. Sergio Camacho Le on, Ph.D.
Member
Prof. Gerardo A. Casta n on

Avila, Ph.D.
Member
INSTITUTO TECNOL

OGICO Y DE ESTUDIOS
SUPERIORES DE MONTERREY
CAMPUS MONTERREY
SCHOOL OF ENGINEERING
DIVISION OF MECHATRONICS AND INFORMATION
TECHNOLOGIES
GRADUATE PROGRAMS
MODELING OF A CMOS ACTIVE PIXEL IMAGE SENSOR
TOWARDS SENSOR INTEGRATION WITH MICROFLUIDIC DEVICES
THESIS
SUBMITTED AS PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
MASTER OF SCIENCE WITH MAJOR IN ELECTRONICS
ENGINEERING (ELECTRONCS SYSTEMS)
BY
MATIAS V

AZQUEZ PI

N

ON
MONTERREY, N.L. MAY, 2011
To my family. . .
For supporting me when I decide,
congratulating me when I succeed
and advising me when I mistake.
v
Modeling of a CMOS Active Pixel Image Sensor -
Towards Sensor Integration with Microuidic Devices
Matias V azquez Pi n on, B.Sc.
Instituto Tecnol ogico y de Estudios Superiores de Monterrey, 2011.
Advisor: Sergio Omar Martnez Chapa, Ph.D.
Instituto Tecnol ogico y de Estudios Superiores de Monterrey.
A B S T R A C T
Recently, microuidic devices have received considerable attention because of the many
potential applications in medicine and environment monitoring. In such systems, cells and
particles suspended in uids can be manipulated for analysis. On the other hand, solid state
imagers have been very successful in consumer electronic devices like digital still cameras
and handy camcorders. Microuidic systems are projected to develop more complex func-
tions as they integrate electronic/optoelectronic sensors that could monitor the activity within
microchannels.
This thesis presents research work on modeling and simulation of CMOS Active Pixel
Sensors providing some basis for their future integration with microuidic devices. An
overview of image sensors and a literature review of microuidic systems integrating image
sensors are presented. Dierent stages of a CMOS active pixel sensor are modeled, including
readout, buer and selection circuits. Computer simulations are carried out demonstrating
the functionality of every stage. Additionally, it was modeled and simulated a 4 5 pixel
array, incorporating the addressing and reset signals.
Simulation results illustrate how the performance of the CMOS active pixel sensor can
be adjusted to meet the specications for scientic applications. A wide dynamic range is
obtained by achieving a large full-well capacity for the photodiode and maximizing the gain
of the source follower amplier. Also, the ll factor is increased by reducing the size of the
on-pixel transistors.
vi
Contents
1 Introduction 1
2 Theoretical Background on Solid-State Image Sensors 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Human light perception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 The solid-state imaging process . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.1 Absorption of light in semiconductors . . . . . . . . . . . . . . . . . 7
2.3.2 Charge collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.1 Operation principle of photodiodes . . . . . . . . . . . . . . . . . . 9
2.4.2 The photodiode full-well capacity model . . . . . . . . . . . . . . . 11
2.5 CMOS Image Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.1 CMOS pixel structures . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 State-of-the-Art on Microuidic Systems and Image Sensors Integration 18
4 Active Pixel Sensor Modeling and Simulation 25
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Pixel read-out circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.1 Reset transistor M
RST
. . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.2 Source Follower Amplier . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 Photodiode design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.1 Pn-junction capacitance . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.2 Physical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4 Pixel array simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4.1 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5 Conclusions and future work 46
6 Appendix A 49
References 52
Vita 53
vii
List of Figures
2.1 Solid-state imaging process [1]. . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Transmission and reection of light in dielectric layers . . . . . . . . . . . . 7
2.3 Silicon absorption length of light [2]. . . . . . . . . . . . . . . . . . . . . . . 8
2.4 The photodiode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Evolution of pixel size, CMOS technology node used to fabricate the devices
and the minimum feature size of the most advanced CMOS logic process [3]. 13
2.6 Passive CMOS pixel with a single in-pixel transistor [3]. . . . . . . . . . . . 14
2.7 Active CMOS pixel based on in-pixel amplier [3]. . . . . . . . . . . . . . . 15
2.8 Digital Pixel Sensor Architecture . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Integrated digital cytometer system components and architecture [4]. . . . . . 18
3.2 Photograph of the linear active pixel CMOS sensor [4]. . . . . . . . . . . . . 19
3.3 Flip-chip on glass illustration of a hybrid microuidic digital cytometer. [4]. . 20
3.4 PDMS cast chamber, shown in a cross-sectional view, realized a microuidic
channel passing through the structure and over the active area of the sensor
chip which is wire-bonded to a PCB. [4]. . . . . . . . . . . . . . . . . . . . . 20
3.5 The photodiode pixel linear arrays. [5]. . . . . . . . . . . . . . . . . . . . . 21
3.6 Post bond image of the CMOS sensor to the microuidic chip. [5]. . . . . . . 21
3.7 Plot of the CMOS sensor output upon detection of a 6 m polystyrene poly-
sphere. [5]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8 A schematic of photodiode type CMOS active pixel sensor. [6]. . . . . . . . . 22
3.9 Comparison of images of microbeads on chip surface taken by (a) a camera
and (b) the contact imager. An overlapped view is also shown in (c). [6]. . . . 23
3.10 Schematic diagram of the modied active pixel circuit. [7]. . . . . . . . . . . 24
4.1 3T pixel conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Linear approximation of V
TH
term as a function of the body-factor term

s
+ V
S B
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Boosted V
RST
and resulting V
PD RST
. . . . . . . . . . . . . . . . . . . . . . 29
4.4 Source follower drain current and output voltage for dierent feature sizes of
M
COL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5 Photodiode response at dark environment at 33ms integration time . . . . . . 32
4.6 Charge distribution eect in the photodiodes capacitance . . . . . . . . . . . 33
4.7 Photodiode response at a dark environmet at 3.3ms integration time . . . . . 34
viii
4.8 Full discharge of the 50 fF ideal capacitance at a) 30 frames per second, b)
300 frames per second, c) 3,000 frames per second and d) 30,000 frames per
second. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.9 Layout example of a square-shaped photodiode including on-pixel transistors 36
4.10 Pn-junction photodiode response at dark environment at 33ms integration time 37
4.11 Charge distribution eect on the pn-junction photodiode . . . . . . . . . . . 38
4.12 Pn-junction photodiode response at dark environment at 300 frames per second 38
4.13 Full discharge of the square-shaped N
DIFF
P
SUB
photodiode with a C
PD
= 58.44 fF
pn-junction capacitance at a) 30 frames per second, b) 300 frames per second,
c) 3,000 frames per second and d) 30,000 frames per second . . . . . . . . . 39
4.14 Full discharge of the ideal photodiode with a C
PD
= 58.44 fF capacitance at a)
30 frames per second, b) 300 frames per second, c) 3,000 frames per second
and d) 30,000 frames per second . . . . . . . . . . . . . . . . . . . . . . . . 40
4.15 Timing signals for accessing and read-out pixels . . . . . . . . . . . . . . . . 41
4.16 Active pixel sensor array including horizontal, vertical and read-out circuitry 42
4.17 Simulation results for a single pixel of the 4 5 array. From top to bottom:
Reset pulse, Select pulse, Photodiode voltage, Source follower output, Col-
umn output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.18 Vertical control signals: Reset pulses and row selection . . . . . . . . . . . . 44
4.19 Output signals of the pixel array . . . . . . . . . . . . . . . . . . . . . . . . 45
ix
List of Tables
3.1 Output characteristics and specications of the Linear Active Pixel Sensor . . 19
3.2 Summary of sensor performance . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Physical parameters of M
RST
for simulation of a photodiode with capacitance
C
PD
= 58.44 fF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Simulation results and percentage error of the full-discharge current of the
ideal and the pn-junction capacitances. . . . . . . . . . . . . . . . . . . . . . 39
4.3 Simulation results and percentage error of the full-discharge current of the
ideal and the pn-junction capacitances for the same capacitance values. . . . . 40
x
Chapter 1
Introduction
In recent years, biomedical research has brought to the world the possibility of developing
each time smaller and more complex devices designed for a wide range of medical applica-
tions. From micro-machined accelerometers useful to measure patients movement in ther-
apy rehabilitation to complete laboratories implemented in just one small piece of silicon to
diagnose fast and eectively illnesses. Today, micro-fabrication processes allow the imple-
mentation of, not only electronic circuits, but also mechanical and optoelectronical systems
on the same silicon die. This capability widely extends the design possibilities when thinking
about new devices that help people to diagnose illness, develop new drugs and new kind of
sensors.
Of particular interest is the development of new micro-devices that have the capability
of performing clinic analysis using a very small volume of samples like corporal uids, tis-
sues or even individual cells [7]. These devices, so-called Laboratory-on-a-Chip (LoCs), are
promising instruments because of its high throughput and the possibility of performing such
analysis without relying on signicant laboratory infrastructure.
A lab-on-a-chip device integrates all the instruments required to perform a clinical anal-
ysis on a single die of a very small size (few cm
2
). This possibility brings some important
advantages such as mass fabrication through a standard semiconductor process and with this,
a reduced fabrication cost; ease of transportation due to its low volume and weight, low sam-
ple volume consumption and shorter analysis times.
On the other hand, LoC technologies are new research areas having many innovations
possibilities. The laboratory miniaturization innovation provides development of sensor, in-
struments and microelectronic devices on the same die. The LoC technology can be used in
a wide variety of biological studies, for example the extraction of DNA from a blood sample,
cellular separation and characterization, detection of virus, bacteria and cancer cells, testing
of new drugs, among others.
LoCs are possible thanks to the research advances in Biological-Microelectromechanical
Systems (BioMEMs) where, as the name suggests, mechanical and electrical elements can be
1
integrated in a single microsystem in order to analyze biological matter. Mechanical devices
are used to manipulate the sample and electrical devices are used to stimulate reactions and
monitor results.
Such new micro-opto-electronic devices suggest the possibility of implementing a full
image-sensing system where not only the image capture is possible but also the chip timing,
control and image processing circuitry onto the same silicon die. This allows the possibility
of customizing a micro-camera for a particular application [8] such as LoCmonitoring. These
micro-devices are called Camera-on-a-Chip and are possible thanks to a relatively new im-
age sensor technology called Active Pixel Sensor (APS) that takes advantage of the existing
Complementary Metal-Oxide Semiconductor (CMOS) manufacturing facilities. This possi-
bility of fabrication brings several advantages over the other main imaging technologies, the
Coupled-Charge Device (CCD), like lower foundry cost, lower power consumption, lower
power supply voltages, higher speed and smartness by incorporating on-chip signal process-
ing [1]. These advantages makes the camera-on-a-chip the perfect complement for the LoCs
to accomplish the objective of fast and low-cost clinical analysis.
Camera-on-a-chip technology is implemented using CMOS active pixel sensors. These
image sensors have been the subject of extensive development and now share the market with
the CCD image sensors, which have dominated the eld of imaging sensors for a long time
[9]. The CMOS image sensor technology nds many areas of application including robotics
and machine vision, guidance and navigation, automotive, etc. [10]. Consumer electronic
devices such as digital still cameras (DSC), mobile phone cameras, handy camcorders and
digital single lens reex cameras (DSLR) are other applications of this technology. Moreover,
scientic applications sometimes requires additional functions like real-time target tracking
or three-dimensional range nding, etc. The devices designed for such applications are called
smart CMOS image sensors [9].
In solid-state imaging, there are four important functions that have to be realized: light
detection, accumulation of photo-generated signals, switching from accumulation to readout
and scanning. The scanning function was proposed in early 1960s by S. R. Morrison at Hon-
eywell as the photoscanner and by J. W. Horton et al. at IBM as the scanistor [9]. After
that, the solid-state image sensor with scanning circuit using thin-lm transistors (TFT) as
the photodetector was proposed by P. K. Weimer et al., and M. A. Schuster and G. Strull at
NASA proposed the phototransistor (PTr) as well as switching devices to realize X-Y pixel
addressing. They successfully obtained images with a fabricated 50 x 50-pixel array sensor
[9].
The details of solid-state image sensors were published in IEEE Transaction on Elec-
tron Devices in 1968 and almost at the same time, the CCD was invented in 1969 by W.
Boyle and G. E. Smith at AT&T Bell Laboratories. The production of rst commercial MOS
imagers was in the 1980s. CCDs image sensors were prefered over the MOS image sen-
sors due to the fact that they oered superior image quality. Subsequently, eorts has been
made to improve quality of signal of MOS imagers by incorporating an in-pixel amplication
2
mechanism resulting in several amplied type imagers proposed in the late 1980s including
the charge modulated device (CMD), oating gate array (FGA), base-stored image sensor
(BASIS), static induction transistor (SIT) type, amplied MOS imager (AMI), and others.
Besides AMI, these architectures required some modication of standard MOS fabrication
technology and ultimately they were not commercialized and their development was termi-
nated. AMI, on the other hand, can be fabricated in standard CMOS technology without
any modication and its structure is the active pixel sensor (APS). However, AMI uses I-V
converter as a readout circuit while APS uses a source follower, though this dierence is not
critical [9].
The development of CMOS APS technology has several advantages over CCD technol-
ogy. It has been mentioned the possibility of being fabricated on a standard CMOS process
which results in a lower foundry cost, but also has performance improvements such lowpower
consumption (100 to 1000 times lower), high dynamic range, higher blooming threshold, in-
dividual pixel readout, low supply voltage operation, high speed, large size array, radiation
hardness and smartness [1].
High-resolution imaging applications such as professional photography, astronomical
imaging, x-ray, TV broadcasting and machine vision require very large format image sensors.
CCD image sensors have being fabricated with very large formats to support these applica-
tions (from 66 megapixel by Philips in 1997 to 111 megapixel by STA Inc in 2007), however,
large format CCDs are very expensive and dicult to produce with the low defect densities
needed for high quality imaging. When increasing the full-well capacity and incorporating
higher spectral response requirements, the necessary pixel size (i.e, sensor size) makes the
production of such CCDs extremely expensive. Furthermore, power consumption and the
need for external support electronics make CCDs less attractive for those applications. On
the other hand, CMOS APS technology has recently gained more popularity in these image
sensor segments with the recent advancement in frame rates, noise levels and array formats.
This was achieved by utilizing better image sensor architectures and design techniques, and
by improvement in the CMOS fabrication processes and pixel technologies [1].
Furthermore, it has been demonstrated the integration of micro-opto-electronic devices
with LoCs. The opto-electronic components placed directly over the LoCs, replace the task
done by a microscope in the actual laboratory analysis [7], providing, a low-cost, portable
microsystem for clinical analysis.
The work presented in this thesis is concerned with the realization of a CMOS pixel
which can be used in the design of a complete CMOS APS camera-on-a-chip useful for con-
tact imager applications such as micro-channel dielectrophoretic analysis (DEP), cell-based
characterization and others. The proposed pixel was designed using a standard 0.35 m
CMOS process which counts with four metal layers, two poly layers, and a high-resistance
poly layer. Pixel schematic circuits were implemented for parameter extraction and behav-
ioral simulations. The design of the pixel is a modication of the methodology presented by
S. U. Ay in [1].
3
Thesis outline
This document is organized as follows. Chapter 1 presents a general overview of the recent
needs for the development of biomedical micro-devices. It is also explained how advances
in MEMS and Microelectronics has brought new concepts of Lab-on-a-Chip, Camera-on-a-
Chip, and the integration of both technologies to produce a full clinic analysis system. This
explanation includes main applications, advantages and disadvantages.
Chapter 2 presents a theoretical framework on the design of CMOS image sensors. It
begins with solid state imaging concepts in order to describe the process; from photons im-
pacting the active area of the pixel, through the absorption of light and charge collection.
The main pixel architectures used for CMOS image sensors are described and one of them is
selected for this application. Then, the design step of such architecture is presented including
the equations that will be used in later chapters.
Chapter 3 reviews the state-of-the-art literature for CMOS image and optical sensors with
lab-on-a-chip applications. Some of the active pixel architectures using three and four tran-
sistors are described. The chapter also describes techniques used for sensor-microchannel
coupling and packages used to avoid microelectronics breakdown due to microuids manip-
ulation. Moreover, advantages and disadvantages are discussed in detail.
In chapter 4, a CMOS active pixel sensor is designed using equations presented on chapter
2. The design process begins in-pixel with the read-out circuit including the reset transistor
and the source follower amplier. Then the photodiode characteristics are determined and
simulated including electrical and physical parameters. Simulation results between an ideal
capacitance and the designed pn-junction photodiode are presented and analized and the op-
timum parameters are determined. Also, the simulation analysis for a complete active pixel
is performed its results are discussed.
Finally, chapter 5 shows conclusions and future work.
4
Chapter 2
Theoretical Background on Solid-State
Image Sensors
2.1 Introduction
In this chapter, the human perception of light and its similarity with solid-state image sen-
sors are described. Also a theoretical framework about solid-state imaging is given. The
chapter describes the imaging process using the semiconductor material as the photo-sensing
element, and includes the transmission and reection phenomena due to the opaque materials
used in todays fabrication processes. The chapter also illustrates the collection of photo-
generated carriers produced by the incidence of photons over the sensitive region.
The main pixel structures described includes the photo-sensitive elements available in a
standard CMOS technology. The photodiode structure is shown in detail because this element
is the most commonly used in the design of CMOS image sensors and it was selected as the
ideal sensing element in this work.
2.2 Human light perception
The human eye is capable of detecting light within a wavelength range of 370 nm to 730 nm.
This is due to the two type of photo-detection cells: the rods and the cones. Both cell types
are located at the retina; the rods are located at the periphery and the cones are concentrated at
its center. The rods are highly photosensitive but have poor color sensitivity, while cones are
highly color sensitive but poor photosensitivity. This means that rods are mainly used under
low-light conditions (scotopic vision) at expense of poor color perception and cones are used
at well-lit conditions and color perception is better (photopic vision). In dark environments,
the human eye can detect between 126 and 214 photons per second in a range of 650nm and
450nm wavelength, respectively, and at 555nm, it can detect 10 photons per second [1]. For
color sensitivity, rods are classied into L, M and S types, which have similar characteristics
of RGB color lters in image sensors having its center wavelengths of red at 565 nm, green
at 545 nm and blue at 440 nm, respectively. The solid-state image sensors developed using
5
silicon as the photo-sensitive element are suitable to detect light with similar characteristics
as the human eye.
2.3 The solid-state imaging process
A solid-state image sensor is a semiconductor device capable to convert an optical image that
is formed by an imaging lens into electric signals (current or voltage). An image sensor can
detect light within a wide spectral range: from x-rays to infrared wavelengths regions. This
is possible by tunning the detector structure and/or by employing a material that is sensitive
to the wavelength region of interest [11]. The process of converting light into an electrical
signal is depicted in Figure 2.1.
Photon
Transmission - Reection
Absorption / Convertion
Collection
Buering
Conversion
Processing
Interpretation
Pixel
Imager
System
Figure 2.1: Solid-state imaging process [1].
The imaging process starts at the pixel. Impinging photons pass through dielectric layers,
then are absorbed in pixel structures and converted into charges taking advantage of the pho-
ton energy. Those photogenerated charges are collected in a three dimension conned area,
then buered and read sequentially to an upper level of processing circuits.
The image sensor converts pixel signals into more meaningful signal type, and processes
it in such a way that todays signal processors could use and transport. Processing circuits
convert and process pixel readings to form images.
Finally, at the system level these images are again processed or interpreted for human or
machine use. All these processes are done at dierent levels as shown in Figure 2.1[1].
6
2.3.1 Absorption of light in semiconductors
When light strikes a semiconductor, the photons pass through multiple layers of dielectrics
before reaching the photo-conversion sites. Those dielectric layers are placed on top of the
solid-state material to isolate dierent functional layers such as multi-layer routing metals.
Some of the layers are opaque and some of them are transparent. Because each layer has
dierent optical properties, some portions of the impinging photons are reected and some
are absorbed, leading to quantum loss (Figure 2.2).
I
n
d
i
c
e
n
t
l
i
g
h
t
R
e

e
c
t
e
d
l
i
g
h
t
A
b
s
o
r
b
e
d
l
i
g
h
t
Figure 2.2: Transmission and reection of light in dielectric layers
Nowadays, silicon is the most widely used material in very-large scale integrated circuits
(VLSI) and is also suitable for visible-range image sensors because the band gap energy of
silicon ( 1.12 eV) matches the energy of visible wavelength photons [11]. This means that
photons with an energy higher than 1.12 eV could produce electron-hole pairs in the silicon
substrate and those pairs are called photo-generated carriers [9, 1].
The amount of photo-generated carriers in a material is described by means of its absorp-
tion coecient (), which is dened as the fractional change of light power when the light
travels through the material. The mathematical expression is given as follows:
() =
1

z
P
P
(2.1)
where is the wavelenght of the light,
P
P
is the fractional reduction of light power inside
the material and
z
is the distance traveled by the light. The absorption length L
abs
in a
semiconductor is dened as:
L
abs
=
1
(2.2)
Figure 2.3 shows the absorption depth of light for silicon at 300

K, depending on the
wavelength of the incident light. Photons that have shorter than 1100 nm wavelength are
7
elegible for silicon base imaging. Since the human visible range is in about 380-750 nm, the
absorption length lies within 0.038 to 8 m.
Figure 2.3: Silicon absorption length of light [2].
2.3.2 Charge collection
After photo-generated carriers are released, negatively charged electrons are separated from
positively charged holes using an electric eld by which electrons are collected and holes are
drained. The electric eld of a photodiode-based image sensor is produced at the depletion
region of the pn-junction as shown in Figure 2.4.
8
Vbias
p-substrate
- +
Depletion
Region
SiO2
n+
Figure 2.4: The photodiode structure
The number of the collected electrons is a measure of the amount of light dropped on the
photosensitive region of the pixel and the way to measure it is to integrate such charges in a
charge pocket and read the integrated charges at predetermined time intervals [1].
2.4 Photodiodes
There is a variety of photo-sensing elements that can be built using the silicon substrate and
the most commonly used is the pn-junction photodiode [1, 11, 9]. In this work, the photodiode
was studied as the sensing element for the design of the CMOS image sensor.
2.4.1 Operation principle of photodiodes
The photodiode is a reverse biased p-n junction diode grounded at the p-type substrate with
a shallow n+ doped region. A bias voltage is applied to the n+ region to form a depletion
region around the metallurgical p-n junction. This depletion region is free of any charge be-
cause of the electrical eld formed in that region. Any electron generated in there slide at
the opposite direction of the electric eld towards the n+ region, while the holes go towards
the p- region. Electrons are collected in the charge pocket in the n+ region and the holes are
driven to ground, or they are recombined.
The main problem of photodiodes for CMOS image sensors is their low sensitivity in the
blue spectrum. This is because short wavelength photons (blue photons) are absorbed on the
surface of the silicon so they can reach the depletion region.
There is another type of photodiode which have improved the short wavelength response;
the pinned photodiode. This type of photodiode has been used in CCDs and CIS but its main
disadvantage is that it is not available for a standard CMOS process due to an extra p+ mask
9
that has to be used.
In a pn-junction diode, the forward current I
F
is expressed as
I
F
= I
di
_
exp
_
qV
nk
B
T
_
1
_
(2.3)
where q is the electron charge, k
B
is the Boltzmann constant, n is an ideal factor and I
di
is
the saturation current or diusion current, which is given by
I
di
= qA
_
D
n
L
n
n
po
+
D
p
L
p
p
no
_
(2.4)
where D
n,p
is the diusion coecient, L
n,p
is the difussion length, n
po
is the minority carrier
concentration in the p-type region and p
no
is the minority carrier concentration in the n-type
region and A is the cross-section area of the pn-junction photodiode. The output current of
the pn-junction photodiode is expressed as follows:
I
L
= I
ph
I
F
= I
ph
I
di
_
exp
_
qV
nk
B
T
_
1
_
(2.5)
where I
ph
is the photo-generated current.
There are three modes for biasing a photodiode: solar cell mode, PD mode and avalanche
mode [9]:
Solar cell mode. In the solar cell mode, no bias is applied to the PD. Under light
illumination, the PD acts as a battery that produces a voltage across the pn-junction. In
the open circuit condition, the voltage V
oc
can be obtained from I
L
= 0 A in Equation
2.5, and thus
V
oc
=
nk
B
T
q
ln
_
I
ph
I
di
+ 1
_
(2.6)
This shows that the open circuit voltage does not linearly increase according to the
input light intensity.
PD mode. The second mode is the PD mode. When a PD is reverse biased, that is
V < 0, the exponential term in Equation 2.5 can be neglected, and thus I
L
becomes
I
L
I
ph
+ I
di
(2.7)
In Equation 2.7 can be seen that in the absence of light (I
ph
= 0 A), there is only the
diusion current owing through the photodiode and as the light intensity increases, the
photo-generated current also increases linearly due to the electron-hole pairs generated
by the impinging photons.
10
Avalanche mode. The third mode is the avalanche mode. When a PD is strongly
biased, the photocurrent suddenly increases. This phenomena is called an avalanche,
where impact ionization of electrons and holes occurs and the carriers are multiplied.
The voltage where an avalanche occurs is called the avalanche breakdown voltage V
bd
.
The avalanche mode is used in an avalanche photodiode (APD).
2.4.2 The photodiode full-well capacity model
The collected charges are stored in the depletion region of the photodiode. The photodiodes
capacitance is related to the area and peripheral of diusion layer forming the pn-junction.
The junction capacitance of the reverse-biased photodiode si voltage dependent, so the deple-
tion capacitance is non-linear. Pn-junction capacitances are function of the applied terminal
voltage across the terminals and process parameters. This capacitance consists of two com-
ponents: the bottom plate capacitance and the sidewall capacitance.
The zero-bias junction capacitance per unit area associated with the bottom plate deple-
tion region of the photodiode is given by
C
J0
=
_

si
q
2
_
N
A
N
D
N
A
+ N
D
_
1

0
(2.8)
where
si
is the permitivity of silicon, q is the charge of the electron, N
A
and N
D
are the
doping concentrations for p-type and n-type materials, respectively and
0
is the junction
built-in potential which is given by

0
=
T
ln
_
N
A
N
D
N
2
i
_
(2.9)
where
T
is the thermal voltage (26mV at 300

K) and N
i
is the intrinsic carrier concentration
of the material, which is N
i
= 1.432 10
10
cm
3
for silicon.
With this, the junction area capacitance of the bottom plate region of the photodiode is
given by
C
J
=
A C
J0
_
1 +
V
PD

0
_
mj
(2.10)
where A is the area of the bottom plate pn-junction, mj is a grading factor specic for each
technology and V
PD
is the photodiodes reverse bias voltage. Similarly to Equation 2.8, the
zero reverse-bias sidewall junction capacitance per unit length is given by
C

J0SW
=
_

si
q
2
_
N
A
N
D
N
A
+ N
D
_
1

OSW
(2.11)
where
0SW
is the built-in potential for the sidewall junction. Considering the depth of the
pn-junction, x
J
, the sidewall junction capacitance per unit length is dened as
C
J0SW
= C

J0SW
x
J
(2.12)
11
With this, the total sidewall junction capacitance at zero bias can be calculated by mul-
tiplying C
J0SW
with the perimeter of the junction and the total junction capacitance for any
reverse bias voltage on the photodiode is given by
C
JSW
=
P C
J0SW
_
1 +
V
PD

0SW
_
mjsw
(2.13)
Finally, the total photodiode junction capacitance is calculated as follows:
C
PD
= C
J
+ C
JSW
(2.14)
2.5 CMOS Image Sensors
An image sensor consists of an imaging area, vertical/horizontal access circuitry and read-
out circuitry. The imaging area is formed by an array of pixels where each pixel contains a
photo-sensitive element and some transistors for accessing and buering the generated sig-
nals out of the array using the access and readout circuitry. The transistors included in the
pixel structure dene the type of the image sensor.
A pixel structure that includes, besides the photo-sensing element, only one access tran-
sistor, is called the passive pixel sensor (PPS) because there is no in-pixel amplication of
the photo-generated signal. This was the rst structure used in CMOS image sensors.
The second generation of CMOS image sensors. called active pixel sensor (APS), im-
proved the image quality due to a buer (source follower) that was included in the pixel
circuit to prevent destructive readout [12]. This type of pixel includes, in its most basic struc-
ture, three transistors: one used to take the photodiodes voltage to a known value, one for
accessing the pixel through the external circutry, and one more used as an in-pixel amplier.
This last type of pixel structure is the most widely used for image sensors today because of
its superior image quality when compared to passive pixel sensors. A detailed characteristics
description is illustrated in this work.
There is a novel type of pixel structure called digital pixel sensor (DPS), which includes
an in-pixel analog-to-digital converter. This structure, besides the tasks performed by the
APS, it also converts the photodiodes voltage into a digital signal which is read by an exter-
nal circuit.
2.5.1 CMOS pixel structures
Through time, the whole variety of photo-sensing elements have been studied and tested on
image sensors designs. The rst APS was fabricated using a photogate (PG) as the photode-
tector element. After that, the photodiode (PD) was used. The PG was rst implemented due
12
to ease of signal charge handling but its main problem was low sensibility due to the polysil-
icon in transistors gate is opaque to the visible spectrum. Today, the most used architecture
in CMOS image sensors is the APS using three transistors and a photodiode in a pixel (3T-
APS). In the rst stage of 3T-APS development, the image quality could not compete with
that of CCDs, with respect to both, xed pattern noise (FPN) and random noise [9] (noise
types are described in Appendix 6).
By incorporating a pinned PD structure used in CCDs, which has a low dark current and
complete depletion structure, the four transistor APS (4T-APS) has been successfully devel-
oped. This architecture has four transistors plus a PD and oating diusion in the pixel. The
implementation of the 4T-APS with correlated double-sampling (CDS) circutry reduces the
random noise. The main issue for 4T-APSs is the large pixel size when compared to the CCD
[9].
Figure 2.5 gives an overview of CMOS imager data published at IEDM and ISSCC over
the last 15 years. The bottom curve illustrates the CMOS scaling eects over the years, as
described by the International Technology Roadmap for Semiconductors. The second curve
shows the technology node used to fabricate the reported CMOS image sensors, and the third
curve illustrates the pixel size of the same devices [3].
Figure 2.5: Evolution of pixel size, CMOS technology node used to fabricate the devices and the
minimum feature size of the most advanced CMOS logic process [3].
As seen in Figure 2.5, CMOS image sensor are fabricated using processes behind the
ITRS processes. The reason for this is that very advanced CMOS processes are not imag-
ing friendly due to issues like large leakage currents, low light sensitivity, noise, etc. The
dierence between CMOS technology used for image sensors and ITRS technology is about
3 technology generations but, CMOS image sensor technologgy scales almost at the same
pace as standard digital CMOS processes do and also pixel dimension scales down with the
technology node used and the ratio is about a factor of 20 [3].
13
With the CMOS processes scaling down over the years, the design and fabrication of
smaller pixels result in a weaker performance and is a real challenge to improve the pixel de-
sign. Nevertheless, there are new innovations and techniques that improve the light sensitivity
of imagers like:
Dedicated processes with limited amount of metal layers
Thin interconnect layers and thin dielectrics
Micro-lenses
Light guide-waves on top of pixels
Back-side illumination
Recently, CMOS fabrication technology advances have successfully reduced the pixel
size of CMOS image sensors [13], although is still dicult to realize a smaller pixel size
than that of CCDs. Moreover, a pixel sharing technique has been widely used in 4T-APSs
because has been eective in reducing the pixel size to be comparable with that of CCDs [9]
and even with that of the conventional 35 mm lm cameras [11]. The main pixel structures
are described next.
Passive Pixel Sensor
The rst CMOS generation of image sensors was based on passive pixel sensors (PPS) with
analog readout. This sensors had poor signal quality due to the direct transmission of the
pixel voltage on capacitive column busses [12].
A passive pixel is formed by a combination of a photodiode and an addressing transistor
that act as a switch (Figure 2.6).
Figure 2.6: Passive CMOS pixel with a single in-pixel transistor [3].
In this pixel architecture, imaging starts with the light exposure of the photodiode, which
is reverse biased to a high voltage. During exposure time, photons impinging decrease the
reverse voltage across the photodiode and, at the end of exposure, the remaining voltage is
14
transmitted to the column bus. This remaining voltage is a measure of the amount of photons
falling in the photodiode during exposure time [3].
The main advantage of this architecture is the large ll factor, but unfortunately, the pixels
suers a large noise level as well, but the improvement of this was made with the next pixel
architecture, the active pixel.
Active Pixel Sensor
In this architecture, each pixel has an amplier, being the source follower (Figure 2.7). Each
pixel counts with a photodiode, a reset transistor, the driver for the source follower and the
addressing transistor. The current source of the source follower is placed at the end of the
column bus.
Figure 2.7: Active CMOS pixel based on in-pixel amplier [3].
In APS based image sensors, after exposure time, each pixel is addressed and the remain-
ing voltage across the photodiode is buered outside the pixel array by means of the source
follower, then the photodiode is reset.
This architecture solve a lot of noise issues but not the kTC noise component which is
introduced by resetting the photodiode.
Digital Pixel Sensor
With reduced feature sizes, more transistor per pixel can be added to the point where a sig-
nicant part of the pixel circuit is entirely digital. Today, the trend of image sensors moving
towards digital pixel sensors (DPS) [12], which is a novel pixel architecture in the design of
CMOS image sensors. In this devices, the conversion from analog photo-generated voltage
to digital data is implemented on-pixel, due to each pixel, besides a photodiode, it also counts
15
with a single slope ADC [14].
v
re f

+
Figure 2.8: Digital Pixel Sensor Architecture
In a CMOS image sensor based in this pixel architecture, the analog-to-digital conversion
is performed in parallel in every pixel and, therefore, readout time is signicantly less than a
single or per-column analog readout architecture, which permits very high frame rates (up to
10,000 frames per second) [14].
This architecture makes many applications feasible, specially the dynamic range enhance-
ment due to the possibility of combining two or more pictures taken with a very high rate. It
has been demonstrated that the more samples used for the composition, the better dynamic
range will be achieved, so DPS-based image sensors with its very high readout speed is the
perfect solution for this type of applications [14].
The main constraint of this architecture is that the use of multiple sampling to get a pic-
ture with high dynamic range consumes signicant power. Furthermore, an extra hardware is
required for implementing the multi-sampling algorithm, so the processing time is extended
[14].
The performance of a image sensor is constrained by factors like pixel full-well capac-
ity, sensor resolution, wafer/die size, quantum eciency, sensitivity and dark current. Pixel
size is limited by the reticle (die or wafer size), and quality of the supporting optics [1]. For
scientic image sensors, the two most important requirements are: a large full-well capacity
and low noise readout. The combination of these two requirements leads to a higher dynamic
range. Large pixel full-well capacity is only achieved through the use of novel fabrication
process and circuit design techniques. In photodiode type CMOS APS pixels, especially in
near-UV spectrum (200-400 nm), quantum eciency (QE) is improved using novel pixel
design techniques since it depends on the fabrication process technology and pixel design
technique [1].
The die size of a CMOS integrated circuit is limited by the exposure eld size of the
photolithographic stepper used during manufacturing which is typically 20mm by 20mm
[1]. However, with new technology in CMOS Image Sensor (CIS) manufacturing, so-called
stitching technology, now is possible to fabricate die sizes up to a single die per 200 mm
wafer using a 0.18 m CMOS process. The photolithographic stepper in the stitching process
16
exposes the entire image sensor structure, one piece at a time, by precisely aligning each
reticle step. The stitching technology allows to seam 5.5 m pixel sections into a large pixel
array, resulting in ultra-high resolution, high-quality color image sensors [15].
17
Chapter 3
State-of-the-Art on Microuidic Systems
and Image Sensors Integration
In this chapter is presented a revision of the state-of-the-art about image sensors designed
to monitor microuidic channels. Due to this work presents a design based on a standard
CMOS process, the articles reviewed in this chapter includes only image sensors designed
using this type of process. As will be seen through this revision, there is a variety of designs
which are specic depending on the characterization type and the specic task of the sensor.
In reference [4] is reported a digital 16-element mixed-signal, near-eld CMOS active
pixel optical sensor using 0.18 m CMOS technology. This optical sensor is coupled directly
to a microuidic channel employing either ip-chip or molded polymer packing technologies.
Such system is used to identify and quantify the biophysical or biochemical properties of
the cell population transported in the microchannel. The schematic diagram of the ip-chip
system is illustrated in Figure 3.1.
Figure 3.1: Integrated digital cytometer system components and architecture [4].
As seen in Figure 3.1, the microchannel was mounted over the optical sensor and the
generated signal is processed by the on-chip digital interface. Output signals are sent to a mi-
crocontroller for interpretation and nally displayed in a pocket PC. The Texas Instruments
MSP430F449 mixed-signal microcontroller was used to control and monitor the output of
the sensor and to interface to the Viewsonic VC37 pocket PC that acts as the host controller.
The microcontroller is an ultra low power, battery-operated, 16-bit RISC architecture which
allows portability of the entire system. The CMOS optical sensor designed for near-eld
microuidic integration is shown in Figure 3.2.
18
Figure 3.2: Photograph of the linear active pixel CMOS sensor [4].
The optical sensor was designed to be directly coupled to the microuidic channel fabri-
cated in glass or polymer as a modular add-on in order to enable the collection of particles
and the uid ow information. This device has seven electrical pads (left-hand side of the
gure) and seven mechanical pads (right-hand side of the gure) for ip-chip bonding sta-
bility. The output electrical properties, physical dimensions and technology specications of
the sensor chip are provided in Table 3.1 [4].
Table 3.1: Output characteristics and specications of the Linear Active Pixel Sensor
Linear Sensor Chip Specications
Technology 0.18 m
Dimensions 1.0 2.4 mm
Supply Voltage 1.8 V
Power Consumption 15 mW
Pads 5 dig / 2 pwr / 7 mech
Number of pixels 16
Pixel size 7 m 7 m
Fill Factor 75%
Dynamic Range 30 dB
Figure 3.3 shows a block diagram of the mixed-signal CMOS sensor architecture which
comprises the linear active pixel sensor array (APS), correlated double-sampling (CDS), and
an adaptive spatial lter (SF) with a digital control block for monitoring and conguration.
19
Figure 3.3: Flip-chip on glass illustration of a hybrid microuidic digital cytometer. [4].
The optical sensor chip was wire-bonded to a PCB and subsequently encapsulated in poly-
dimethylsiloxane (PDMS) beneath 120 m diameter cylindrical microchannel passing over
the sensors active area. The cross-section diagram for this structure is depicted in Figure 3.4
[4].
Figure 3.4: PDMS cast chamber, shown in a cross-sectional view, realized a microuidic channel
passing through the structure and over the active area of the sensor chip which is wire-
bonded to a PCB. [4].
While the assembly process of the system proved to be mechanically simple and cheap to
produce, the reliability of the device presents some issues specically in the region where the
microchannel passes over the chip surface. In this region, the technique used for forming the
microchannel resulted in some tearing of the PDMS which results in mechanical instability.
Furthermore, after extensive handling, prototypes eventually succumbed to wire-bond sepa-
ration, rendering the devices electricalle non-functional.
In contrasts to reference [4], where a single row APS array was used, in [5] a double
linear array was used, which makes possible not only detection, but also the determination
of particle velocity and size, which means that the sensor can be used to characterize cells as
well as count them. The active area of the new optical sensor consist of two linear arrays of
16 elements with each pixel measuring 7 m 7 m (see Figure 3.5).
20
Figure 3.5: The photodiode pixel linear arrays. [5].
In the same way than the die fabricated in [4], the pads located on the left-hand side of
the chip are the electrical interface pads, and the pads on the right-hand side are electrically
inactive and provide ip-chip bonding stability only. The chip bonding on the glass substrate
is designed to ensure that the active area of the sensor properly aligns to the microchannel of
the microuidic substrate after bonding. Figure 3.6 shows the CMOS sensor coupled to the
microuidic chip [5].
Figure 3.6: Post bond image of the CMOS sensor to the microuidic chip. [5].
From Figure 3.6, as an individual particle is transported over the active area of a pixel, the
light intensity received by the photodiode changes. This change manifests as an input current
change in the pixel which gives rise to a rapid change in the output voltage of the sensor. In
the dual photodiode-photodiode pixel array conguration, such perturbations in voltage as a
particle passes over the active area of the sensors, give rise to a characteristic double-pulse
signature. Thus by monitoring the output of the sensor, and suitably tracking the presence of
double pulses, the detection of particles is enabled. Figure 3.7 shows the output of the sensor
during the transit of a 6 m polystyrene polysphere. As the particle passes over the rst APS
array, the rst negative-going pulse is generated, and as it passes over the second APS array,
the second negative-going pulse is generated.
21
Figure 3.7: Plot of the CMOS sensor output upon detection of a 6 m polystyrene polysphere. [5].
The negative-pulse width and time interval between pulses are the features of the detected
signal, and is sensitive to the particle size and uid ow rate. The average negative-pulse
width increases as the particle size increases, assuming the uid ow rate is invariant. and
the time period between two consecutive pulses is inversely proportional to the particle ve-
locity and uid ow rate is independent of particle size.
Ji et al. developed an optical image sensor called contact imager in order to manipulate
individual cells using on-chip micro-actuators [6]. This sensor was designed using a 0.5 m
CMOS technology with a pixel pitch of 8.4 m and is capable of providing a 2D image of the
monitored cells. The designed pixel was intended to be minimum size, so in order to avoid
Nwell spacing requirements, a N+Psub photodiode was used. Also, to reduce the number of
contacts, there is only one Vdd contact per pixel which is shared by the source follower input
transistor of one pixel and the reset transistor of another with this, the ll factor is 17%. The
contact imager consists of a 9696 APS array, row and column scanners, column-wise read-
out circuits and buers and switches for input control and clock signals. Figure 3.8 shows
the schematic diagram for the CMOS APS.
Figure 3.8: A schematic of photodiode type CMOS active pixel sensor. [6].
22
The major characteristics of the chip are summarized in Table 3.2.
Table 3.2: Summary of sensor performance
Process AMI05 (SCMOS design rule, = 0.35 m)
Power supply 5 V
Maximum signal 1.2 V
Conversion gain 22 m/e
Pixel noise = 2.5 mV over 2 ms
Dynamic range 53.6 dB
Dark signal 0.46 V/sec
The chip was tested as a contact imager using microbeads placed directy on the chip
surface (Figure 3.9), then after bio-compatible material packaging to protect the bonds and
wires, the chip was tested with cells. Figure 3.9 shows the image acquired from the contact
imager using dry polymer microspheres of diameter 16 mplaced directly on the chip surface.
Figure 3.9: Comparison of images of microbeads on chip surface taken by (a) a camera and (b) the
contact imager. An overlapped view is also shown in (c). [6].
A most recent version of the contact imager was published in [7]. This work shows a
256 256 four-transistor pixel array. The new active pixel has a 5 m 5 m area with a
ll factor of 31%. One of the improvements of this new pixel was that the pixel is able to
operate at dierent modes which are selected by some control signals for either reset noise
suppression or dark current reduction. The pixels electronic circuit is shown in Figure 3.10.
23
Figure 3.10: Schematic diagram of the modied active pixel circuit. [7].
Recent eorts have resulted in the development of lab-on-a-chip systems in which it is
possible to perform a wide variety of tests using microuidics. Also, it has been demonstrated
that exists the possibility of designing and fabricating a CMOS optical sensor capable of be-
ing coupled to either a microuidic channel or a plane surface where particles are suspended
in order to be detected identied and monitored, avoiding with this, the need of expensive
and bulky microscopes. Furthermore, with the integration of smart on-chip functions is now
possible not only to detect, but also to identify, monitor and even characterize the suspended
particles. The goals are pursued due to the need of having highly automated testing plat-
forms to enable robust, low-cost analysis in order to eliminate the conventional laboratory
equipment, which is roughtly automated.
24
Chapter 4
Active Pixel Sensor Modeling and
Simulation
In this chapter, the design methodology for the design of an Active Pixel Sensor is presented.
It begins with the read-out circuit that consists of the reset transistor, buer transistor as part
of the source follower amplier and the selection transistor. There are also determined the
characteristics of the active load that is located at the bottom of the pixel array and which,
together with the buer transistor located in-pixel, forms the source follower amplier that
brings the output signal out of the array.
The electrical and physical characteristics of the pn-junction photodiode are determined
and compared to an ideal photodiode simulated using a capacitor and a current source. The
source terminal of the reset transistor is designed as the pn-junction photodiode by sizing its
area and perimeter in order to obtain the required capacitance.
4.1 Introduction
In microuidics research, a 640480 image sensor pixel resolution is well suited for particle
tracking and parameter-determination. On the other hand, at a xed resolution, the random
noise introduced in the image is inversely proportional to the image sensor image size. This
is, less random noise will be introduced to a 2/3

sensor (which actual size is 8.8mm

6.6mm) than a 1/8

sensor (actual size: 1.6mm 1.2mm) if both have the same number of
pixels. This is because the photo-sensitive area on a pixel is larger on a larger image sensor,
so more electron-hole pairs can be generated because of more photons have the possibility to
impinge such a area. For a larger count of photo-generated carriers, a greater voltage is gen-
erated, so the introduced noise is less representative for that signal. If the generated voltage
is comparable to the random noise signal, the amplied signal will have a signicant amount
of noise.
Another important parameter in the noise-inmunity for a image sensor is the full-well
25
capacity, which is the amount of charge that an imaging pixel could collect and transfer. This
parameter is limited by the size of the photoconversion region and by the read-out circuits
ability to buer pixel signals [1].
4.2 Pixel read-out circuit
4.2.1 Reset transistor M
RST
The read-out circuit of a three-transistor, single active pixel is shown in Figure 4.1. There
are three in-pixel NMOS transistors and a load transistor at the bottom including the load
capacitor.
V
DD
M
RST
V
RST
C
PD
I
PD
V
PD
M
SF
M
SEL
V
SEL
M
COL
V
BIAS
V
OUT
C
COL
10 pF
Figure 4.1: 3T pixel conguration
The transistor M
RST
is used to set the photodiode to a known voltage value through signal
V
RST
. This device is usually sized to have the minimum allowable feature size in order to
maximize the pixels ll factor and to reduce the charge injection to the photosensitive area
after reset [1]. In the case of the CMOS process used in this work, the minimum feature size
is W/L = 0.4m/0.35m.
The threshold voltage for an NMOS transistor is given by
V
TH
= V
TH0
+ K
1
_ _

s
+ V
S B

_

s
_
+ K
2
V
S B
+ V
TH
(4.1)
where V
TH0
is the zero back-gate bias threshold voltage; K
1
and K
2
are the body-eect coef-
cients, V
TH
is the term that contains short channel eects, and V
SB
is the applied voltage
26
between source and bulk terminals.
s
is the surface potential and for short channel is given
by

S
=
2kT
q
ln
_
N
CH
N
i
(T)
_
= 0.86440 V (4.2)
where k is Boltzmann constant, T is room temperature (300

K), q is the charge of the elec-

tron, N
CH
is the channel doping concentration and N
i
(T) is the temperature dependend intrin-
sic carrier concentration of silicon.
Although equation 4.1 is used by the simulation tools to determine the thresold voltage,
reference [1] gives a new equation more suitable for hand-calculations. Such equation takes
two tting-coecients (
1
and
2
) to approximate VTH on Equation 4.1 as a linear equation:
V
TH
= V
TH0
+ K
1
(1 +
1
)
_

s
+ V
S B
K
1
(1 +
2
)
_

s
+ K
2
V
S B
. (4.3)
From the BSIM3v3 model card for the n-channel device, the zero-bias threshold voltage
was found to be V
TH0
= 0.4979 V, the rst-order body eect coecient K
1
= 0.50296 V
1
2
and the second-order body eect coecient K
2
= 0.033985.
Using the conguration depicted in Figure 4.1, the V
TH
term was obtained through
simulation. A minimumsize reset transistor and a test current source were used to charge and
discharge the junction capacitance of the photodiode. The body-factor term was calculated
as

s
+ V
S B
. Results are shown in Figure 4.2, where V
TH
term is plotted as a function of
the body-factor term.
0.8 1 1.2 1.4 1.6 1.8 2 2.2
0.12
0.1
0.08
0.06
0.04
0.02
0
0.02
0.04
Body Factor term
D
e
l
t
a

t
e
r
m

(
V
)
Figure 4.2: Linear approximation of V
TH
term as a function of the body-factor term

s
+ V
S B
From the linear regretion of V
TH
, the two tting function coecients (
1
and
2
) were
found. Coecient
1
corresponds to the slope of the linear approximation and coecient
2
corresponds to the oset. The values for these two coecients are

1
= 0.111665

2
= 0.123019
27
Using Equation 4.3 is possible to calculate the threshold voltage for any V
S B
value. The
photodiode reset voltage can be found using Equation 4.4.
V
PD RST
= V
SB M1
= V
RST
V
TH RST
=
2

S
(4.4)
where
= +
_

2
+
2
_
1 +
2
_
1 +
1
_

S
+
S
+
2 (V
RST
V
TH0
)
K
1
(1 +
1
)
and
=
K
1
_
1 +
1
_
2(1 + K
2
)
.
With these equations and using a reset pulse V
RST
= 3.3 V on the gate of the M
RST
device,
the photodiode reset voltage was found to be V
PD RST
= 2.43 V, which means that more than
the 26% of the signal range is lost because of the increased threshold voltage of M
RST
.
From the previous results and using Equation 4.4, the threshold voltage of M
RST
can be
easily calculated:
V
TH RST
= V
RST
V
PD RST
= 3.3 2.43 = 0.87 V
Through simulation, the threshold voltage of the reset transistor was found to be V
TH RST
= 0.931 V
for the same conditions; this gives a 6.5% calculation error for the threshold voltage and a
3.7%calculation error for the reset voltage of the photodiode which has a value of V
PD RST
= 2.34 V
in simulation.
One way to recover the voltage loss is to boost the reset pulse to a value above the power
supply voltage [suat]. The boosting factor (B) is a fraction of the zero-bias voltage threshold
of M
RST
and is a function of the power supply voltage (V
DD
) and the minimumchannel length
available in the technology (L
min
) and can be calculated using the Equation 4.5:
B =
V
DD
L
min
+ 1.5
4
(4.5)
which, for a 3.3 V supply voltage and 0.35 m minimum channel length, gives a boosting
factor B 1.79. With this, the required reset pulse that allows a 3.3 V photodiode reset
voltage is
V
RST
= B V
TH0
+ 3.3 = 4.2 V
From simulation and using a reset pulse of V
RST
= 4.2 V, the reset voltage of the photo-
diode gives V
PD RST
= 3.12 V. The optimum value was determined to be V
RST
5 V for
V
PD RST
= 3.3 V. Figure 4.3 shows the obtained results.
28
0 0.5 1 1.5 2 2.5
x 10
6
1
0
1
2
3
4
5
Time [s]
V
o
l
t
a
g
e

[
V
]
Photodiode reset voltage for different reset pulse amplitudes


Reset pulse
Photodiode reset voltage
Figure 4.3: Boosted V
RST
and resulting V
PD RST
4.2.2 Source Follower Amplier
After integration time, the remaining photodiode voltage is buered by the source follower
(common-drain) amplier. From Figure 4.1, device M
SF
acts as a buer and M
COL
as a cur-
rent sink; these two devices form the source follower when both are working on saturation.
Such amplier has a low voltage gain (slightly less than 1), a high current gain and is used to
drive the capacitive load encountered at the end of each column of pixels.
The minimumoutput voltage of the source follower amplier is determined by the thresh-
old voltage of the buer device, V
TH SF
, since for a lower voltage values than that, the buer
device is turned o. On the other hand, the maximum output voltage is considerably lower
than V
DD
because of the body eect which causes V
TH SF
to increase as the output voltage
increases.
The output voltage range of the source follower amplier is determined by the threshold
voltage of the buer transistor, V
TH SF
, and by the column current biased by the load transistor
M
COL
. As mentioned before, the body eect present in the operation of the buer device
causes the output voltage to increase at a slower rate than the input signal, which means that
V
TH SF
increases with the output and so, the gain is lower than 1. This behavior is described
by Equation (4.6):
V
OUT
= V
PD
V
TH SF
(4.6)
where V
PD
is the voltage of the photodiode and V
TH SF
is the modulated threshold voltage of
the buer device M
SF
.
29
In order to determine the output voltage range of the source follower amplier, the relative
minimum voltage that can be buered by M
SF
was determined through Equation 4.7 [1]:
V
OUT
= V
SB SF
=
2

S
(4.7)
where
= +
_

2
+
2
_
1 +
2
_
1 +
1
_

S
+
S
+
2 (V
PD
V
TH0
)
1 + K
2
. (4.8)
An output voltage value of V
OUT
= 0 V in Equation 4.7 was set and it was found that
the absolute minimum photodiode voltage that can be buered by M
SF
is V
PD MIN0
= 0.48 V,
which is close to its zero-bias threshold voltage. Then, the absolute minimum photodiode
voltage was found by adding the eective voltage of the load transistor to V
PD MIN0
:
V
PD MIN
= V
EFF COL
+ V
PD MIN0
(4.9)
where V
EFF COL
is the eective voltage of the load transistor and is given by:
V
EFF COL
= V
GS COL
V
TH0
(4.10)
A bias voltage of V
GS COL
= 1 V was used to determine the size of M
COL
so, substituting
(4.10) into (4.9), the input voltage necessary for the source follower to operate linearly was
determined to be V
PD MIN
1 V.
The buer device, M
SF
, was set to the minimum aspect ratio in order to maximize the
pixels ll factor, that is, W/L = 0.4 m/0.35 m, and the load transistor, M
COL
, was de-
signed to sink a low bias current ( 1.5 A) in order to achieve the widest output voltage
range possible which also enables a reduced noise performance. A simulation analysis has
been performed in order to determine the optimumfeature size of M
COL
and results are shown
in Figure 4.4.
Figure 4.4 shows that for an input voltage of V
IN
1 V, the load transistor M
COL
with
an aspect ratio of W/L = 0.1 begins to operate in saturation at a lower bias current. For
greater feature sizes, drain current increases and saturation starts at a greater input voltage,
so the output voltage range is reduced, as can be seen from the output voltage plot 4.4. Also
through simulation was determined that for aspect ratios smaller than W/L = 0.1, the out-
put voltage range was incremented in a very low quantity and the size of the load transistor
occupies a larger area, so the optimumfeature size of M
COL
was determined to be W/L = 0.1.
From the results above was determined that, applying a boosted pulse to reset the photo-
diodes voltage level and biasing the source follower amplier with optimum column current
found through simulation, the output voltage range of the pixel is
V
PR
= V
DD
V
PD MIN
= 3.3 1 = 2.3 V (4.11)
This result is about the 70% of the photodiode voltage swing or a voltage gain of 0.7 V/V.
30
0 0.5 1 1.5 2 2.5 3 3.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
x 10
5
Input voltage [V]
D
r
a
i
n

s
o
u
r
c
e

c
u
r
r
e
n
t

[
A
]


W/L=0.1
W/L=0.25
W/L=0.5
W/L=0.75
W/L=1
0 0.5 1 1.5 2 2.5 3 3.5
0
0.5
1
1.5
2
2.5
Input voltage [V]
O
u
t
p
u
t

v
o
l
t
a
g
e

[
V
]


W/L=0.1
W/L=0.25
W/L=0.5
W/L=0.75
W/L=1
Figure 4.4: Source follower drain current and output voltage for dierent feature sizes of M
COL
4.3 Photodiode design
On a standard CMOS technology, the three types of photodiode that can be built:
N
di
P
sub
N
well
P
sub
P
di
N
well
4.3.1 Pn-junction capacitance
As a starting point in the design of the photodiode, it was found in the literature that for
scientic applications of Active Pixel CMOS image sensors, the typical charge pocket size
is between N = 100Ke

and N = 1Me

, so in this design a value of N = 1Me

was taken.
On the other side, the photodiodes voltage swing is V
PD
= 3.3 V, as shown in the previous
section.
The conversion gain of the photodiode necessary to reach such specications was deter-
mined to be: [1]
CG =
V
FD
N
=
3.3
1 10
6
= 3.3 V/e

. (4.12)
Therefore, the capacitance of the photodiode C
PD
is evaluated as follows:
C
FD
=
q
CG
=
1.602 10
19
3.3 10
6
50 fF. (4.13)
31
0 0.01 0.02 0.03 0.04 0.05 0.06
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5


X: 0.03299
Y: 2.137
X: 0.001999
Y: 3.3
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
Reset signal
Dark response
Figure 4.5: Photodiode response at dark environment at 33ms integration time
A simulation test was performed in order to determine the photodiodes capacitance per-
formance for dierent light levels and sampling rates. The testing circuit includes the reset
transistor (M
RST
), the calculated capacitance of the photodiode (C
PD
) represented by an ideal
capacitor and a test current source (I
PD
) which represents the photo-generated carriers on the
depletion region of the photodiode.
Figure 4.5 shows the simulation results for a dark environment which is represented by
setting I
PD
= 0 A. It was determined that under this conditions, a leakage current discharges
the photodiode about 1.2 V. Using Equation (4.12) was found that the number of electrons
accumulated by the leakage eect is
N
dark
=
3.3 2.137
3.3 10
6
= 350 Ke

.
So the dynamic range of the pixel at this sampling rate is
DR = 20 log
_
1 10
6
350 10
3
_
= 9 dB
The charge distribution also aects the pixel performance by decreasing the pixel voltage
when the reset device turns o. Figure 4.6 is a close up to Figure 4.5 at the time when
M
RST
turns o. It can be seen that the remaining electrons in the channel discharges the
photodiodes capacitance about 12 mV.
32
1.9975 1.998 1.9985 1.999 1.9995 2 2.0005 2.001 2.0015
x 10
3
3.286
3.288
3.29
3.292
3.294
3.296
3.298
3.3
3.302


X: 0.001999
Y: 3.3
X: 0.002
Y: 3.288
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
Reset signal
Dark response
Figure 4.6: Charge distribution eect in the photodiodes capacitance
At the same lighting conditions, if the sampling rate is increased, the dynamic range
is also increased. This is because for shorter integration times, the photodiode is less time
exposed to the leakage current. In Figure 4.7 is shown that for a sampling rate of 300 samples
per second, the voltage reduction due to the dark current is of 0.197 V and the dynamic range
of the sensor is then increased to DR = 24.5 dB.
33
0 1 2 3 4 5 6 7
x 10
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5


X: 0.0001935
Y: 3.301
X: 0.0033
Y: 3.104
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
Reset signal
Dark response
Figure 4.7: Photodiode response at a dark environmet at 3.3ms integration time
The current required to completely discharge the photodiode for dierent sampling rates
was also determined. There were used sampling rates of 30, 300, 3,000 and 30,000 frames
per second. The width of the reset pulse in all cases is 30% of the total integration time and
a boosted amplitude V
RST
= 5 V was set. Simulation results are shown in Figure 4.8.
Simulation results on Figure 4.8 shows that the maximum photodiode voltage swing
(V
PD
= 3.3 V) was reached in all cases. The current necessary to discharge the photodi-
ode capacitance, C
PD
, in a) is I
PD
6 pA, in b) is I
PD
55 pA, in c) is I
PD
550 pA and in d)
I
PD
5.5 nA. Due to each time the integration time is shorter, a bigger current is necessary
to discharge the same capacitance.
4.3.2 Physical characteristics
Figure 4.40 in [1] shows that for a charge pocket of 1Me

, the pixel pitch using a standard

0.35 m technology is about 17 m, which gives a pixel ll factor between 15% and 45%,
depending on the photodiode architecture and design rules of each specic foundry.
The total junction capacitance of the photodiode as a function of the area and perimeter
is given by
C
PD
=
C
J
A
_
1
V
PD

B
_
MJ
+
C
JSW
P
_
1
V
PD

BSW
_
MJSW
(4.14)
where C
J
and C
JSW
are the unit zero-bias area and peripheral junction capacitances, A and
34
0 0.01 0.02 0.03 0.04 0.05 0.06
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
a)


Reset signal
I
PD
=6pA
0 1 2 3 4 5 6 7
x 10
3
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
b)


Reset signal
I
PD
=55pA
0 2 4 6 8
x 10
4
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
c)


Reset signal
I
PD
=550pA
0 1 2 3 4 5 6
x 10
5
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
d)


Reset signal
I
PD
=5.5nA
Figure 4.8: Full discharge of the 50 fF ideal capacitance at a) 30 frames per second, b) 300 frames per
second, c) 3,000 frames per second and d) 30,000 frames per second.
P are the area and perimeter of the photodiode,
B
and
BSW
are the built-in potentials of
area and side-wall junctions, M
J
and M
JSW
are the junction grading coecients of area and
side-wall junctions and V
PD
is the photodiode junction voltage.
Equation (4.14) was solved for an square-shaped photodiode and it was determined that
for an area A
PD
= 100 m
2
and a perimeter P
PD
= 40 m, the capacitance of the photodiode
is C
PD
= 58.44 fF, which represents a 16.8% greater capacitance than the dened for a 1Me

charge pocket using an ideal capacitor.

According to the design rules of the CMOS process used in this design, the area and
perimeter for a minimum feature size transistor are, respectively,
A
MIN
= 0.45 m 0.4 m = 0.18 m
2
(4.15)
P
MIN
= 2 0.45 m+ 2 0.4 m = 1.7 m (4.16)
As an example (not optimized area), Figure 4.9 shows an active pixel using the designed
square-shaped photodiode and minimum size transistors. In this gure, the source terminal
of the reset transistor was set as the photo-sensitive area. This is achieved by exposing such
region to light by avoiding all superior layers (metal layers) to overlay the n-active surface of
the transistor.
35
Figure 4.9: Layout example of a square-shaped photodiode including on-pixel transistors
With this, a new simulation test was set, but now the ideal capacitor used before was
removed and instead of it, the area and perimeter of both drain an source terminals of the
M
RST
transistor were included in the Spice deck. Table 4.1 shows the physical parameters set
for M
RST
in simulation.
Table 4.1: Physical parameters of M
RST
for simulation of a photodiode with capacitance
C
PD
= 58.44 fF.
Physical parameter Value
Width 0.4 10
6
Lenght 0.35 10
6
Drain area 0.18 10
12
Drain perimeter 1.7 10
6
Source area 100 10
12
Source perimeter 40 10
6
36
In the rst run of the simulation, a test current I
PD
= 0 A was set in order to determine
the dark current and charge distribution eects on the pn-junction photodiode. Figure 4.10
shows the simulation results.
0 0.01 0.02 0.03 0.04 0.05 0.06
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5


X: 0.03299
Y: 2.252
X: 0.001999
Y: 3.3
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
Reset signal
Dark response
Figure 4.10: Pn-junction photodiode response at dark environment at 33ms integration time
Then, as done before, the number of electrons that discharges the photodiodes capaci-
tance at the absense of light was calculated:
N
dark
=
3.3 2.252
3.3 10
6
= 317 Ke

,
and the dynamic range of the pixel at 30 frames per second is
DR = 20 log
_
1 10
6
317 10
3
_
= 10 dB
As in Figure 4.6, Figure 4.11 shows the charge distribution eect on the pn-junction
photodiode. It can be seen that the total voltage discharge is about 10 mV.
37
1.985 1.99 1.995 2 2.005 2.01
x 10
3
3.285
3.29
3.295
3.3
3.305


Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
X: 0.001999
Y: 3.3
X: 0.002
Y: 3.29
Reset signal
Dark response
Figure 4.11: Charge distribution eect on the pn-junction photodiode
A slightly decrease can be appretiated on the number of electrons accumulated due to
the dark current when compared to the ideal capacitor and the dynamic range increases 1
dB. A more signicant increase in the dynamic range is described when the sampling rate is
increased as shown in Figure 4.12.
0 1 2 3 4 5 6 7
x 10
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5


X: 0.0001999
Y: 3.299
X: 0.0033
Y: 3.129
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
Reset signal
Dark response
Figure 4.12: Pn-junction photodiode response at dark environment at 300 frames per second
38
For a 300 frames per second sampling rate, the voltage reduction due to the dark current
is 0.170 V which means a reduction of 15% when compared to the ideal capacitance; the
dynamic range this time is 25.8 dB, which represents a increase of 5% when compared to the
ideal 50 fF capacitance.
The current necessary to completely discharge the pn-junction capacitance for dierent
sampling rates was also determined through simulation. Figure 4.13 shows that more current
is needed in this case due to the increased capacitance of the photodiode.
0 0.01 0.02 0.03 0.04 0.05 0.06
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
a)


Reset signal
I
PD
=7.5pA
0 1 2 3 4 5 6 7
x 10
3
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
b)


Reset signal
I
PD
=70pA
0 2 4 6 8
x 10
4
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
c)


Reset signal
I
PD
=700pA
0 1 2 3 4 5 6
x 10
5
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
d)


Reset signal
I
PD
=7nA
Figure 4.13: Full discharge of the square-shaped N
DIFF
P
SUB
photodiode with a C
PD
= 58.44 fF pn-
junction capacitance at a) 30 frames per second, b) 300 frames per second, c) 3,000
frames per second and d) 30,000 frames per second
Table 4.2 shows the current values for a full discharge of both capacitances, ideal and
pn-junction, for dierent sampling rates and the percent error between these two cases. As
can be seen, the maximum error is about 27.3% and ocurrs at the higher sample rates.
Table 4.2: Simulation results and percentage error of the full-discharge current of the ideal and the
pn-junction capacitances.
Sample rate [fps] Ideal [pA] p-n junction [pA] Error [%]
3 6 7.5 25
30 55 70 27.3
300 550 700 27.3
3000 5500 7000 27.3
39
The ideal capacitor was then xed to the calculated pn-junction capacitance and a new
simulation was set in order to determine the percentage error using the same capacitance
value. With this, the charge capacity of the ideal photodiode is the same as the pn-junction
photodiode. Figure 4.14 shows the simulation results.
0 0.01 0.02 0.03 0.04 0.05 0.06
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
a)


Reset signal
I
PD
=7pA
0 1 2 3 4 5 6 7
x 10
3
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
b)


Reset signal
I
PD
=65pA
0 2 4 6 8
x 10
4
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
c)


Reset signal
I
PD
=650pA
0 1 2 3 4 5 6
x 10
5
1
0
1
2
3
4
5
Time [s]
P
h
o
t
o
d
i
o
d
e

v
o
l
t
a
g
e

[
V
]
d)


Reset signal
I
PD
=6.5nA
Figure 4.14: Full discharge of the ideal photodiode with a C
PD
= 58.44 fF capacitance at a) 30 frames
per second, b) 300 frames per second, c) 3,000 frames per second and d) 30,000 frames
per second
The currents needed to completely discharge the capacitance of the ideal photodiode
changed with respect to the pn-junction photodiode, although the percentage error was re-
duced considerably. This is shown in Table 4.3.
Table 4.3: Simulation results and percentage error of the full-discharge current of the ideal and the
pn-junction capacitances for the same capacitance values.
Sample rate [fps] Ideal [pA] p-n junction [pA] Error [%]
3 7 7.5 7.1
30 65 70 7.7
300 650 700 7.7
3000 6500 7000 7.7
The maximum percent error in this case is 7.7% which is considerably lower than the
27.3% of the 50 fF capacitance.
40
4.4 Pixel array simulation
A pixel array was simulated using the active pixel sensor designed on the previous sections
and the corresponding control signals for vertical and horizontal accessing. The pixels were
distributed in four rows and ve columns (4 5) and each pixel in a row shares the reset and
select signals so the read-out was performed one row at a time.
At the bottom of each column was placed an nmos device acting as the active load of the
buer transistor of each pixel. Such load was biased with a voltage source in order to set a de-
termined drain current and a capacitive load of 5 fF was connected at the output each column.
4.4.1 Simulation setup
Each pixel has a pn-junction photodiode with a capacitance of 58.44 fF, as designed in section
4.3.2, and its corresponding reset, buer and select transistors (see Figure 4.1). As mentioned
before, at the end of each column is placed the active load device and at the output of each
column is connected a capacitive load of 5 fF.
PHOTODIODE
VOLTAGE
RESET
SELECT
Integration time
Figure 4.15: Timing signals for accessing and read-out pixels
The timing signals of the pixel array are shown in Figure 4.15. As can be seen in this
gure, a reset pulse is applied to the photodiode to set the voltage across its terminals to a
known value. Once the reset device is turned o, the integration time starts until a new reset
pulse is applied. During integration time, the photodiode is oated and electron-hole pairs are
generated on the depletion region of the junction depending on the light intensity and wave-
length of the photons. The select signal is applied just a moment before and during the reset
pulse so the voltage variation on that time lapse can be amplied, measured and sampled.
41
PIXEL ARRAY
R
E
S
E
T

&

R
O
W

S
E
L
E
C
T

S
I
G
N
A
L
S
READ-OUT
VERTICAL ACCESS OUTPUT
Figure 4.16: Active pixel sensor array including horizontal, vertical and read-out circuitry
The control signal were set using voltage sources on simulation. There were set four reset
signals, one per each row of the array, although just one reset signal could be applied to all
the pixels since this event occurrs at the same time for all the pixels in the array. The select
signals were set on the same way so the read-out could be done row per row.
Although it was not included in the simulation, the horizontal access circuitry of Figure
4.16 includes the conditioning circuits that prepares the analog signals to be converted to its
digital version so they can be interpreted out of the sensor easily.
There were set 20 current sources to emulate the impinging photons on each pixel. The
values of each current source were chosen randomly.
4.4.2 Results
Simulation results of the pixel array are shown next. In Figure 4.17 are depicted the control
signals and the output voltage for one of pixels included in the array. In this case, a source
current of I
PD
= 2.3 pA was randomly set. As can be seen, the reset pulse has 5 V amplitude
which sets the voltage of the photodiode to 3.3 V. When integration time has nished, voltage
of the photodiode has discharged from its reset value to 1.573 V for an integration time of 33
ms.
42
0 0.01 0.02 0.03 0.04 0.05 0.06
0
2
4
6


X: 0.001999
Y: 5
V
o
l
t
a
g
e

[
V
]
0 0.01 0.02 0.03 0.04 0.05 0.06
0
2
4
6


X: 0.001999
Y: 5
V
o
l
t
a
g
e

[
V
]
0 0.01 0.02 0.03 0.04 0.05 0.06
0
1
2
3
4


X: 0.03299
Y: 1.573
X: 0.001999
Y: 3.3
V
o
l
t
a
g
e

[
V
]
0 0.01 0.02 0.03 0.04 0.05 0.06
0
1
2
3


X: 0.03279
Y: 1.117
X: 0.001999
Y: 2.34
V
o
l
t
a
g
e

[
V
]
0 0.01 0.02 0.03 0.04 0.05 0.06
2
0
2
4


X: 0.001999
Y: 2.338
Time [s]
V
o
l
t
a
g
e

[
V
]
X: 0.03279
Y: 1.117
Reset pulse
Select pulse
Photodiode voltage
Source follower voltage
Output voltage
Figure 4.17: Simulation results for a single pixel of the 4 5 array. From top to bottom: Reset pulse,
Select pulse, Photodiode voltage, Source follower output, Column output.
In section 4.2 was determined that using a boosted reset pulse of 5 V, the photodiodes
reset voltage could be set to 3.3 V (Figure 4.3). Also, it was determined that the source fol-
lower amplier has a voltage gain of 0.7 V/V and that output voltage range for this amplier
was 2.3 V (Equation 4.11).
In this simulation, the maximum voltage at the output of the the source follower amplier
is at the beginning of the integration time, which is 2.34 V and the gain at this point of time
is
A
SF
B
=
2.34
3.3
= 0.71
and the gain at the end of the integration time is
A
SF
E
=
1.117
1.573
= 0.71.
With this, the design parameters obtained previously are demonstrated to be correct by
means of the simulation of a complete pixel as part of a pixel array.
43
In order to demonstrate the performance of the array, a complete exposition was simu-
lated. Figure 4.18 shows four reset pulses, one for each row, and the corresponding row select
signals. In this simulation, one row was selected for each reset pulse applied to the entire ar-
ray, so the output shows the buered signal of each row when a reset pulse is applied.
0 0.02 0.04 0.06 0.08 0.1 0.12
0
5
V
o
l
t
a
g
e

[
V
]


Reset
0 0.02 0.04 0.06 0.08 0.1 0.12
0
5
V
o
l
t
a
g
e

[
V
]


Row 1
0 0.02 0.04 0.06 0.08 0.1 0.12
0
5
V
o
l
t
a
g
e

[
V
]


Row 2
0 0.02 0.04 0.06 0.08 0.1 0.12
0
5
V
o
l
t
a
g
e

[
V
]


Row 3
0 0.02 0.04 0.06 0.08 0.1 0.12
0
5
V
o
l
t
a
g
e

[
V
]
Time [s]


Row 4
Figure 4.18: Vertical control signals: Reset pulses and row selection
In Figure 4.19 the output signals for each row are shown. The reading of the signals
is actually done in parallel for each column, so at 1 ms, there are ve pulses, one for each
column, and all those pulses are read at the same time. Then, at 3 ms, the second reading
takes places and so on until the four rows are read.
44
0 0.02 0.04 0.06 0.08 0.1 0.12
2
0
2
4
V
o
l
t
a
g
e

[
V
]


0 0.02 0.04 0.06 0.08 0.1 0.12
2
0
2
4
V
o
l
t
a
g
e

[
V
]


0 0.02 0.04 0.06 0.08 0.1 0.12
2
0
2
4
V
o
l
t
a
g
e

[
V
]


0 0.02 0.04 0.06 0.08 0.1 0.12
2
0
2
4
V
o
l
t
a
g
e

[
V
]


0 0.02 0.04 0.06 0.08 0.1 0.12
2
0
2
4
V
o
l
t
a
g
e

[
V
]
Time [s]


Column 1
Column 2
Column 3
Column 4
Column 5
Figure 4.19: Output signals of the pixel array
According to the results presented in this chapter, it can be assumed that the design pa-
rameters and simulation results obtained are correct from a simulation point of view.
45
Chapter 5
Conclusions and future work
This work presented the main pixel architectures used today in the design of CMOS image
sensors. Based on literature, the more suitable architecture for scientic applications was
chosen and analysed. The CMOS active pixel as part of a complete image sensor was studied
and a new design was presented. Also, a small array was simulated and results were reported.
The design presented on this work aims to the possibility of fabricate a CMOS image sensor
using the studied pixel architecture. Also, simulation results agree with must designs pre-
sented recently in literature.
A CMOS active pixel image sensor was designed. This task was made considering the
most common in-door lighting environments. The size of the on-pixel devices were chosen
to be the minimum feature size possible in order to maximize the pixels ll factor.
From the results obtained, it was found that the current necessary to fully discharge the
capacitance of the photodiode increases as the sampling rate increases, this is because the
well capacity needs to be lled in a shorter amount of time. In order to determine the op-
timum sampling rate of the sensor, it is necessary to perform tests at the laboratory where
illumination is controlled.
One important design issue found in this work is that both, the charge distribution and
the dark current considerably aects negatively the dynamic range of the sensor, so it is im-
portant to choose the optimum size of the reset transistor in order to reduce both eects as
low as possible. From simulation it was determined that the charge distribution eect is min-
imum when used a minimum feature size for M
RST
. This is because for a smaller channel,
less charge is retained and then distributed to the drain and source when the transistor goes
o. On the other side, it also was found that if the channel length of the reset transistor is
increased, so the channel resistance is also increased, a small reduction on the dark current is
obtained but the charge distribution eect is increased because of the bigger channel area.
The easiest way to reduce the dark current eect on the photodiode is to increase the sam-
pling rate of the sensor as shown in the design chapter, but it has to be considered the lighting
conditions because an increase in the sampling rate means that more light power is required
46
to expose correctly the subject.
Through simulation was also determined that the pn-junction photodiode, which has a
slightly higher capacitance than the 50 fF calculated for the 1 Me

charge pocket, describes

an improved behavior than the ideal capacitor including less photodiode discharge due to
dark current (32% versus 35% at 33ms integration time), reduced charge distribution eect
(3% versus 3.6%), and wider dynamic range by 1 dB. This results suggests that maximizing
the area and/or perimeter of the photodiode and hence the charge capacity, the dynamic range
will also increase, keeping the same pixel pitch.
Fixing the ideal capacitor to have the same value as the pn-junction capacitance, so the
charge capacity is equal for both devices, the percentage error was considerably reduced al-
though not equal, but this result gives a better insight for when the layout of the pixel be
designed.
At the end of this work, a simulation of a small pixel array was simulated using the control
signals typically used in a real sensor and the output signals of the array were obtained. The
APS array simulations were performed including only the pixel array and the control signals
were emulated using voltage sources.
It is also important to take in count that all the control circuitry including the access,
reset, and sampling circuits, must be manipulated externally, which means that a microcon-
troller can be used to set the sampling rates of the array, so depending on the application and
illumination conditions, such rates can be adjusted to obtain the ideal exposure and overall
performance.
Future work
The recommended future work to do based on the obtained results presented in this document
would be:
Adjust the size of the reset transistor in order to reduce the charge distribution to the
photodiode. In this work
Determine a range for the integration times through experimentation on the laboratory,
which also could reduce the dark currents if it is increased.
Maximize the ll factor of the pixel by adjusting the area and perimeter of the photodi-
ode. There has been demonstrated [1] that increasing the perimeter of the photodiode
by opening holes to the n-active surface, the full-well capacity of the pixel also in-
creases. Furthermore, the response to short wavelength photons, as is the blue photons,
also increases.
47
Design of the conditioning circuits to prepare the array signals to be converter to a
digital version, so the external readings can be performed eciently. This circuits
include sampling and hold, buering and ampling circuits.
Design of the control circuits for the pixel array including the vertical and horizontal
accessing circuits. The most common circuit used for this task is the shift register. As
mentioned, it is important to have external control of this circuits.
This work can be interpreted as a starting point in the task of designing a fully functional
CMOS image sensor. Experimentation is always necessary so it is important to fabricate test
chips to be able to compare simulation and real results. It is not essential to design the entire
sensor to know the sensor performance so is enough to design the array of pixels and test
it using external circuitry like a FPGA or a microcontroller together with an analog readout
interface and an ADC.
48
Chapter 6
Appendix A
Pixel
Basic photosensitive unit of an image sensor. It has the ability of collect photo-generated
charges and to restrict the location of charges to a discrete volume of space within the
silicon substrate. For CMOS image sensors, there are passive pixels and active pixels.
Passive pixel have a photosensitive region, reset and access transistors, while active
pixels have also counts with an preampling transistor.
Fill Factor
Ratio of the actual photosensitive area inside a pixel A
pd
, to the total pixel area, A
pix
.
That is, the percentage area of the photosensitive region with respect to the total area
of the pixel and it is given by:
Fill factor =
A
pd
A
pix
100 [%] (6.1)
Full-well capacity
Maximum number of electrons that can be collected and transferred by the photodiode.
This parameter is limited by the area and perimeter of the photodiode. The full-well
capacity is given by:
N
SAT
=
V
SAT
C
PD
q
(6.2)
where V
SAT
is the saturation voltage of the photodiode, q is the electron charge and C
PD
is the photodiodes pn-junction capacitance.
Dynamic range
Is dened as the ratio between the maximum signal (saturation level) that could be
imaged by a pixel and the noise level in dark conditions. It is expressed in decibels and
it is given by:
DR = 20 log
_
N
SAT
N
DARK
_
(6.3)
where N
DARK
is the number of electrons generated by the dark current of the pixel.
49
Resolution
Sensitivity
Ratio of the pixel output change (current or voltage) obtained after an exposure time to
the amount of light change that has a specic wavelength. The amount of light change
during the exposure time is given by Lux second:
R
ph
=
I
L
P
o
(6.4)
Quantum Eciency
The quantum eciency is dened as the ratio of the number of generated photocarriers
to the number of the input photons and is measured and dened at dierent wave-
lengths. The input photon number per unit time and the generated carrier number per
unit time are P
0
/(hv) and I
L
/q, respectively. Wavelength dependent quantum eciency

Q
() is given by:

Q
()
I
L
/q
P
0
/(hv)
= R
ph
hv
q
(6.5)
Dark current
Is the current present in the pixel when no light is incident over the photo-sensitive area.
It depends on the fabrication process, temperature, pixel architecture and operation
mode.
Fixed-pattern noise
It is a non-temporal, xed noise that can be seen on an image when a uniform illumi-
nation is present over the image sensor. This type of noise is originated by fabrication
variations on the devices present in the pixel and it can not be corrected after fabrica-
tion.
Temporal noise
It refers to time-dependent uctuations that are originated by the sensor devices. It
includes the thermal, shot and 1/f noise.
k
B
TC noise
Reset or k
B
TC is caused by uncertainty of the voltage on the photodiode capacitance
after pixel reset operation.
50
Bibliography
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[10] R. H. Nixon, S. E. Kemeny, B. Pain, C. O. Staller, and E. R. Fossum, 256 x 256 cmos
active pixel sensor camera-on-a-chip, IEEE Journal of Solid State Circuits, vol. 31,
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51
[13] H.-S. Wong, Technology and device scaling considerations for cmos imagers, IEEE
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52
Vita
Matias V azquez Pi n on was born on September 26
th
, 1984 in M exico City. He earned his
B.Sc. degree in Electronics and Communications Engineering on May, 2008 from the Insti-
tuto Tecnol ogico y de Estudios Superiores de Monterrey (ITESM), Campus Monterrey.
Since the beginning of his graduate studies, Matias have been working as teaching assis-
tant for the Department of Electrical and Computer Engineering. His research interests are
the design of optoelectronic and analog/mixed-signal devices with biomedical applications.
In addition to his thesis research, Matias have been working in collaboration with pro-
fessor Graciano Dieck Assad, Ph.D. on the rst edition of the e-book Simulation Practices
for Electronics and Microelectronics Engineering which is intended to support electronics
students by means of simulation practices using free and/or open-source software.
Permanent Address: Corregidora Sur #105,
Colonia Centro,
Matias Romero, Oaxaca, M exico.
C.P. 70300.
Email contact: a00783236@itesm.mx
vazquez.mp@gmail.com
This document has been typeset in L
A
T
E
X by Matias V azquez Pi n on.
53