Analog Behavioral Modeling

Sathishkumar Balasubramanian Senior Manager, Solutions Marketing, Cadence Technology on Tour, Singapore July 25th , 2013

Agenda

1. Mixed-signal Overview 2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL) 3 Model Generation and Validation 4. Demo: Schematic Model Generator(SMG) 5. Demo: AMS Design & Model Validation (amsDmv) 6. Conclusions

2013 Cadence Design Systems, Inc. Cadence confidential.

Todays needs are vast and complex

Mixed Signal Testbench
How do I verify the digital content in this SoC? How do I verify the mixedsignal interconnects?

Design Analog Design Measure

How do I model analog behavior efficiently?

3

How do I measure the quality of analog verification?

2013 Cadence Design Systems, Inc. Cadence confidential.

MS Verification Challenge
Main Design Challenges Biggest Challenge in MS Verification

Cause of Silicon Re-spins

Preventable by better Verification Methodology

Verification is biggest overall challenge in mixed-signal design Many of silicon re-spins could be prevented by better verification

2013 Cadence Design Systems, Inc. Cadence confidential.

Mixed signal simulation performance

The performance gap between analog simulation and digital is ever-widening Analog simulation does not scale to IC/SoC level
SPICE

FASTSPICE

Performance Gap
Circuit Complexity
AMS-HDL Models FAST SPICE SPICE Digital Simulators/Emulators

Run Time

HDLsim

1x

10x

100x

1Kx

10Kx

1Gx
Event based

1Tx

Matrix based

Relative Simulation Performance

5 2013 Cadence Design Systems, Inc. Cadence confidential.

Key Elements of MS Verification Solution

New, Digital-like Methodology applied on analog and mixed-signal

Integrated Environment

Assertion, Coverage and Metric-Driven Methodology

Simulation
Continuous advancements in performance and features

Behavioral Modeling
Methodology, library and tools abstracting analog and mixed-signal functionality to higher level

2013 Cadence Design Systems, Inc. Cadence confidential.

Bridging the mixed signal divide

Analog Domain
Transistor level Schematic

Mixed Signal Verification

Digital Domain

Schematic Model Generation Behavioral Model (RNM)

R D

D D

D D

D
Validate Models to Circuit (amsDMV)

A D

Testbench

Behavioral models used for functional verification

Real number models offer analog functionality at digital speeds Models are easily used in the Virtuoso and Incisive environments

Pin/Bus communication abstracted to the transaction-level Benefits: Increased Predictability, Productivity and Quality
7 2013 Cadence Design Systems, Inc. Cadence confidential.

Flexible simulation using AMS Designer

Unifying analog and digital engines AMS Designer is a single kernel mixed-signal simulator
Flexible Use Model ( GUI / Command-line ) Choice of Analog solvers (Spectre / Ultrasim / APS ) Configurable Interface Elements

AMS Designer
AMS-Ultra & AMS-Spectre AMS-APS

AMS-Analog Design Environment (Virtuoso GUI integration)

AMS in Analog Design Environment (OSS->UNL+irun)

AMS-irun (AIUM)

(Incisive batch mode regression)

irun + amsd block

IC & IUS
8 2013 Cadence Design Systems, Inc. Cadence confidential.

IUS only

Agenda

1. Mixed-signal Overview 2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL) 3 Model Generation and Validation 4. Demo: Schematic Model Generator(SMG) 5. Demo: AMS Design & Model Validation (amsDmv) 6. Conclusions

2013 Cadence Design Systems, Inc. Cadence confidential.

Real number modeling

Enable high-speed simulation of analog/mixed-signal blocks by using real numbers (floating-point) for signal values in discrete-time, eventdriven simulation Removes the analog solver dependency from mixed signal verification Can be written by analog designers and/or digital verification engineers Enables digital verification techniques for analog/mixed signal blocks
Assertion-based verification Coverage driven verification Metric driven verification Reusable analog verification components (UVM-MS)

Differs from analog behavioral languages (like Verilog-A) since targeted for higher level of integration/testing (IC/SoC) Possible RNM languages include
Verilog-AMS (wreal and Verilog subset) VHDL SystemVerilog

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2013 Cadence Design Systems, Inc. Cadence confidential.

Analog modeling abstraction trade-offs

Speed
108 104 102

Logic

Discrete

Real

Electrical
101

SPICE
Continuous

Accuracy Multiple abstractions required for high confidence in design

11 2013 Cadence Design Systems, Inc. Cadence confidential.

Real number modeling language choices

Several languages to choose from: Verilog-AMS, SystemVerilog, VHDL
Several ways to reach your goals Cadence has robust language support

Start with Verilog-AMS wreals

Works well in Virtuoso Allows porting from Verilog-A performance models to RNM Provides for a compatibility path to SystemVerilog Real (to new IEEE P1800 standard) for SoC verification teams Application note available today

Technical details available if needed

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2013 Cadence Design Systems, Inc. Cadence confidential.

New 2012 SystemVerilog connectivity features

Driven by the IEEE 1800 SV-DC committee

Combining the best features of VHDL and Verilog-AMS real number modeling in SystemVerilog
IEEE 1800-2012 was released in February 2013 Cadence contributed to SV-DC additions

New features enable robust real number modeling New features overcome issues with prior versions of SystemVerilog (2009 and prior LRM)
Real number nets Bi-directional real connections Multiple RNM contributors to the same net Modeling complex information on a single net (eg. Voltage and current)

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2013 Cadence Design Systems, Inc. Cadence confidential.

SystemVerilog used-defined nets

Can carry one or more (real) values over a single net
Can be used to communicate voltage, current or other values between design blocks

User-defined resolutions (UDR) functions used to combine multiple outputs together

V(out)

V(in)

Analog Analog Behavioral Behavioral Model (SV) Real-value Model (SV) nettype

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2013 Cadence Design Systems, Inc. Cadence confidential.

Why do we need UDTs/UDRs?

IEEE 1800-2009 supports real variable port connections
Restricted to input and output only (no inout) Real value connections restricted to variables (multiple net contributors not allowed)

Difference between variables and nets

Variables store value (new assignments overwrite previous values) Nets are used for structural connections and allow for resolution of multiple drivers
Analog Behavioral Model (SV) Analog Behavioral Model (SV)
15 2013 Cadence Design Systems, Inc. Cadence confidential.

Real variable

Analog Behavioral Model (SV)

RNM performance case study

Internal Example: Compare 14bit ADC + 14 bit DAC in transistor and in RNM
We exercise and simulate all possible conversions of the ADC and DAC. Because there are 14 bits, the number of conversions to simulate is 2**14=16384 steps. Transistor performance: several days RNM performance: 3 seconds

TI success story on cadence.com

Analog Real Input A2D

Bit 13

Analog Real Output

D2A

V(in) Bit 0
16 2013 Cadence Design Systems, Inc. Cadence confidential.

V(out)

Agenda

1. Mixed-signal Overview 2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL) 3. Model Generation and Validation 4. Demo: Schematic Model Generator(SMG) 5. Demo: AMS Design & Model Validation (amsDmv) 6. Conclusions

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2013 Cadence Design Systems, Inc. Cadence confidential.

Problem Statement
Customers concerned about behavioral modeling effort for analog/mixed signal designs The current methodology write the behavioral text in a text editor is not acceptable to many analog/mixed signal designers Analog designers prefer a graphical viewpoint of a designs function at the schematic level
Most prefer not to interact with a model at the text language level

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2013 Cadence Design Systems, Inc. Cadence confidential.

Schematic Model Generator (SMG)

User creates a schematic like representation of their behavioural model using the provided building blocks

SMG Processes the schematic to create the behavioural model

Easy to use Building blocks are placed, wired, configured and calibrated using a standard schematic in VSE Integrated into Cadence Virtuoso design flow Improve consistency and model quality Create models from existing qualified building blocks Model-schematic can be reused, shared, reconfigured and easily maintained

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2013 Cadence Design Systems, Inc. Cadence confidential.

Key Benefits of SMG

Easy to use (schematic / GUI based)
Building blocks are placed, wired, configured, and calibrated using a standard schematic (in Virtuoso Schematic Editor) No language to enter or understand Fully integrated into the well know Virtuoso design flow

Reusable model-schematic
Model-schematic can be reused, shared, reconfigured, and easily maintained Easily understandable graphical representation of the design functionality

Model generation creates a standard text model

Provides significantly more flexibility than standard netlisting approaches Connections between blocks can be anything (variables, constants, parameters), not just signals

Improved and consistent model quality

Created from existing mature and qualified model building blocks Reduces the problems resulting from the lack of a designers skill set that adversely affects the quality and performance of the final model Model calibration with measured results by associating ADE XL measured result data with building block parameters
20 2013 Cadence Design Systems, Inc. Cadence confidential.

Model Validation Problems

Analog/MS behavioral models are created and initially validated against the original transistor level design The design/model continues to evolve and change Designers do not have time to continually validate models
Issues such as pin list mismatches or result variations occur

Using the original (out of sync) model could result in incorrect verification results which hide design flaws Thus, continual model validation is mandatory during the design creation and modeling process

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2013 Cadence Design Systems, Inc. Cadence confidential.

What is amsDmv?
AMS Design and Model Validation

Integrated model validation solution that supports:

Validation of analog and digital waveform signals saved from simulations Validation of measured values: Gain, power, delay, noise, etc. Validation of pin/module interfaces of the design and model

Support GUI based setup and exported command line regression run Provides straightforward pass/fail output, reports and extended debugging capabilities (waveform zoom, etc.)

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2013 Cadence Design Systems, Inc. Cadence confidential.

Model Validation Flow (amsDmv)

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Model Validation Flow

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2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview 2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL) 3. Model Generation and Validation 4. Demo: Schematic Model Generator(SMG) 5. Demo: AMS Design & Model Validation (amsDmv) 6. Conclusions

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2013 Cadence Design Systems, Inc. Cadence confidential.

Demo: Schematic Model Generation (SMG)

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2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview 2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL) 3 Model Generation and Validation 4. Demo: Schematic Model Generator(SMG) 5. Demo: AMS Design & Model Validation (amsDmv) 6. Conclusions

27

2013 Cadence Design Systems, Inc. Cadence confidential.

Demo: AMS Design & Model Validation

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2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview 2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL) 3. Model Generation and Validation 4. Demo: Schematic Model Generator (SMG) 5. Demo: AMS Design & Model Validation (amsDmv) 6. Conclusions

29

2013 Cadence Design Systems, Inc. Cadence confidential.

Summary
More functional verification is needed with increasing A/D interactions in designs

Incisive enables plug-and-play mixed signal simulation using AMS Designer

Real number modeling provides high design accuracy while increasing MS simulation speed dramatically Schematic Model Generator (SMG) enables analog engineers to graphically create behavioral models SystemVerilog users can write real number models today nettypes with built-in resolution functions or the Cadence RNM library Auto-inserted connect modules are powerful ways to help with AD ports automatically Automatic wire coercions enables plug-n-play model integration without recoding port connection types

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2013 Cadence Design Systems, Inc. Cadence confidential.

Demos/Workshops/Examples
Real Number Modeling (workshop and examples)
<Incisive 12.2 path>/doc/kit_topics/dms/workshop/lab_manual <Incisive 12.2 path>/tools/amsd/wrealSamples/wrealModels

SMG (examples, model schematics and models)

<IC 6.1.5 path>/tools/dfII/samples/smg/smgAmsExample.tar.Z

AMS Designer using AIUM (26 examples)

< Incisive 12.2 path>/tools/amsd/samples/aium

UVM for Mixed Signal (overview, appnote, labs)

<Incisive 12.2 path>/doc/kit_topics/uvm_ms/

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2013 Cadence Design Systems, Inc. Cadence confidential.

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