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Inverter
Vin
Vout CL
Inverter
CMOS Inverters
VDD PMOS
NMOS GND
Inverter
Ron
R on
VOH = VDD
V out Vout
VOL= 0
R on
Vin = V DD
Vin = 0
Inverter
Vout VDD
ln(0.5)
0.5 0.36
Vin = V DD RonC L
Digital Integrated Circuits Inverter
CMOS Properties
Full rail-to-rail swing l Symmetrical VTC l Propagation delay function of load capacitance and resistance of transistors l No static power dissipation l Direct path current during switching
l
Inverter
Inverter
G S S
PMOS Enhancement
Inverter
n+
n+
n-channel p-substrate B
Depletion Region
Inverter
Inverter
V (V)
-2
-1.5
-1
-0.5
V BS (V)
Digital Integrated Circuits Inverter Prentice Hall 1995
VGS= 2.5 V
Resistive
4 I (A)
Saturation
VGS= 2.0 V
VDS = VGS - VT
VGS= 1.5 V VGS= 1.0 V
Quadratic Relationship
0.5
1 VDS (V)
1.5
2.5
Inverter
Transistor in Linear
S VGS G n+ + L x VDS D n+ ID
V ( x)
p -substrate B
Transistor in Saturation
VGS VDS > VGS - VT D
G S n+
-
VGS - VT
n+
Pinch-off
Inverter
Inverter
Inverter
Early Saturation
2
VGS= 2.5 V
VGS= 2.0 V
1.5 I D (A)
VGS= 1.5 V
Linear Relationship
0.5
VGS= 1.0 V
0.5
1 VDS (V)
1.5
2.5
Inverter
Velocity Saturation
n ( m/s) sat = 105
Constant velocity
c = 1.5
Digital Integrated Circuits Inverter
(V/m)
Prentice Hall 1995
Perspective
ID
Long-channel device VGS = V DD Short-channel device
V DSAT
Digital Integrated Circuits
VGS - V T
Inverter
V DS
Prentice Hall 1995
10
ID versus VGS
6 5 2 4
I D (A)
x 10
-4
x 10 2.5
-4
quadratic
linear
1.5
ID (A)
3 2 1 0 0
0.5
quadratic
0.5 1
VGS(V)
1.5
2.5
0 0
0.5
1
VGS (V)
1.5
2.5
Long Channel
Digital Integrated Circuits Inverter
Short Channel
Prentice Hall 1995
Inverter
11
1.5
I D (A)
1 0.5 0 0
0.5
1.5
2.5
VDS (V)
Digital Integrated Circuits Inverter Prentice Hall 1995
A PMOS Transistor
0 x 10
-4
VGS = -2.0V
-0.6
-0.8
VGS = -2.5V
-1 -2.5
-2
-1.5
VDS (V)
-1
-0.5
Inverter
12
Inverter
D
Rmid R0
V GS = VDD
V DS VDD/2 VDD
Inverter
13
(Ohm) R
eq
0 0.5
1.5
2.5
VDD (V)
Digital Integrated Circuits Inverter Prentice Hall 1995
Inverter
14
Inverter
Threshold Variations
VT Long-channel threshold VT Low V DS threshold
Inverter
15
Sub-Threshold Conduction
10
-2
Linear
10
-4
10
I D (A)
-6
Quadratic
10
-8
10
-10
Exponential VT
0 0.5 1
VGS (V)
10
-12
Inverter
Parasitic Resistances
Polysilicon gate G VGS,eff S RS RD Drain D W LD Drain contact
Inverter
16
Future Perspectives
Inverter
17
Vout IDp Vin=0 Vin=3 VDSp VGSp=-2 VGSp=-5 Vin = V DD-VGSp IDn = - IDp Vout = VDD -VDSp VDSp IDn IDn Vin=0 Vin=3 Vout
Inverter
Vin = 4
Vin = 1
Vin = 4
Vin = 2 Vin = 3
Vin = 3 Vin = 2
Inverter
18
NMOS off PMOS lin NMOS sat PMOS lin NMOS sat PMOS sat NMOS lin PMOS sat
Inverter
Simulated VTC
4.0
1.0
3.0
4.0
5.0
Prentice Hall 1995
19