1 myRISC1 1

Design Specification
Name: myRISC1 Specification: 1. 8-bit program counter 2. 256x8 instruction memory 3. 256x8 data memory 4. 8-bit instruction register 5. 4x8 register file 6. 8-bit ALU 7. 8-bit data bus 8. 8-bit address bus 9. 1-bit status register 10. 16 8-bit instructions 10.1. 10.2. 10.3. 10.4. One miscellaneous type instruction (NOP) Eight register type instructions (ADD,SUB,OR,AND,XOR,MOV,LD,ST) Four immediate type instructions (ADDI,SUBI,RLI,RHI) Three jump type instructions (BZ,BNZ,BRA) range of jump is from -8 to +7

11. Harvard memory architecture

2

RISC Instruction Set Architecture

One of the characteristics of RISC architectures is that it has a single instruction format. By providing a single instruction format, the decoding of an instruction into its component fields can be performed by a minimum level of decoding logic. A RISCs instruction length should be sufficient to accommodate the operation code field (opcode) and one or more operand fields. Consequently, a RISC processor may not utilize memory space as efficiently as a conventional CISC microprocessor. Figure below describes the format of a Berkeley RISC instruction, one of the first RISC processor that came from the University of California at Berkeley.

The op-code field is the Operation code field that indicates the code for each instruction. Each instruction has its own unique Op-code. Scc field whether the condition code bits are updated after the execution of an instruction. Destination and Source 1 fields determine the address of register of which the result would be written into and the first source for an instructions operand, respectively. The IM field determines the source for another instructions operand. If it is 0, the source is the 5-bit address of the registers while if it is 1, the source is the 13-bit immediate number. Because of 5-bits are allocated to each operand field, it follows that this RISC can access up to 25 = 32 internal registers at a time.

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RTL Design Methodology

Design Spcification

Algorithmic Modeling

RTL Modeling
ASM Flowchart

RTL Code

Top Level IOBD

FBD - DU

RTL-CS Table

RTL Design
FBD - CU

FBD Top Level

Verilog HDL Code

Testbench

Pre-synthesis

RTL Verification

Synthesizing

Post-synthesis

Performance Analysis

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Processor Resources 1. Program Counter (PC)

7 0

PC
2. Instruction Memory (IM)
0x00 7 0

IM
0xFF

3. Instruction Register (IR)

7 0

IR
4. Register File (RF)
0 7 0

RF
3

5. Data Memory (DM)

0x00 7 0

DM
0xFF

6. Status Register

SR

4 myRISC1 5

Processor Functional Units 1. Program Counter (PC)

Program counter contain the next instruction address to be executed. This address will be input the program RAM to access a specific line of instructions. Normally, PC would be increased after every instruction executed to point to the next address except if flow control instructions is executed which modify the bits contain in the PC.

2. Program/Instructions Memory Program memory contains the list of instruction to be executed. In Von Neumann architecture machine, program memory and data memory use the common RAM, while in Harvard architecture machine, program memory and data memory use separate RAMs.

3. Instruction Register Instruction register contains the current instruction. It stores the current register temporarily and connects to various other logic devices such as control logic, and register files. When the next instruction is executed, it will overwrite the content of this instruction register.

4. Register File (General Purpose Registers) In RISC machine, register files are the important characteristic. It serves as the general purpose register to store temporary data that is executed by specific instruction. Register files are pretty similar to the RAM except that it doesnt have as much capacity as RAM and thus reduce the cost. Typically, registers are faster than RAM that makes execution of register-register instruction could be faster.

5. Arithmetic and Logic Unit ALU is the unit that does the manipulation to the data such as addition, subtraction, logical AND, logical OR and many more.

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6. Status Register Update the flags when a specific instruction requires the flags to be updated. The flags can is the input to the control unit and will take effect on the sequence of the program execution. The flags can be zero, negative, carry and over flow.

7. Data Memory Data memory is the storage device that store data from the program executed. It could be the constants, variables, address etc. Normally, data that are stores here are not a frequently used data as accessing the memory is slow thus make the program execution slower.

8. Control Unit Control logic is among most important modules that make up a processor. It controls the sequence and datapath flow of an instruction. When an instruction is executed, it fetch and decode the opcode of that instruction and generate the control logic signals to the appropriate modules such as register files, ALU and memory.

9. Address Bus and Data Bus Bus is used to simplify the movement of data from point to point in a computer. Bus is analogous to a highway and the devices are analogous to junctions that connect to this highway. By having both address bus and data bus, it is possible to reduce the number of wires that interconnect within a computer but, it introduces a complexity. In a bused system, only one communication from point to point could happen at a time. Thus a careful synchronization needs to be taken care of and each bus access time has to be long enough for the safe reception in a communication.

6 myRISC1 6

Instruction Set and Format

opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra n n k k k Rb Rb Rb Rb Rb Rb Rb Rb m m operand1 operand2 Assembly Language Mnemonics NOP ADD Ra,Rb SUB OR Ra,Rb Ra,Rb No Operation Ra Ra + Rb ; update Z Ra Ra - Rb ; update Z Ra Ra | Rb ; update Z Ra Ra & Rb ; update Z Ra Ra ^ Rb ; update Z Ra Rb ; update Z Ra M[Rb] M[Rb] Ra Ra Ra + 000000m1m0 ; update Z Ra Ra - 000000m1m0 ; update Z R0 R0 | 0000n3n2n1n0 ; update Z R0 n3n2n1n00000 ; update Z (Z) / PC PC + k (k is 4 bit signed number) (!Z) / PC PC + k (k is 4 bit signed number) PC PC + k (k is 4 bit signed number) RTL Operation

AND Ra,Rb XOR Ra,Rb MOV Ra,Rb LD ST Ra,Rb Ra,Rb

ADDI Ra,m SUBI Ra,m RLI RHI BZ BNZ BRA n n k k k

7 myRISC1 7

ASM Flowchart
rst S0 PC 0 0
start

1 S1 read , IR IM[PC]

S2 IR IM[PC] PC PC + 1 S3 NOP
No action opcode

S14 SUBI
RF[IR3:2] RF[IR3:2] - RF[IR1:0]

S4 ADD
RF[IR3:2] RF[IR3:2] + RF[IR1:0]

S15 RLI
RF[00] RF[00] | {4'b0,RF[IR3:0]}

S5 SUB
RF[IR3:2] RF[IR3:2] - RF[IR1:0]

S16 RHI
RF[00] {RF[IR3:0],4'b0}

S6 OR
RF[IR3:2] RF[IR3:2] | RF[IR1:0]

S17 BZ

S7 AND
RF[IR3:2] RF[IR3:2] & RF[IR1:0]

0
Z

1 S8 XOR
RF[IR3:2] RF[IR3:2] ^ RF[IR1:0] PC PC + {4'b0,IR[3:0]}

S18

S9 MOV
RF[IR3:2] RF[IR1:0]

S19 BNZ

S10 LD0
read , RF[IR3:2] DM[RF[IR1:0]]

0
!Z

1 S11 LD1 S20

PC PC - {4'b0,IR[3:0]}

read , RF[IR3:2] DM[RF[IR1:0]]

S12 ST
DM[RF[IR1:0]] RF[IR3:2]

S21 BRA
PC PC + {4'b0,IR[3:0]}

S13 ADDI
RF[IR3:2] RF[IR3:2] + RF[IR1:0]

8 myRISC1 8

FBD-DU

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RTL-CS Table : Control Signal Activated

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RTL-CS Table : Control Vector

11 myRISC1
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FBD-CU
CU NS opcode z start
Next State Logic

PS d q 5
State Register Output Logic
15

CV [14:0]

rst PS[4:0] clk

12

rst

IOBD and Interconnection -Top Level

12 myRISC1
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FBD-Top Level

13 myRISC1
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Verilog Code 1. myRISC1 Top Level

module myRISC1(clk,rst,start,PS,opcode,PC,IM_instr,IR_instr,CV,R0,R1,R2,R3,Z,A_ALU,B_ALU); input output output output output output output output output wire wire wire wire wire wire wire wire wire wire wire wire wire [3:0] [4:0] [7:0] [7:0] [7:0] [7:0] [14:0] [3:0] [14:0] [7:0] [7:0] [7:0] [7:0] [7:0] [8:0] [7:0] [7:0] [4:0] [7:0] clk,rst,start; opcode; PS; R0,R1,R2,R3,A_ALU,B_ALU; PC; IM_instr; IR_instr; CV; Z; opcode; CV; Z; PC; IM_instr; IR_instr; A; B; out_alu; data; RF_wdata; NS; k;

DU myRISC1_DU(clk,rst,CV[14],CV[13],CV[12],CV[11],CV[10:8],CV[7],CV[6],CV[5],CV[4:3],CV[2:1],CV[0],opcode, out_alu,data,R0,R1,R2,R3,A,B,Z,k,PC,IR_instr,IM_instr,RF_wdata,A_ALU,B_ALU); CU myRISC1_CU(clk,rst,start,opcode,Z,NS,PS,CV);

endmodule

2. Datapath Unit
Module DU(clk,rst,clrPC,selPC,ldPC,ldIR,op_alu,ldSR,wDM,sel_MUX21_1,sel_MUX41_1,sel_MUX41_2,wRF,opcode, out_alu,data,A_reg,B_reg,C_reg,D_reg,A,B,Z,k,PC,IR_instr,IM_instr,RF_wdata,A_ALU,B_ALU); input input input input output output output output output output output output output wire wire wire wire wire wire clk,rst; ldPC,clrPC,selPC,ldIR,wRF,wDM,sel_MUX21_1,ldSR; [1:0] sel_MUX41_1,sel_MUX41_2; [2:0] op_alu; [8:0] [7:0] [7:0] [7:0] [7:0] [3:0] [7:0] [7:0] Z; [7:0] [7:0] [3:0] [1:0] [1:0] [7:0] out_alu; data; IR_instr,IM_instr,RF_wdata; A_reg,B_reg,C_reg,D_reg,A_ALU,B_ALU; A,B; opcode; PC; k; i_addr_in; i_instr; i_opcode; i_A_raddr; i_B_raddr; i_A_reg,i_B_reg,i_C_reg,i_D_reg;

14 myRISC1
wire wire wire wire wire wire wire wire wire wire wire wire wire wire [7:0] i_A_data,i_B_data; [1:0] i_data_MUX21_1_0,i_data_MUX21_1_1,i_data_MUX21_1; [7:0] i_data_MUX41_1_0,i_data_MUX41_1_1,i_data_MUX41_1_2,i_data_MUX41_1; [1:0] i_A_waddr; [7:0] i_w_data; [7:0] i_A; [7:0] i_B; [8:0] i_out_alu; [7:0] i_data; i_C,i_Z; [7:0] i_rwaddrM,i_PC; [7:0] i_wdataM; [7:0] i_rdataM; [7:0] i_data_MUX41_2_0,i_data_MUX41_2_1,i_data_MUX41_2_2,i_data_MUX41_2;

IFU DU_IFU(clk,rst,ldPC,clrPC,selPC,ldIR,i_instr,i_opcode,k,i_PC,IM_instr); MUX21_1 DU_MUX21_1(sel_MUX21_1,i_data_MUX21_1_0,i_data_MUX21_1_1,i_data_MUX21_1); RF DU_RF(clk,rst,wRF,i_A_raddr,i_B_raddr,i_A_reg,i_B_reg,i_C_reg,i_D_reg,i_A_data,i_B_data,i_A_waddr, i_w_data); ALU DU_ALU(clk,rst,ldSR,op_alu,i_A,i_data_MUX41_1,i_out_alu,i_data,i_C,i_Z); MUX41_1 DU_MUX41_1(sel_MUX41_1,i_data_MUX41_1_0,i_data_MUX41_1_1,i_data_MUX41_1_2,i_data_MUX41_1); DM DU_DM(clk,wDM,i_rwaddrM,i_wdataM,i_rdataM); MUX41_2 DU_MUX41_2(sel_MUX41_2,i_data_MUX41_2_0,i_data_MUX41_2_1,i_data_MUX41_2_2,i_data_MUX41_2); assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign opcode = i_opcode; out_alu = i_out_alu; i_data_MUX21_1_0 = 2'b00; i_data_MUX21_1_1 = i_instr[3:2]; data = i_data; IR_instr = i_instr; A_reg = i_A_reg; B_reg = i_B_reg; C_reg = i_C_reg; D_reg = i_D_reg; i_A_raddr = i_data_MUX21_1; i_B_raddr = i_instr[1:0]; i_A_waddr = i_data_MUX21_1; i_w_data = i_data_MUX41_2; i_A = i_A_data; i_B = i_B_data; A = i_A; B = i_B; i_wdataM = i_A_data; i_rwaddrM = i_data_MUX41_1; i_data_MUX41_1_0 = i_B; i_data_MUX41_1_1 = {6'b000000,i_instr[1:0]}; i_data_MUX41_1_2 = {4'b0000,i_instr[3:0]}; i_data_MUX41_2_0 = i_data_MUX41_1; i_data_MUX41_2_1 = i_data; i_data_MUX41_2_2 = i_rdataM; Z = i_Z; PC = i_PC; RF_wdata = i_data_MUX41_2; A_ALU = i_A; B_ALU = i_data_MUX41_1;

endmodule

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3. Instruction Fetch Unit (IFU)

module IFU(clk,rst,ldPC,clrPC,selPC,ldIR,IR_instr,opcode,k,PC,IM_instr); input input output output output output reg wire wire wire wire clk,rst; ldPC,clrPC,selPC,ldIR; [3:0] k; [7:0] PC; [7:0] IR_instr,IM_instr; [3:0] opcode; [7:0] [7:0] [7:0] [3:0] k; i_PC; i_w_instr,i_r_instr; i_opcode; iwe;

PC IFU_PC(clk,rst,ldPC,clrPC,selPC,PC,k); IM IFU_IM(clk,iwe,PC,i_w_instr,i_r_instr); IR IFU_IR(clk,rst,ldIR,i_opcode,i_r_instr,IR_instr); assign opcode = i_opcode; assign IM_instr = i_r_instr; always@(IR_instr) if(IR_instr[3]) k = {4'b1111,IR_instr[3:0]}; else k = {4'b0000,IR_instr[3:0]}; endmodule

4. Program Counter (PC)

module PC(clk,rst,ldPC,clrPC,selPC,PC,k); input input input output reg clk,rst,clrPC; selPC,ldPC; [7:0] k; [7:0] PC; [7:0] PC;

//PC_value always@(posedge clk or posedge rst) if(rst) PC<=8'b00000000; else if(clrPC) PC<=8'b00000000; else if(ldPC) if(selPC) PC<=PC+8'b00000001; else PC<=PC+k; else PC<=PC; endmodule

16 myRISC1

5. Instruction Memory(IM)
//RAM 256 x 8 //using lpm_ram_dq //256 address location,8-bit data module IM(clk,we,PC,w_instr,r_instr); input input input input output wire high; assign high = 1; parameter i=8; parameter a=8; //instruction width = 8-bit //address width = 12-bit clk; we; w_instr; PC; r_instr;

[i-1:0] [a-1:0] [i-1:0]

lpm_ram_dq myRAM(.q(r_instr), .data(w_instr), .address(PC), .we(we), .inclock(clk), .outclock(high)); defparam defparam defparam defparam defparam endmodule myRAM.lpm_width = 8; myRAM.lpm_widthad = 8; myRAM.lpm_indata = "REGISTERED"; myRAM.lpm_outdata = "UNREGISTERED"; myRAM.lpm_file = "IM.mif";

6. Instruction Register
module IR(clk,rst,ldIR,opcode,w_instr,r_instr); input input input output output reg clk,rst; ldIR; w_instr; r_instr; opcode; r_instr;

[7:0] [7:0] [3:0] [7:0]

always@(posedge rst or posedge clk) if(rst) r_instr<=8'b00000000; else if(ldIR) r_instr<=w_instr; else r_instr<=r_instr; assign opcode = r_instr[7:4]; endmodule

17 myRISC1

7. Register File (RF)

module RF(clk,rst,we,A_raddr,B_raddr,A_reg,B_reg,C_reg,D_reg,A_data,B_data,A_waddr,w_data); input input input input input input output output output reg reg reg clk,rst; we; A_raddr; B_raddr; A_waddr; w_data; A_reg,B_reg,C_reg,D_reg; A_data; B_data; A_reg,B_reg,C_reg,D_reg; A_data; B_data;

[1:0] [1:0] [1:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

//writing to RF always@(posedge clk or posedge rst) if(rst)begin A_reg <= 8'b00000000; B_reg <= 8'b00000000; C_reg <= 8'b00000000; D_reg <= 8'b00000000;end else if(we) case(A_waddr) 0: A_reg <= w_data; 1: B_reg <= w_data; 2: C_reg <= w_data; 3: D_reg <= w_data; endcase else begin A_reg <= A_reg; B_reg <= B_reg; C_reg <= C_reg; D_reg <= D_reg;end //reading A_data always@(A_raddr or A_reg or B_reg or C_reg or D_reg) case(A_raddr) 0: A_data = A_reg; 1: A_data = B_reg; 2: A_data = C_reg; 3: A_data = D_reg; endcase //reading B_data always@(B_raddr or A_reg or B_reg or C_reg or D_reg) case(B_raddr) 0: B_data = A_reg; 1: B_data = B_reg; 2: B_data = C_reg; 3: B_data = D_reg; endcase endmodule

18 myRISC1

8. Arithmetic Logic Unit (ALU)

module ALU(clk,rst,ldSR,op_alu,A,B,out_alu,data,C,Z); input input input input output output output reg reg clk,rst; ldSR; op_alu; A,B; out_alu; data; C,Z; out_alu; Z;

[2:0] [7:0] [8:0] [7:0] [8:0]

always@(op_alu or A or B) case(op_alu) 0: out_alu = A + B; 1: out_alu = A - B; 2: out_alu = A | B; 3: out_alu = A & B; 4: out_alu = A ^ B; 5: out_alu = A; 6: out_alu = B; 7: out_alu = {B[3:0],4'b0000}; default: out_alu = 9'bxxxxxxxx; endcase //Status_Reg always@(posedge clk or posedge rst) if(rst) Z<=1'b0; else if(ldSR) Z<=(data==0); else Z<=Z; assign data = out_alu[7:0]; assign C = out_alu[8]; endmodule

9. Data Memory (DM)

module DM(clk,we,rwaddrM,wdataM,rdataM); input input input input output clk; we; [d-1:0] wdataM; [a-1:0] rwaddrM; [d-1:0] rdataM;

wire high; assign high = 1; parameter d = 8; parameter a = 8;

//data width = 8-bit //address width = 8-bit

lpm_ram_dq myRAM(.q(rdataM), .data(wdataM), .address(rwaddrM), .we(we), .inclock(clk), .outclock(high)); defparam defparam defparam defparam defparam endmodule myRAM.lpm_width = 8; myRAM.lpm_widthad = 8; myRAM.lpm_indata = "REGISTERED"; myRAM.lpm_outdata = "UNREGISTERED"; myRAM.lpm_file = "DM.mif";

19 myRISC1

10. MUX21_1
module MUX21_1(sel_MUX21_1,data_MUX21_1_0,data_MUX21_1_1,data_MUX21_1); input input output reg [1:0] [1:0] [1:0] sel_MUX21_1; data_MUX21_1_0,data_MUX21_1_1; data_MUX21_1; data_MUX21_1;

always@(sel_MUX21_1 or data_MUX21_1_0 or data_MUX21_1_1) if(sel_MUX21_1) data_MUX21_1 = data_MUX21_1_1; else data_MUX21_1 = 2'b00; endmodule

11. MUX41_1
module MUX41_1(sel_MUX41_1,data_MUX41_1_0,data_MUX41_1_1,data_MUX41_1_2,data_MUX41_1); input input output reg [1:0] [7:0] [7:0] [7:0] sel_MUX41_1; data_MUX41_1_0,data_MUX41_1_1,data_MUX41_1_2; data_MUX41_1; data_MUX41_1;

always@(sel_MUX41_1 or data_MUX41_1_0 or data_MUX41_1_1 or data_MUX41_1_2) case(sel_MUX41_1) 0: data_MUX41_1 = data_MUX41_1_0; 1: data_MUX41_1 = data_MUX41_1_1; 2: data_MUX41_1 = data_MUX41_1_2; default data_MUX41_1 = 8'bxxxxxxxx; endcase endmodule

12. MUX41_2
module MUX41_2(sel_MUX41_2,data_MUX41_2_0,data_MUX41_2_1,data_MUX41_2_2,data_MUX41_2); input input output reg [1:0] [7:0] [7:0] sel_MUX41_2; data_MUX41_2_0,data_MUX41_2_1,data_MUX41_2_2; data_MUX41_2; [7:0] data_MUX41_2;

always@(sel_MUX41_2 or data_MUX41_2_0 or data_MUX41_2_1 or data_MUX41_2_2) case(sel_MUX41_2) 0: data_MUX41_2 = data_MUX41_2_0; 1: data_MUX41_2 = data_MUX41_2_1; 2: data_MUX41_2 = data_MUX41_2_2; default data_MUX41_2 = 8'bxxxxxxxx; endcase endmodule

20 myRISC1

13. Control Unit (CU)

module CU(clk,rst,start,opcode,Z,NS,PS,CV); input input input output output reg reg clk,rst,start; Z;

[3:0] [4:0] [15:0]

opcode; PS,NS; CV; [14:0] [4:0]

CV; PS,NS;

parameter [4:0] S0=5'b00000,S1=5'b00001,S2=5'b00010,S3=5'b00011,S4=5'b00100,S5=5'b00101,S6=5'b00110,S7=5'b00111,S8 =5'b01000,S9=5'b01001,S10=5'b01010,S11=5'b01011,S12=5'b01100,S13=5'b01101,S14=5'b01110,S15=5'b01111,S16=5'b 10000,S17=5'b10001,S18=5'b10010,S19=5'b10011,S20=5'b10100,S21=5'b10101; parameter [3:0] NOP=4'b0000,ADD=4'b0001,SUB=4'b0010,OR=4'b0011,AND=4'b0100,XOR=4'b0101,MOV=4'b0110,LD0=4'b0111, LD1=4'b0111,ST=4'b1000,ADDI=4'b1001,SUBI=4'b1010,RLI=4'b1011,RHI=4'b1100,BZ=4'b1101,BNZ=4'b1110,BRA=4'b111 1; //define STATE_REG: always@(negedge clk or posedge rst) if(rst) PS <= S0; else PS <= NS; //define NS LOGIC: always@(start or opcode or Z or PS) begin case(PS) S0: S1: S2: begin

if(start) NS = S1; else NS = S0; NS = S2; case(opcode) NOP : ADD : SUB : OR : AND : XOR : MOV : LD0 : ST : ADDI: SUBI: RLI : RHI : BZ : BNZ : BRA : endcase NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS = = = = = = = = = = = = = = = = S3; S4; S5; S6; S7; S8; S9; S10; S12; S13; S14; S15; S16; S17; S19; S21;

S3: S4: S5: S6: S7: S8: S9: S10: S11: S12: S13:

NS = S1; NS = S1; NS = S1; NS NS NS NS NS NS = = = = = =

end NS = S1;

NS = S1; S1; S1; S11; S1; S1; S1;

21 myRISC1
S14: S15: S16: S17: NS = S1; NS = S1; NS = S1; if(Z) else S18: S19: NS = S1; if(!Z) else S20: NS = S1; S21: NS = S1; default: NS = S1;

NS = S18; NS = S1; NS = S20; NS = S1;

endcase end

//define OUTPUT LOGIC: always@(PS or start) begin case(PS) S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 default endcase end endmodule

: begin CV = 15'h4000; end : begin CV = 15'h0800; end : begin CV = 15'h3800; end : begin CV = 15'h0000; end : begin CV = 15'h00A3; end : begin CV = 15'h01A3; end : begin CV = 15'h02A3; end : begin CV = 15'h03A3; end : begin CV = 15'h04A3; end : begin CV = 15'h00A1; end : begin CV = 15'h0025; end : begin CV = 15'h0025; end : begin CV = 15'h0060; end : begin CV = 15'h00AB; end : begin CV = 15'h01AB; end : begin CV = 15'h0293; end : begin CV = 15'h0793; end : begin CV = 15'h0000; end : begin CV = 15'h1000; end : begin CV = 15'h0000; end : begin CV = 15'h1000; end : begin CV = 15'h1000; end :begin CV = 15'h0000; end

22 myRISC1
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Test Pattern 1. Input Program

Instruction Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D opcode RHI RLI MOV RHI MOV MOV ADDI ST ADDI SUBI NOP BNZ NOP RHI RLI MOV RHI MOV LD ADD ADDI SUBI NOP BNZ NOP MOV RHI RLI ST NOP R3 #0 #4 R3 R0 R0 #-6 #0 #4 R1 #0 R2 R3 R0 R0 R1 R0 R2 R3 #1 #1 R0 #-6 operand1 #0 #4 R1 #0 R2 R3 R3 R3 R2 R1 R0 R0 #2 R2 #1 #1 R0 operand2 opcode 1100 1011 0110 1100 0110 0110 1001 1000 1001 1010 0000 1110 0000 1100 1011 0110 1100 0110 0111 0001 1001 1010 0000 1110 0000 0110 1100 1011 1000 0000 Machine Code operand1 00 01 01 00 10 11 11 11 10 01 00 10 00 00 01 01 00 10 11 00 00 01 00 10 00 11 00 01 11 00 operand2 00 00 00 00 00 00 10 10 01 01 00 10 00 00 00 00 00 00 10 11 01 01 00 10 00 00 00 00 00 0 0 Instruction in decimal 192 180 100 192 104 108 158 142 153 165 0 234 0 192 180 100 192 104 126 19 145 165 0 234 0 108 192 180 140 0

2. Instruction Memory

23 myRISC1
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Simulation Result

24 myRISC1
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Result Analysis
1. Programming Analysis
Addr 00 01 02 03 04 05 06 Instruction RHI 0 RLI 4 MOV R1,R0 RHI 0 MOV R2,R0 MOV R3,R0 ADDI R3,2 R0 00000000 00000100 00000100 00000000 00000000 00000000 0+2=2 2+2=4 4+2=6 6+2=8 M[0]=2 M[1]=4 M[2]=6 M[3]=8 0+1=1 1+1=2 2+1=3 3+1=4 4-1=3 3-1=2 2-1=1 1-1=0 =zero R1 counter R2 memory address R3 result data Data Memory

07

ST R3,R2

08

ADDI R2,1

09

SUBI R1,1

0A 0B 0C 0D 0E 0F 10 11 12

NOP BNZ -6 NOP RHI 0 RLI 4 MOV R1,R0 RHI 0 MOV R2,R0 LD R3,R2

00000000 00000100 00000100 00000000 00000000 2 2 2 2 2+0=2 3+2=5 6+2=8 9+2=11 2+1=3 5+1=6 8+1=9 11+1=12 4-1=3 3-1=2 2-1=1 1-1=0 zero

13

ADD R0,R3

14

ADDI R0,1

15

SUBI R1,1

16 17 18 19 1A 1B 1C 1D

NOP BNZ -6 NOP MOV R3,R0 RHI 0 RLI 4 ST R3,R0 NOP

12 00000000 00000100 M[4]=12

25 myRISC1

2. Data Memory (Final data stored in DM)

18

Timing Analysis
The maximum frequency could be performed by this processor is 57.05 MHz and in the running program, the frequency is used is 50 Mhz. The critical path comes from Present State Register in CU to Status Register in DU as shown below.

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Resource Utilization
The total logic element used is 185 and the total number register used is 54. The number of memory bit used is 4096. The summary of the compilation is shown below. Here is how the total number of register used and memory bit used are defined: Number of Register Used : RF + PC + IR + SR + NS = ( 4 x 8 ) + 8 + 8 + 1 + 5 = 54 Number memory bit used: (256x8 for IM) + (256 x 8 for DM) = 2 x (256 x 8) = 4096

26 myRISC1

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Conclusion
A RISC processor has been designed, synthesized, validated and working correctly as expected by running the test pattern. The final result is validated by observing the final data stored data in data memory as well as in the register files. For further study, the performance of this RISC processor can be improved by implementing the 5-state pipeline mechanism as shown on figure below which is based on MIPS architecture.

Furthermore, since the jump type instruction is only can jump in range from -8 to +7, the datapath unit design have to redesign on order that the jump type instruction can jump from -128 to +127 by storing the k immediate value into register file first and then supply to program counter with adding one stack pointer if the return instruction is needed as shown in the datapath below.

27 myRISC1

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References
1. Dr Mohamed Khalil Hani, Starters Guide to Digital Systems VHDL & Verilog Design , Revised Edition 2, July 2010, Desktop Publisher.

2. Stephen Brown & Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design,
Second Edition, 2003, McGraw Hill.