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All Graduate Theses and Dissertations Graduate Studies, School of
5-1-2008
Design and Implementation of Digital Signal Processing Hardware for a Software Radio Reciever
Jake Talbot
Utah State University
Recommended Citation
Talbot, Jake, "Design and Implementation of Digital Signal Processing Hardware for a Software Radio Reciever" (2008). All Graduate Theses and Dissertations. Paper 265. http://digitalcommons.usu.edu/etd/265
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DESIGN AND IMPLEMENTATION OF DIGITAL SIGNAL PROCESSING HARDWARE FOR A SOFTWARE RADIO RECIEVER by
Jake Talbot A report submitted in partial fulllment of the requirements for the degree of MASTER OF SCIENCE in Computer Engineering
Approved:
ii
Copyright
iii
Abstract
Design and Implementation of Digital Signal Processing Hardware for a Software Radio Reciever by Jake Talbot, Master of Science Utah State University, 2008
Major Professor: Dr. Jacob H. Gunther Department: Electrical and Computer Engineering This project summarizes the design and implementation of eld programmable gate array (FPGA) based digital signal processing (DSP) hardware meant to be used in a software radio system. The lters and processing were rst designed in MATLAB and then implemented using very high speed integrated circuit hardware description language (VHDL). Since this hardware is meant for a software radio system, making the hardware exible was the main design goal. Flexibility in the FPGA design was reached using VHDL generics and generate for loops. The hardware was veried using MATLAB generated signals as stimulus to the VHDL design and comparing the VHDL output with the corresponding MATLAB calculated signal. Using this verication method, the VHDL design was veried post place and route (PAR) on several dierent Virtex family FPGAs. (123 pages)
iv
Acknowledgments
I am indebted to many people for the completion of this project. First and foremost, I would like to thank my major professor, Dr. Gunther. He has shown a tremendous amount of patience throughout the design process. He has always been eager to entertain questions and elicit advice whenever I would arrive at his oce, often times unannounced. I would also like to thank my committee members, Dr. Moon and Dr. Dasu, for their patience and willingness to help me throughout the course of this project. Next, I would like to thank my wife for her loving support throughout my college career, especially for helping me edit the rst draft of this thesis. She often supplied motivation when I felt like I had none. Thanks also to my oce mates: Roger West, John Flake, Cameron Grant, and Darin Nelson who have helped me greatly these last few semesters. Finally, I would like to extend thanks to my parents, Steve and Jill. They have provided unending support and encouragement to me throughout my whole life.
Jake Talbot
vi
Contents
Page Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Background . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . 1.2 Software Radios . . . . . . . . . 1.3 Project Scope . . . . . . . . . . 1.4 CIC Filter Theory . . . . . . . 1.5 Polyphase FIR Filter Theory . 1.6 Conclusion . . . . . . . . . . . 2 MATLAB Design . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . 2.2 Specications . . . . . . . . . 2.3 CIC Filter Design . . . . . . . 2.4 Polyphase FIR Filter Design . 2.5 Conclusion . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . ..... . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . .. . . . . . . ix 1 1 1 2 3 7 9 10 10 10 13 15 19
..... . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . . . . . .
.... . . . . . . . . . . . . . . .
.... . . . . . . . . . . . . . . . . . . . . . . .
... . . . . . . . . . .
3 VHDL Design . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . 3.2 Generics . . . . . . . . . . . . . 3.3 Design Hierarchy . . . . . . . . 3.3.1 Demodulator . . . . . . 3.3.2 CIC Hierarchy . . . . . 3.3.3 FIR Filter Hierarchy . . 3.4 Conclusion . . . . . . . . . . . 4 Verication . . . . . . . . . . . . 4.1 Introduction . . . . . . . 4.2 Verication Method . . 4.3 FPGA Utilization . . . . 4.4 Conclusion . . . . . . . .... . . . . . . . . . . . .
..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . .
.... . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 20 . . 20 . . 20 . . 22 . . 22 . . 23 . . 25 . . 28 ... . . . . . . . . 29 29 29 30 33
.... . . . . . . . . . . . .
..... . . . . . . . . . . . . . . . .
.... . . . . . . . . . . . .
vii 5 Summary and Future 5.1 Introduction . . . . 5.2 Work Completed . 5.3 Future Work . . . 5.4 Conclusion . . . . Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . .... . . . . . . . . . . . . ..... . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . 35 . 35 . 35 . 37 . 38
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A Synthesis Options and Timing Constraints . . A.1 Introduction . . . . . . . . . . . . . . . . . . . . A.2 Synthesis Options . . . . . . . . . . . . . . . . . A.3 Timing Constraints . . . . . . . . . . . . . . . . . A.4 Conclusion . . . . . . . . . . . . . . . . . . . . . Appendix B MATLAB Listings . . . . . . . . . . . . . . . B.1 Main Script . . . . . . . . . . . . . . . . . . . . . B.2 Functions Used . . . . . . . . . . . . . . . . . . . Appendix C VHDL Listings . . . . . . . . . . . . . . . . . C.1 Top Level of the Hierarchy . . . . . . . . . . . . C.2 Second Level of the Hierarchy . . . . . . . . . . . C.3 Third Level of the Hierarchy . . . . . . . . . . . C.4 Fourth Level of the Hierarchy . . . . . . . . . . . C.5 Fifth Level of the Hierarchy . . . . . . . . . . . . C.6 Leaf Nodes . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 . 41 . 41 . 41 . 43 . 50 . 51 . 51 . 55 . 59 . 59 . 63 . 73 . 87 . 92 . 94
viii
List of Tables
Table 2.1 3.1 4.1 Input signal specications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of generics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic values used to generate g. 4.2. . . . . . . . . . . . . . . . . . . . . Page 11 21 30 42
ix
List of Figures
Figure 1.1 1.2 1.3 1.4 Basic building blocks of a CIC lter. . . . . . . . . . . . . . . . . . . . . . . Frequency response of three CIC lters, each with a dierent number of stages. Block diagram of a CIC decimator. . . . . . . . . . . . . . . . . . . . . . . . Block diagram of a decimating CIC lter in which the downsampler has been pushed before the comb cascade using a Noble identity. Notice that the comb lters now delay the input signal by M samples instead of RM samples as in g. 1.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram showing the processing from (1.2) using polyphase lters and delay elements. The ltered signal is then downsampled. . . . . . . . . . . . Block diagram showing a decimating polyphase lter after a noble identity has been applied to the block diagram in g. 1.5, pushing the downsamplers in front of the polyphase lters. This is the processing that will be performed after the CIC lter in the design of this project. . . . . . . . . . . . . . . . . A gure showing the role of each of the specications outlined in Table 2.1. Page 4 5 6
1.5
1.6
9 11
2.1 2.2
Spectrum of the test signal that contains the four frequency components at F0 + W , F0 W , F0 + F , and F0 F . The rst two are desired, whereas the second two frequency components are undesired and should be ltered out. 14 Spectrum of the test signal after demodulation by cosine. . . . . . . . . . . Top-level block diagram of the system. . . . . . . . . . . . . . . . . . . . . . Frequency response of the CIC lter with ve stages. At W , the frequency of interest, the attenuation is about -0.56 dB. At W + F , the rst unwanted frequency component, the attenuation is about -1.28 dB. . . . . . . . . . . . Test spectrum after CIC lter has decimated it by 125. . . . . . . . . . . . . Frequency response of the designed low-pass prototype lter. Notice that the stop-band attenuation is actually 80 dB. This is because the lter was designed above specs to account for quantization error when xed point coecients are used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15
16 16
2.6 2.7
17
x 2.8 Frequency response of the quantized low-pass prototype lter. The frequency response of the full precision lter is also shown for comparison. . . . . . . . Spectrum of the fully decimated signal. This signal is sampled at the desired sample rate, FS,f inal = 100kHz , which is twice the symbol rate of the communications system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of the top level in the design hierarchy. The decimation factor generics for each lter are specied. The q1 and q2 blocks shown are quantizers. They perform quantization using truncation, keeping the upper bits of the input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The top-level of the CIC lter hierarchy. . . . . . . . . . . . . . . . . . . . . Integrators module structure. This structure was generated using a generate for loop based on the N stages cic generic of the top-level module. Registers are shown as a block with a triangle on the bottom. . . . . . . . . . . . . . Block diagram of the downsampler module in the CIC lter hierarchy. The start ctrl module enables the ce ctrl module to grab the rst good sample. . A block diagram of the comb lter cascade. The M parameter is called the dierential delay. There is no generic specifying this parameter; it is xed at two for this design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram showing the top level of the hierarchy for the polyphase FIR lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram showing the structure of the FIR taps module in the polyphase FIR lter design hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . Plot showing quantized outputs from the MATLAB simulation alongside the corresponding outputs from the post PAR top level VHDL simulation. . . . Waveform showing the rst 350s of the top level post PAR simulation. The simulation was performed in ModelSim using input stimulus from the test signal generated in MATLAB. This test signal is described in Chapter 2. . . An excerpt of a Xilinx ISE 9.1i PAR report outlining the target FPGA utilization for the VHDL design. The target FPGA here is a Xilinx Virtex5 95sxt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
2.9
18
3.1
22 23
3.2 3.3
24
3.4
24
3.5
25
3.6
26
3.7
27
4.1
31
4.2
32
4.3
33
Chapter 1 Background
1.1
Introduction In recent years, there has been a great demand for wireless communications technology.
As a result of this increasing demand, several new wireless communication standards have been created and put into use. With the advent of all of these dierent wireless standards, it is desirable to have a radio receiver that is capable of communicating with several dierent standards. This requires a radio to be able to recongure its features (demodulation, error correction, etc.) according to the type of communications standard it is trying to interact with. Another advantage of a radio that can be recongured is the fact that the radio does not become obsolete with the creation of a new wireless standard. A radio that can be recongured is called a software radio.
1.2
Software Radios In order for a radio to be able to recongure itself based on the signals it is receiving,
it has to be largely dened with software. In other words, these types of radios are able to recongure the hardware using software. This terminology is somewhat vague. How much exibility does a radio need to have in order to be called a software radio? The following quote helps to dene what it means to be a software radio. A good working denition of a software radio is a radio that is substantially dened in software and whose physical layer behavior can be signicantly altered through changes to its software [1, pg. 2]. As an example, a radio that utilizes a digital signal processor or microprocessor is not necessarily a software radio. On the other hand, if a radio denes its modulation, error
2 correction and encryption in its software and also exhibits some exibility over the radio frequency (RF) hardware, it is clearly a software radio. Generally, a software radio refers to a radio that is exible with respect to the software, but the software operates on a static hardware platform. In order to maximize exibility, a software radio receiver digitizes the received signal as soon as possible to utilize the exibility of digital signal processing (DSP). This is usually done after an analog front end lters, amplies, and mixes the signal to an intermediate frequency (IF). The signal is then digitized and translated to baseband using a digital down converter (DDC).
1.3
Project Scope In this project, hardware will be designed and implemented that will perform an IF to
baseband conversion of a received signal. This hardware is intended for use in a software radio. The functions that this hardware will perform are outlined below: Demodulation: The incoming signal will be translated from an intermediate frequency to baseband. Decimation: The baseband signal will be ltered and downsampled to a more manageable sampling rate. Even with RF hardware partially demodulating the carrier signal to an intermediate frequency, the sample rate of the system is still fairly high (about 100 - 500 M Hz ). This being the case, a DSP chip will not be able to process the data coming from the analog to digital converter (ADC) fast enough for a real time setting. This leaves either a eld programmable gate array (FPGA) or an application specic integrated circuit (ASIC) as the target hardware for this project. Being in a University setting, an FPGA is the more economical choice. Using an FPGA is desirable also because they can be reprogrammed on the y, coinciding with the recongurability required of a software radio. Having determined that an FPGA will be used to perform the processing, very high speed integrated circuit hardware description language (VHDL) will be used to implement
3 the hardware. VHDL was chosen since the use of generic modules and generate for loops (a VHDL construct, discussed in detail in Chapter 3) will make the FPGA design exible and recongurable. With generic modules, the processing the FPGA performs can be greatly altered or modied by simply changing the generic values of the top level design. Generate for loops that are based on the generic values will then be used to create the structures of the decimating lters. For this design, the intermediate frequency is assumed to be
1 4
This imposes some restrictions on the analog front end of the receiver. These restrictions on the RF hardware make the demodulation circuitry multiplier free (see Chapter 2 for more details). Another implication of these simplifying assumptions is that the received signal is going to be oversampled by a large factor, leading to a high decimation factor required of the DDC hardware. For example, if FS = 100 M Hz and the bandwidth of the desired signal is 100 kHz , the decimation factor will be in the neighborhood of 1000. Since the DDC hardware is going to need to decimate the input signal by a large factor, the decimation will be broken up into a cascade of two to three decimating lters. The rst lter in the cascade is going to have to operate at a fairly high sample rate. Because of this, the rst lter in the cascade was chosen to be a cascaded integrator-comb (CIC) lter [14]. These lters have a low-pass response and are multiplier-free. With applications of the Noble identities, these lters can also be made to decimate or interpolate. After the CIC lter partially decimates the input signal, a more complicated lter can be implemented to perform the rest of the decimation. Due to this, the next lter(s) in the cascade were chosen to be polyphase decimating lters [2, 5]. The theory of each of these types of lters are described in the following sections.
1.4
CIC Filter Theory As mentioned before, a cascaded integrator comb (CIC) lter is a multiplier free lter
that has a low-pass response1 . These lters can also be used as a decimating lter. As the
1
4 name suggests, a CIC lter is constructed by cascading two simple lter structures together: combs and integrators. Figure 1.1 shows the structure of each of these building blocks. The more integrator and comb lters that are cascaded together, the better the CIC lter does at ltering. The CIC lter exhibits better stopband attenuation, but the sinc shaping in the passband is more pronounced. In essence, a cascade of an integrator and a comb lter is equivalent to an FIR lter with an impulse response of a rectangular window of length M . This translates to a sinc shaped lter response. Figure 1.2 shows the frequency response of CIC lters with one, three, and ve stages to further illustrate this point. In order to make this a decimating lter, N integrator lters are cascaded together followed by N comb lters and nally by a downsampler. Figure 1.3 shows a block diagram of this cascade. The transfer function of the decimating CIC lter shown in g. 1.3 is 1 z RM 1 z 1
N
H (z ) =
H ( ) =
where R is the decimation factor of the lter, M is the dierential delay (or the number of samples to delay the input signal in the comb stages), and N is the number of stages in the CIC. Using one of the Noble identities, the downsampler can be pushed before the comb lter cascade. This is shown in g. 1.4. z 1 z M IN OUT
(a) Integrator Filter
IN
(b) Comb Filter
OUT
5
Frequency Response of CIC Filter, N = 1
10
20
30
|FFT| (dB)
40
50
60
70
80 0
0.5
1.5
2.5
3.5
4.5 x 10
5
6
10
20
30
|FFT| (dB)
40
50
60
70
80 0
0.5
1.5
2.5
3.5
4.5 x 10
5
6
10
20
30
|FFT| (dB)
40
50
60
70
80 0
0.5
1.5
2.5
3.5
4.5 x 10
5
6
Fig. 1.2: Frequency response of three CIC lters, each with a dierent number of stages.
Fig. 1.3: Block diagram of a CIC decimator. The structure shown in g. 1.4 is desirable because in this conguration, the comb cascade can operate at the lower sample rate. There are several advantages for using a CIC lter. The rst reason is that they are multiplier free, making them ideal for high sample rate applications. Secondly, they can be organized such that they decimate the incoming signal while at the same time ltering with a low-pass lter to avoid aliasing in the frequency domain. One disadvantage of the CIC lter, however, is that they have relatively large gain. The gain of a CIC lter is (RM )N . This leads to large accumulator registers in the integrator stages when xed-point arithmetic is used. If the bit width of the accumulator registers is not sucient to allow for the gain of the lter, they can overow and cause the lter to be unstable. It has been shown [6] that if the output bit width follows
(1.1)
where Bout is the bit width of the CIC lter output and Bin is the bit width of the input to the CIC lter, then the accumulators will not overow and the lter will be stable. It can be seen from (1.1) that the bit width of the accumulators can be quite large. With modern FPGAs however, registers are plentiful. Due to this, full precision according to (1.1) will be kept throughout the CIC lter and quantized before the next lter processes the data. Another disadvantage of the CIC lter is that it has a sinc shaped frequency response. This could lead to unwanted attenuation in the passband of the lter. To correct this, a N Integrators N Combs (M delay)
IN
OUT
Fig. 1.4: Block diagram of a decimating CIC lter in which the downsampler has been pushed before the comb cascade using a Noble identity. Notice that the comb lters now delay the input signal by M samples instead of RM samples as in g. 1.3.
7 CIC correction lter [7] usually follows a decimating CIC lter to correct the unwanted droop. The lter that will follow the CIC lter and decimate the signal to its nal desired sample rate is a polyphase FIR lter.
1.5
Polyphase FIR Filter Theory A decimating FIR lter is constructed by taking a prototype lter (a low-pass lter
radians or
1 2M
factor) and decomposing the coecients into several shorter polyphase lters in such a way that a Noble identity can be invoked to push the downsampling operation before the polyphase representations of the lter2 . This is desirable for this application for two main reasons: 1. The polyphase lters operate at the slower sample rate. 2. A single FIR lter can be used to both downsample and lter the input signal to avoid aliasing in the downsampling process. The rst step in constructing a polyphase representation is to decompose the coecients, h(n), into M dierent polyphase lters, each with
N M
of taps in the prototype lter and M is the decimation factor. This decomposition can be visualized by writing the Z-transform of h(n) in the following way:
+ + +
h(2M + 0)z 2M
+ ...
...
8 H0 (z M ) +z 1 H1 (z M ) = +z 2 H2 (z M ) ... +z M 1 HM 1 (z M ). Now, each row in (1.2) can be looked at as a polynomial in z M , with each row oset with a one sample delay from the row above it. Each row now represents a polyphase lter. Figure 1.5 shows a block diagram that performs the same processing as (1.2) and then downsamples the signal by M . We are now in a position to apply a Noble identity and push the downsampler in front of the polyphase lters. The block diagram showing this operation is shown in g. 1.6. The sequence of delay elements and downsamplers preceding the polyphase lters in g. 1.6 is often replaced with a commutator switch. One or two cascaded stages of these polyphase lters will follow the decimating CIC to nish the decimation of the oversampled input signal coming from the ADC in the system. This concludes the theory of the lters used in this project. There will be two polyphase lters if the droop in the passband of the CIC causes enough distortion to require a CIC compensation lter. If the droop in the passband is acceptable, however, there will only be one decimating polyphase lter in the system. H0 (z M ) z 1 IN z 2 . . . z (M 1) H1 (z M ) H2 (z M ) . . . HM 1 (z M ) M OUT (1.2)
Fig. 1.5: Block diagram showing the processing from (1.2) using polyphase lters and delay elements. The ltered signal is then downsampled.
9 M H0 (z )
z 1 IN z 2 . . . z (M 1)
H1 (z ) OUT
M . . . M
H2 (z ) . . . HM 1 (z )
Fig. 1.6: Block diagram showing a decimating polyphase lter after a noble identity has been applied to the block diagram in g. 1.5, pushing the downsamplers in front of the polyphase lters. This is the processing that will be performed after the CIC lter in the design of this project. 1.6 Conclusion In this chapter, we have described a need for this project and given sucient background theory to understand the terminology used in the following chapters of this report. This chapter has also dened the DSP that is involved with this project and outlined the processing that needs to be taken place for the DDC of the incoming software radio signal. The following chapters will describe the design (in MATLAB) of the lters and the VHDL implementation and verication. The nal chapter will summarize the work completed on this project and outlines possible future work that is related to the work done in this project. Appendix B and Appendix C show the MATLAB and VHDL listings of this design, respectively. These appendices are included for reference.
10
2.1
Introduction As a rst step in the design process, a preliminary MATLAB design was made. The
intended FPGA system was simulated using MATLAB before the digital system was implemented using VHDL. This step in the design process served several purposes. First, a more thorough understanding of how the hardware should work was attained when this step was carried out. Second, intermediate signals from the MATLAB design of the system can be input into a VHDL testbench and used to stimulate certain parts of the design. Third, the MATLAB design was used to determine the tolerable precision of the polyphase FIR lter coecients. Fourth, the performance of the system can be visualized and veried much easier in a MATLAB environment than a VHDL environment. Because of these reasons, a preliminary MATLAB design was implemented.
2.2
Specications To verify correct functionality of the lters in the digital down conversion processing
chain, some general requirements of the spectrum of the incoming signal had to be dened. These specications are shown in Table 2.1. Note that these specications are only to test a single conguration of the software radio. It is necessary to specify a set of specications so that the hardware can be veried for this class of signals. This being said, a main goal of the software radio will be to successfully process other, dierent types of signals when it is implemented in a communications system. To further visualize each specications role and importance, g. 2.1 shows an example spectrum.
11
Specication FS F0
W F F
Table 2.1: Input signal specications. Description The sampling frequency of the ADC used in the system. The carrier frequency of the desired signal. For this design, this specication is xed at 1 4 FS . This makes the demodulation multiplier-less (see discussion below). This species the one-sided bandwidth of the desired spectrum. Frequency separation between wanted signal and unwanted signals in the spectrum. Transition band required of the anti-aliasing lter for the initial decimation.
= 25 MHz
|H (F )|
F (Hz) F0 F F F0 F0 + W F0 + F
Fig. 2.1: A gure showing the role of each of the specications outlined in Table 2.1.
12 Choosing F0 to be
1 4 FS
Normally, the demodulator modulates by sin() and cos() at the carrier frequency F0 , but since F0 = 1 4 FS , the modulators can be simplied: cos (2F0 n) = cos 2 FS n 4 FS n = cos 2 1 n = 0, 4, 8, . . . = 0 n = 1, 3, 5, . . . . 1 n = 2, 6, 10, . . .
(2.1)
The demodulator in the in-phase branch of the receiver can be similarly simplied: 1 n = 1, 5, 9, . . . FS n = sin 0 n = 0, 2, 4, . . . . 2 1 n = 3, 7, 11, . . .
(2.2)
It is important to note, though, that this F0 is not necessarily the true carrier frequency of the desired signal. It is more likely that F0 is going to be an intermediate frequency where an analog front end to the digital receiver has performed a partial demodulation. So to be more precise, F0 is the intermediate carrier frequency. Another important specication that needs to be xed for this example scenario is the overall decimation factor. Suppose that a square root raised cosine (SRRC) pulse shape is used with an excess bandwidth () of 100%. Also assume that we want the nal downsampled signal to be oversampled by a factor of two, that is:
FS,f inal = 2RS , where RS is the symbol rate and FS,f inal is the nal sampling rate after the decimation stages. Because of the SRRC pulse shape, the bandwidth of the signal (W ) can be related
13 to the sampling rate: W = so that FS,f inal = 2RS = 2W = 100kHz, and nally DT OT = FS FS,f inal = 100M Hz = 1000, 100kHz 1 1+ = = RS , 2TS TS
where DT OT is the overall decimation factor. Notice that DT OT can be factored as 23 53 = 8 125. This is convenient because it means that each decimation stage is able to decimate by an integer factor. The CIC lter will decimate by a factor of 125, leaving the polyphase FIR lter to decimate by the remaining factor of 8. To test the design of the lters and to verify their proper operation, a test signal consisting of a sum of cosines at four dierent frequencies will be processed by the lter cascade. The four dierent frequencies were chosen to be: F0 + W , F0 W , F0 + F , and nally F0 F . Obviously, after the ltering and downsampling stages, the rst two frequency components should be intact while the second two frequency components should be ltered out. Figure 2.2 shows the test signal that is applied to the system. Figure 2.3 shows the signal after the test signal was demodulated with the sequence of {1, 0} shown in (2.1). After demodulation, the signal will be downsampled and decimated by a factor of 125 by the CIC lter. Immediately following this decimation, a polyphase lter will lter and downsample the signal by the remaining factor of 8. Figure 2.4 shows a block diagram of the top level system.
2.3
CIC Filter Design Having dened the specications of this test spectrum, the lters can be designed.
As discussed in Chapter 1, the demodulated signal will rst be processed by a CIC lter.
14
x 10
4
X: 2.495e+007 Y: 2.968e+004
Modulated Signal
X: 2.492e+007 Y: 2.952e+004 X: 2.505e+007 Y: 2.964e+004 X: 2.508e+007 Y: 2.943e+004
2.5
|FFT|
1.5
0.5
0 2.49
2.492
2.494
2.496
2.498
2.5
2.502
2.504
2.506
2.508
2.51 x 10
7
Fig. 2.2: Spectrum of the test signal that contains the four frequency components at F0 + W , F0 W , F0 + F , and F0 F . The rst two are desired, whereas the second two frequency components are undesired and should be ltered out.
x 10
16
Demodulated Signal
X: 4.997e+004 Y: 2.546e+016
2.5
X: 7.515e+004 Y: 2.146e+016
|FFT|
1.5
0.5
0 0
5
Continuous Frequency
10
15 x 10
4
Fig. 2.4: Top-level block diagram of the system. At this stage in the downsampling process, the incoming signal is heavily oversampled (FS /2 = 50M Hz whereas W = 50kHz ). This means that the main lobe of the CIC lter has to be fairly narrow, requiring a high number of stages. Through experimentation, it was found that a CIC lter with ve stages had a suciently narrow main lobe. Figure 2.5 shows the frequency response of a CIC lter with ve stages and a dierential delay of two. Notice that the CIC lter will not completely lter out the unwanted frequency component, and also that it does attenuate the desired signal slightly. This attenuation, however, is negligible (in this case) and does not aect the functionality of the receiver. This lter does, however, avoid aliasing before the downsampling operation because it lters out everything except for the two signals that are close to baseband. The demodulated signal after being CIC ltered and decimated by 125 is shown in g. 2.6. Since the eects of the sinc-shaping on the signal from the CIC signal are negligible, there is no need to make the polyphase FIR lter a CIC correction lter [7] and it can simply be designed as a low-pass lter.
2.4
Polyphase FIR Filter Design After the decimation accomplished by the CIC lter, the two frequency components
that remain are separated enough in the spectrum that the polyphase FIR lter can properly lter the remaining unwanted frequency components out of the spectrum while, at the same time, downsampling to the desired sampling rate, FS,f inal . Since the CIC lter decimated the signal by a factor of 125, W is now eectively at (50 125)kHz = 6.25M Hz in the spectrum while the unwanted frequency component lies at (75 125)kHz = 9.375M Hz at a sample rate of
FS 125
prototype lter was designed to be a low-pass lter with a passband (Fpass ) of 6.25M Hz and a stop-band (Fstop ) of 9.375M Hz . This lter was designed using a Chebyshev window
16
10
20 30
|FFT| (dB)
40
50 60
70
80 0
6 x 10
7
5
Fig. 2.5: Frequency response of the CIC lter with ve stages. At W , the frequency of interest, the attenuation is about -0.56 dB. At W + F , the rst unwanted frequency component, the attenuation is about -1.28 dB.
2.5
x 10
14
X: 6.25e+006 Y: 2.036e+014
2
X: 9.375e+006 Y: 1.73e+014
1.5
|FFT|
0.5
0 0
10
12
14
16
18 x 10
6
Fig. 2.6: Test spectrum after CIC lter has decimated it by 125.
17 with 60 dB of attenuation in the stop-band. To achieve the specied stop-band attenuation, 240 lter taps were used. Figure 2.7 shows the frequency response of the designed lter. In the VHDL implementation, the lter coecients are going to be represented as twos-complement signed integers. This means that the designed lter coecients need to be quantized. Sucient precision needs to be maintained to keep the necessary stop-band attenuation. After experimentation, it was determined that 14 bits of precision in the coecients were sucient. Figure 2.8 shows the lter response of the lter with quantized coecients along with the full precision lter. Using the designed prototype lter taps, a polyphase lter is created using the process outlined in Chapter 1. In this case, there are 240 taps and a downsampling factor of eight, so the polyphase lterbank will have eight lters, each with 30 ( 240 8 ) taps (see g. 1.6). After the polyphase lter is designed, the CIC decimated signal is further ltered and downsampled. Figure 2.9 shows the nal, fully decimated signal. As you can see, the lter cascade lters out all the unwanted signal components for this example spectrum and avoids aliasing in the downsampling operations simultaneously.
0 10 20 30
|FFT| in dB
Filter response F
pass stop
40 50 60 70 80 90 100 0
5
Continuous Frequency (Hz)
10
15 x 10
6
Fig. 2.7: Frequency response of the designed low-pass prototype lter. Notice that the stop-band attenuation is actually 80 dB. This is because the lter was designed above specs to account for quantization error when xed point coecients are used.
18
20
40
|FFT| in dB
60
80
100
120 0 5
Continuous Frequency
10
15 x 10
6
Fig. 2.8: Frequency response of the quantized low-pass prototype lter. The frequency response of the full precision lter is also shown for comparison.
18 16 14 12 10
|FFT|
x 10
12
X: 5e+007 Y: 1.68e+013
8 6 4 2 0 0
6
Continuous Frequency (Hz)
10
12 x 10
7
Fig. 2.9: Spectrum of the fully decimated signal. This signal is sampled at the desired sample rate, FS,f inal = 100kHz , which is twice the symbol rate of the communications system.
19 2.5 Conclusion In this chapter, a test signal was created and the appropriate lters were designed to properly process this signal. As you can see from the preceeding sections, the lters designed properly lter and downsample the signal such that aliasing is avoided. Also, the signal is decimated to the appropriate sample rate. The sample rate is low enough now that something like a DSP chip can be used to incorporate further exibility in the signal processing that remains to make decisions on what symbols were sent.
20
3.1
Introduction For reasons discussed in Chapter 1, the down conversion of the signal is performed in
an FPGA. This allows for the exibility required of a software radio. In order to make the design exible, VHDL generics were incorporated into the design. In addition to generics, generate for loops (which were based on the generic parameters) were used to generate the structure of the lters. In order to accommodate the dierent sampling rates that are in the design, one global clock signal is used to drive the ip ops. Clock enable signals are then created and used to drive clock enabled ip ops for the slower sampling rate portions. To implement the math functions required in the antialiasing lters, twos-complement signed, xed point integer arithmetic is implemented on the FPGA. This facilitates the use of the VHDL operators (+,-,*), thus enabling the use of generic adders and multipliers. Also, initializing the FIR lter tap ROMs is done by loading them with les generated by MATLAB. The generic values of the VHDL design are described next.
3.2
Generics As mentioned in the previous section, one important aspect of the design are the
generic parameters. These are used to make the FPGA design exible. In order to change the behavior of the processing, one simply has to change the related generics. Table 3.1 outlines the generics that are used to describe the top level of the design hierarchy. These generics then get mapped to the appropriate modules in the lower levels of the design hierarchy.
21
Table 3.1: Description of generics. generic description B casc in The input bit width of the processing chain, essentially the output bit width of the ADC used in the system. B cic out The output bit width of the CIC lter and the bit width of the accumulators in the integrator stages. D cic The decimation factor of the CIC lter. N stages cic The number of stages in the CIC lter. N poly taps The number of taps in the polyphase FIR lter. B poly coes The number of bits in the coecients of the FIR lter. B poly in The input bit width of the polyphase FIR lter. This is eectively the number of bits to quantize the CIC lter output to before the FIR lter processes the data. B poly out The full precision output of the polyphase FIR lter. This is also the number of bits used in the accumulator registers in the acc D modules. B casc out The output bit width of the lter cascade. This is a quantized version of the FIR lter output. D r The decimation factor of the FIR lter. Also the number of elements in the tap ROM modules. B rom addr The number of bits in the tap ROM module address. This is log2 (D r).
22 As you can see, the behavior of the VHDL design can be greatly modied by simply modifying the generic values. It is important to note, however, that changing a generic changes the entire design. This means that the design needs to be synthesized, mapped, and routed again. This can be a potential problem for a software radio. One possible workaround is to have several dierent FPGA congurations (corresponding to dierent generic values) in on-board memory. The software can then decide which programming image to use to reprogram the FPGA with. A description of the VHDL modules used in the design hierarchy follows this section.
3.3
Design Hierarchy The VHDL design has several dierent levels of hierarchy. This section explains each
level of the hierarchy in detail. Figure 3.1 shows the top level of the hierarchy. The following sections descend into the design hierarchy supplying descriptions of each module.
3.3.1
Demodulator
As shown in g. 3.1, the demodulator module is the rst block in the processing chain. For the reasons discussed in Chapter 2, there are no multipliers in the demodulator circuitry. This module assigns the output according to a two bit counter and (2.1).
INPUT
demod
CIC D cic
q1
FIR D r
q2
OUTPUT
Fig. 3.1: Block diagram of the top level in the design hierarchy. The decimation factor generics for each lter are specied. The q1 and q2 blocks shown are quantizers. They perform quantization using truncation, keeping the upper bits of the input.
The CIC lter is broken down into four dierent levels of hierarchy. The top level of the CIC hierarchy is shown in g. 3.2. A few important things to note about the CIC lter design are: The input is sign extended to B cic out bits, and this amount of precision is kept throughout. B cic out is assumed to be sucient for the accumulations that are occurring in the integrator stages. In other words, the adders in the CIC lter implementation have no carry bits. The CIC lter is pipelined: the accumulator registers are arranged in such a way that there is only one addition in between the register layers [8]. Also, pipeline registers were added in the comb stages in order to only require one subtraction operation in between registers. The next sections describe the Integrators, Downsample, and Combs modules shown in g. 3.2.
CIC Integrators The integrators module of the CIC lter is simply a cascade of several accumulators. How many accumulators to cascade is governed by the N cic stages generic. A generate for loop based on this generic is used to cascade the appropriate number of accumulators in this design. Figure 3.3 shows a block diagram of the structure of this module. It is important to note also that the integrators have to operate at the highest sample rate, therefore, it is critical that they are suciently optimized. The next section shows the design of the downsampler block shown in g. 3.2. D cic
CIC IN
Integrators
Combs
CIC OUT
24 ...
INTS IN
INTS OUT
Fig. 3.3: Integrators module structure. This structure was generated using a generate for loop based on the N stages cic generic of the top-level module. Registers are shown as a block with a triangle on the bottom. CIC Downsampler As mentioned in sec. 3.1, the downsampling operation in the CIC lter is accomplished using a clock enabled register. Two controllers are also in the downsampler module. One control accounts for the latency due to the accumulator registers and outputs an enable signal to the second controller to signal it when to start counting. This ensures that the clock enabled ip op passes on the rst good sample to the rest of the design because it has properly waited for the rst sample to propagate through the accumulators. The second controller generates the clock enable signal that drives the comb ip ops and some of the ip ops in the polyphase FIR lter. The rst controller is based on the N stages cic generic whereas the second controller counts clock cycles according to the D cic generic. Figure 3.4 shows a block diagram of the downsampler module. After the downsampling operation, the data rate is divided by the D cic generic. This means that the comb sections (and the rst half of the FIR lter) can operate at the slower rate.
CIC Combs The nal stage of the CIC lter is a cascade of N comb lters. These lters operate IN d clk start ctrl ce ctrl ce cereg q OUT
Fig. 3.4: Block diagram of the downsampler module in the CIC lter hierarchy. The start ctrl module enables the ce ctrl module to grab the rst good sample.
25
S . As in the CIC integrator stages, a generate for loop based on the N stages cic at DFcic
generic was used to cascade the desired number of comb lters together. A block diagram of the structure of the comb lter cascade is shown in g. 3.5. As you can see from g. 3.5, pipeline registers were added to reduce the combinational path delay. With the extra register layers, there is only one subtractor in between a register. After the comb stage, the signal has been ltered and downsampled by a factor of D cic. After the CIC lter, the signal needs to be downsampled to the nal sample rate. This is accomplished with a polyphase FIR lter.
3.3.3
The polyphase FIR lter is the nal step in the digital down conversion of the signal. As mentioned before, after the CIC lter partially decimates the input signal, it gets quantized and then input to the FIR lter. This is so that the FIR lter can maintain full precision throughout the ltering operations. Also, to make the FIR lter exible, tap ROM modules are loaded from text les. This design method makes it easy to design lter coecients in MATLAB or another software tool and load them into the VHDL design. A block diagram of the top level of the FIR lter hierarchy is shown in g. 3.6. As you can see from g. 3.6, the top level of the polyphase FIR lter hierarchy consists simply of the controllers that are needed to feed the signals needed to do the ltering into the FIR taps block. The FIR taps block is where the ltering actually takes place. Descriptions of the controllers shown are given here: z M COMBS IN ... z M COMBS OUT
Fig. 3.5: A block diagram of the comb lter cascade. The M parameter is called the dierential delay. There is no generic specifying this parameter; it is xed at two for this design.
FIR taps
DATA OUT
Fig. 3.6: Block diagram showing the top level of the hierarchy for the polyphase FIR lter. enable control This controller serves much the same purpose as that of the start ctrl controller shown in g. 3.4. Namely, it outputs an enable signal to the ce control module signaling it when the rst good sample has arrived. The major dierence between start ctrl and enable control is that enable control counts the clock enable signal output from the downsampling module in the CIC lter instead of the global clock signal. This controller accounts for the latency introduced by the pipeline registers in the comb section of the CIC lter. ce control This controller uses both D cic and D r to determine how many cycles of the global clock to count before its clock enable signal is output. Note that this controller counts only the global clock, it does not depend on the clock enable controller from the downsample module in the CIC lter. addr control This controller is a simple down counter that is used to address the tap ROMs in the FIR taps module. It is important to note that this counter can count down from an arbitrary number, it does not have to be a power of two. The following section describes the structure and functionality of the FIR taps module shown in g. 3.6.
FIR Taps Module The FIR taps module is the heart of the polyphase FIR lter. This is where the
27 downsampling and ltering takes place. In a usual polyphase lter bank implementation, there would be several lters operating in parallel (the number of lters is equal to the decimation rate of the lter, in this case, this is described by the D r generic). In order to save resources on the FPGA, this structure was collapsed into one lter. This was accomplished by using tap ROM modules that hold D r coecients and modules that accumulate the tap multiplier outputs for D r cycles [9]. This accumulation is where the eective downsampling operation takes place as well. Figure 3.7 shows the block diagram of this collapsed polyphase FIR implementation. It is also important to note that the structure was implemented using a generate for loop based on the N poly taps generic. Some notes about the design of the FIR taps module are discussed here. The ACCDi modules shown in g. 3.7 accumulate their input for D r cycles. This is where the downsampling operation takes place in the lter. Full precision is kept throughout the lter and quantized at the end. Full precision is kept in the following way: rst, the output bit width of the multiplier is the sum of the bit widths of the two inputs (in terms of generics, this is B rom coes + B poly in). Second, enough guard bits in the accumulator inside the ACCDi modules are added to accommodate both for the accumulation and the adder chain that follows. This is done to avoid having to implement carry chain logic through the adder chain. The bit width of the accumulator registers in the ACCDi modules is set using the generic B poly out. IN ...
ROM0
ROM1
...
ROMN
ACCD0
ACCD1 ...
ACCDN
OUT
Fig. 3.7: Block diagram showing the structure of the FIR taps module in the polyphase FIR lter design hierarchy.
28 3.4 Conclusion This chapter summarized the key points and design methodologies used in translating the DSP design discussed in Chapter 2 into an FPGA design using VHDL. This VHDL implementation obtains the exibility required of a software radio using the generics shown in Table 3.1. The hierarchy of the VHDL design was then summarized and described. The next topic to be discussed is the method of verication used in the design process.
29
Chapter 4 Verication
4.1
Introduction In this chapter, post place and route (PAR) simulations of the VHDL design are com-
pared with outputs from the MATLAB design to verify the correct functionality of the synthesized, placed, and routed VHDL design. Using Xilinx ISE 9.1i software tools1 , the VHDL design was synthesized to several FPGA targets. The post PAR simulations discussed in this chapter used a Virtex5-95sxt FPGA as the target. ModelSim2 simulation software was used to perform the simulations.
4.2
Verication Method In order to verify the VHDL design, intermediate signals from the MATLAB design
were quantized and written to les. These les were then read into a VHDL testbench (using the VHDL textio package) and used to stimulate the design. Next, the VHDL module output was written to a le to compare with the corresponding MATLAB signal. For example, if the CIC lter implementation was to be tested, the demodulator output from MATLAB would be quantized and written to a le. Then the testbench would read in this le and use it to stimulate the CIC lter. The output of the CIC lter module would then be written to a le. Finally, the CIC lter output from the MATLAB simulation could be quantized and compared with the VHDL output. Using this verication method, a simulation was conducted on the top level of the VHDL design hierarchy. Using the test signal described in Chapter 2 as stimulus, the nal downsampled signal from the VHDL module matched exactly to the same signal from the
1 2
30 Table 4.1: Generic values used to generate g. 4.2. generic value B casc in 14 B cic out 54 D cic 125 N stages cic 5 N poly taps 30 B poly coes 14 B poly in 26 B poly out 50 B casc out 24 D r 8 B rom addr 3 MATLAB simulation (as long as the MATLAB signal was quantized to the same xed point precision). Figure 4.2 shows the post PAR ModelSim simulation results. Table 4.1 shows the generic values used for the simulation shown in g. 4.2. As you can see from g. 4.2, the output signal changes at a much slower rate than the input signal. It is important to note also, that the ce out signal shown in the gure is also an output of the system. This is so that the processing that follows the decimation can be synchronized to the output of the FPGA. Figure 4.2 also veries that the design meets the desired sampling rate of the system. In other words, the integrator section of the CIC lter is able to operate at the desired frequency of 100M Hz . In order to verify the functionality of the system however, the output shown in g. 4.2 needs to be compared with the equivalent MATLAB signal. This comparison is shown in g. 4.1. As you can see from g. 4.1, the VHDL implementation and the MATLAB simulation perform the same desired processing of the test signal. A comparison of the VHDL output from g. 4.2 with the VHDL output from g. 4.1 can also be used as further verication.
4.3
FPGA Utilization For reference, a Xilinx ISE 9.1i PAR report that summarizes the utilization of the target
FPGA is included in g. 4.3. Note that the processing that has been described throughout this report has been for a one-dimensional signal (e.g., BPSK or PAM).
31
150
100
Quantized Outputs
50
50
100
Time (samples)
Fig. 4.1: Plot showing quantized outputs from the MATLAB simulation alongside the corresponding outputs from the post PAR top level VHDL simulation.
clk
rst_h
cascade_in
demod_out
ce_out -1
-127
cascade_out 0
165
-183
0
187
-1
-2
-4
-17
21
-21
78
-22
-187
183
-180
176
-175
173
-175
174
-175
174
-175
174
-175
174
100 us
200 us
300 us
Entity:cicwpolyfir_tb_vhd Architecture:behavior Date: Sat Mar 29 2:32:55 PM Mountain Daylight Time 2008 Row: 1 Page: 1
Fig. 4.2: Waveform showing the rst 350s of the top level post PAR simulation. The simulation was performed in ModelSim using input stimulus from the test signal generated in MATLAB. This test signal is described in Chapter 2.
32
33 Device Utilization Summary: Number of Number of Number of Number Number of Number of Number Number Number BUFGs DSP48Es External IOBs of LOCed IOBs RAMB18X2s Slice Registers used as Flip Flops used as Latches used as LatchThrus 2 60 41 0 out out out out of of of of 32 640 640 41 6% 9% 6% 0% 12% 11%
30 out of 244 6949 out of 58880 6949 0 0 6988 out of 58880 11039 out of 58880
11% 18%
Fig. 4.3: An excerpt of a Xilinx ISE 9.1i PAR report outlining the target FPGA utilization for the VHDL design. The target FPGA here is a Xilinx Virtex5 95sxt. If a two-dimensional signal such as QPSK or QAM needs to be processed, an in-phase processing branch needs to be included. Seeing as the processing would be identical for the in-phase branch, these utilization reports need to be roughly doubled if a signal that requires an in-phase branch is required. One thing to note about g. 4.3 is that this design uses 60 DSP48 blocks when there are only 30 taps in the FIR lter. This is because in this design, the multiplication that takes place requires a precision that is above the specication of the DSP48 block, so two of these blocks have to be used for each multiplication in the FIR lter. As it can be seen from g. 4.3, this design uses only a small fraction of the resources available for the target FPGA. Even if a QAM or QPSK signal needs to be processed, this design would only utilize about 20% of the resources available. This opens up the possibility of some of the downstream processing also being done on the FPGA.
4.4
Conclusion In this chapter, the VHDL design and the MATLAB design were compared to verify
the functionality of the VHDL implementation. The method of verication was described
34 and then put to use to verify the functionality of the VHDL implementation. Furthermore, this chapter described the device utilization as reported by the Xilinx ISE 9.1i tool.
35
5.1
Introduction FPGA-based hardware that will take a software radio signal as input and decimate it
to the desired sampling rate has been designed, implemented, and veried. This design is planned to be the rst processing element in a processing chain that will make up a software radio receiver. MATLAB was used to simulate the design at a high level and then VHDL was used to implement the design on an FPGA. Successful post PAR simulations have been obtained for several dierent FPGAs of the Xilinx Virtex family.
5.2
Work Completed The scope of this project has been to design, implement, simulate, and verify the
hardware design summarized above. A summary of the work completed is shown below. Development of DSP theory: Decimating lter architectures and applications were studied. As a result, a cascade of a CIC lter and a polyphase FIR lter was decided to be designed and implemented. Initially, the polyphase FIR lter was going to be made into a CIC correction lter, but later in the design process this was deemed unnecessary. DSP Design: After the general structure of the DSP processing was established, the lters had to be designed. Experiments were conducted using MATLAB to decide on lter parameters such as: - The number of stages in the CIC.
36 - The polyphase lter specications: Passband frequency, cuto frequency, and stopband attenuation. - Polyphase lter design: The polyphase FIR lter was designed using an ideal frequency response and windowing using a Chebyshev window. MATLAB simulation: After the lters were designed, a MATLAB script was written that simulated the cascade of the two lters. A test signal that would simulate a realistic input signal was created and ran through the lter cascade. Several intermediate signals were quantized and written to les in order to verify the VHDL implementation. VHDL implementation: The lter cascade was implemented using VHDL. The use of generics and generate for loops allowed for the exibility required of hardware used in a software radio. Verication: In order to deal with the fact that several sampling rates were present in this design, multi-cycle path specications had to be input into the Xilinx tools to verify that the design would meet timing requirements (see Appendix A). The VHDL implementation was synthesized, placed and routed, and thoroughly simulated using the MATLAB signals mentioned above. Finally, the VHDL output was compared with the MATLAB simulation to ensure that the FPGA would perform the correct processing on the input signal. In summary, some of the necessary hardware for a software radio receiver has been designed. Since the hardware is targeted for an FPGA and was written in VHDL, the design is exible and portable. The VHDL code has also been commented to allow for future work on the design if needed. The MATLAB script used to verify the DSP design is also used to simplify the design process. In particular, a MATLAB script has been written that writes the coecients of the FIR lter to several text les such that they can easily be loaded into the VHDL modules.
37 5.3 Future Work The rst major area of future work in regards to this project consists of verifying the design in an actual FPGA. Because of time and budget constraints, this has not been accomplished at the present time. There are also several other areas of future work that are related to this project. The scope of the project discussed in this report consists of only one of several hardware elements that are needed for a software radio receiver. This being the case, several other projects can be done to construct the other necessary elements that make up an entire software radio receiver. Some of these elements are: An analog front end to the receiver: This circuitry takes the signal from the receiver antenna, demodulates it to the required intermediate frequency ( 1 4 FS ), and then passes this to an ADC. Symbol recovery processing: After the signal is translated from the intermediate frequency and downsampled to the desired symbol rate (by the hardware designed for this project), several other processing steps need to be taken before the sent symbols can be recovered. This processing consists of matched ltering, symbol timing recovery, carrier phase recovery, equalization, and minimum distance decisions. Since the sample rate of the design at this point is a little more manageable, this processing will most likely be done in a DSP chip. This is desirable because these chips can be programmed in a high-level language such as C, giving the design engineer more exibility. As mentioned in Chapter 4, however, there is probably room in the FPGA to do some of these kinds of processing tasks as well. Board design, layout, and fabrication: After the necessary DSP hardware has been designed and implemented, a printed circuit board (PCB), consisting of the necessary hardware, needs to be designed an implemented. This is the ultimate goal of the overall project of which the design in this report is but a small part. If a PCB can be designed, then it can be fabricated at a much smaller cost than a development board with the required functionality. This is an ideal situation for an educational setting.
38 5.4 Conclusion In conclusion, an FPGA design that is exible and portable has been designed for use in a software radio system. This design is not too large to ll a modern FPGA, so additional processing can be performed on the same device if desired. The hardware designed in this project processes the received signal straight from the ADC and decimates it to a more manageable sample rate where a DSP chip can nish the necessary processing in a more exible manner, coinciding with the methodology of a software radio.
39
References
[1] J. H. Reed, Software Radio: A Modern Approach to Radio Engineering. Prentice Hall, 2002. [2] F. J. Harris, Multirate Signal Processing for Communication Systems. 2004. Prentice Hall,
[3] M. Rice, Digital Communications: A Discrete Time Approach. Prentice Hall, 2008. [4] T. Hentschel, Sample Rate Conversion in Software Congurable Radios. Artech House, 2002. [5] T. Bose, Digital Signal and Image Processing. John Wiley and Sons, 2004. [6] E. Hogenauer, An economical class of digital lters for decimation and interpolation, IEEE Transactions on Acoustics, Speech, and Signal Processing, 1981. [7] Understanding CIC Compensation Filters [Online]. Available: http://www.altera. com/literature/an/an455.pdf. [8] Cascaded Integrator-Comb (CIC) Filter V3.0 [Online]. Available: xilinx.com/ipcenter/catalog/logicore/docs/cic.pdf. http://china.
[9] Continuously Variable Fractional Rate Decimator [Online]. Available: http: //www.xilinx.com/support/documentation/application_notes/xapp936.pdf.
40
Appendices
41
A.1
Introduction This appendix describes the synthesis options that were used to synthesize this design
to the FPGA using the Xilinx software tools. This appendix also outlines and describes the methods that were used to apply timing constraints to the design. These timing constraints specify the period for the global clock signal and identify the paths in the design that can take multiple cycles of the global clock due to the downsampling operations present in the processing. These paths are called multi-cycle paths.
A.2
Synthesis Options In order to get the design to synthesize, place, and route properly, several of the
settings of the Xilinx 9.1i synthesizer, mapper, and router were changed. Table A.1 shows the settings that were modied from the default value in the Xilinx tool used. The eect of the synthesis options shown in Table A.1 are outlined below: Ensure that the synthesizer utilizes the block RAM resources embedded in the fabric for the tap ROM modules. The keep hierarchy option tells the synthesizer to keep the hierarchy set up in the VHDL les instead of attening the hierarchy and optimizing the boundaries. Shift register extraction was turned o because it utilized twice as many ip ops for the delay elements in the comb stages. The synthesizer can use LUT elements in each slice as shift registers, but reset logic cannot be included. Reset logic needed to be in the delay elements of the comb lters, so this option was turned o.
42
Table A.1: Modied implementation options. Setting Description Default Synthesis Options Optimization eort high low Keep hierarchy yes no RAM style block auto ROM style block auto Shift register extraction o on Resource sharing o on Register duplication o on Equivalent register removal o on MAP Options Placer extra eort normal none Combinatorial logic optimization on o Register duplication on o Trim unconnected signals o on Optimization strategy balanced area PAR Options PAR eort (overall) high standard Extra eort (highest PAR level only) normal none
43 Equivalent register removal was turned o because the synthesizer optimized elements out of the tap ROM modules if there were two coecients that happened to be the same stored in the same ROM. The other options were set to make the design more optimized and run a little faster. The main eect of the MAP and PAR options was to turn the optimization eort of the tools up. The trim unconnected signals option of the MAP tool had to be turned o because of the quantizer modules. The mapper would see that some of the signals had no load and optimize the logic that created the signals away, eectively optimizing the entire design to nothing. This was obviously a bad thing, so the option that made the mapper do this was turned o.
A.3
Timing Constraints In order to set constraints for the timing of the design, a user constraints le is input
into the Xilinx software tool. The tool then uses this le when it performs a place and route. For this design, the period of the clock was constrained to meet the 100M Hz sample rate. Because of the downsampling operations in both the CIC lter and the polyphase FIR lter, several multi-cycle path constraints also had to be set up. These constraints tell the Xilinx tool that there are paths that are allowed to operate slower than the global clock period constraint. The user constraint le for this design is lt cascade.ucf. This le is shown below.
# global
timing
constraints
NET c l k TNM NET = c l k ; TIMESPEC T S c l k = PERIOD c l k 6 n s HIGH 50 %; # p e r i o d OFFSET = IN 5 n s BEFORE c l k OFFSET = OUT 7 . 5 n s AFTER c l k ; # pad t o s e t u p ; constraint is overconstrained a little
# stepping
level
CONFIG s t e p p i n g = 2 ;
# global
c o n s t r a i n t s on h i g h f a n o u t , non c l o c k
nets
# IF KEEP HIERARCHY I S ENABLED, EN OUT 1 NET DOESN' T EXIST # NET c i c 0 / d e c i m a t o r / d s a m p l e r / e n o u t 1 MAXDELAY = 2 n s ; # NET c i c 0 / d e c i m a t o r / d s a m p l e r / e n o u t 1 MAXSKEW = 1 . 5 ns ;
44
NET c i c 0 / d e c i m a t o r / d s a m p l e r / e n o u t MAXDELAY = 2 n s ; NET c i c 0 / d e c i m a t o r / d s a m p l e r / e n o u t MAXSKEW = 1 . 5 ns ;
# timing groups
f o r comb s e c t i o n s
of
cic
filter
INST c i c 0 / d e c i m a t o r / o u t r e g / o u t p TNM = d s a m p l e o u t ; INST c i c 0 / combs / comb gen [ 0 ] . c m b 1 . f i r s t c m b / o u t r e g / o u t p TNM = comb0 out ; INST c i c 0 / combs / comb gen [ 0 ] . c m b 1 . f i r s t c m b / d e l a y / d e l a y r e g 2 / o u t p TNM = c o m b 0 s r e g o u t ; INST c i c 0 / combs / comb gen [ 1 ] . m i d c m b s . c m b m i d s / o u t r e g / o u t p TNM = comb1 out ; INST c i c 0 / combs / comb gen [ 1 ] . m i d c m b s . c m b m i d s / d e l a y / d e l a y r e g 2 / o u t p TNM = c o m b 1 s r e g o u t ; INST c i c 0 / combs / comb gen [ 2 ] . m i d c m b s . c m b m i d s / o u t r e g / o u t p TNM = comb2 out ; INST c i c 0 / combs / comb gen [ 2 ] . m i d c m b s . c m b m i d s / d e l a y / d e l a y r e g 2 / o u t p TNM = c o m b 2 s r e g o u t ; INST c i c 0 / combs / comb gen [ 3 ] . m i d c m b s . c m b m i d s / o u t r e g / o u t p TNM = comb3 out ; INST c i c 0 / combs / comb gen [ 3 ] . m i d c m b s . c m b m i d s / d e l a y / d e l a y r e g 2 / o u t p TNM = c o m b 3 s r e g o u t ; INST c i c 0 / combs / comb gen [ 4 ] . l a s t c m b . c m b l a s t / o u t r e g / o u t p TNM = comb4 out ; INST c i c 0 / combs / comb gen [ 4 ] . l a s t c m b . c m b l a s t / d e l a y / d e l a y r e g 2 / o u t p TNM = c o m b 4 s r e g o u t ;
# timing groups
for
accumulator
flip
flops
for
fir
filter
INST f i r 0 / f i r / t a p g e n [ 2 9 ] . l a s t t a p . a c c D l a s t / a c c u m u l a t o r TNM = FFS a c c D 2 9 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 8 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 8 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 7 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 7 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 6 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 6 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 5 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 5 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 4 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 4 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 3 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 3 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 2 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 2 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 1 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 1 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 0 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 0 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 9 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 9 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 8 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 8 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 7 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 7 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 6 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 6 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 5 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 5 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 4 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 4 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 3 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 3 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 2 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 2 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 1 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 1 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 0 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 0 a c c ; INST f i r 0 / f i r / t a p g e n [ 9 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 9 a c c ; INST f i r 0 / f i r / t a p g e n [ 8 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 8 a c c ; INST f i r 0 / f i r / t a p g e n [ 7 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 7 a c c ; INST f i r 0 / f i r / t a p g e n [ 6 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 6 a c c ; INST f i r 0 / f i r / t a p g e n [ 5 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 5 a c c ; INST f i r 0 / f i r / t a p g e n [ 4 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 4 a c c ; INST f i r 0 / f i r / t a p g e n [ 3 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 3 a c c ; INST f i r 0 / f i r / t a p g e n [ 2 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 2 a c c ; INST f i r 0 / f i r / t a p g e n [ 1 ] . m i d t a p s . a c c D m i d / a c c u m u l a t o r TNM = FFS a c c D 1 a c c ; INST f i r 0 / f i r / t a p g e n [ 0 ] . f i r s t t a p . a c c D 0 / a c c u m u l a t o r TNM = FFS a c c D 0 a c c ;
# combine
all
g r o u p s above i n t o one b i g t i m e g r o u p accD29 acc accD28 acc accD27 acc accD26 acc accD25 acc accD24 acc accD23 acc accD22 acc accD21 acc accD20 acc accD19 acc accD18 acc accD17 acc accD16 acc accD15 acc accD14 acc accD13 acc accD12 acc accD11 acc accD10 acc accD9 acc accD8 acc accD7 acc accD6 acc
TIMEGRP a c c u m r e g s =
45
accD5 acc accD4 acc accD3 acc accD2 acc accD1 acc accD0 acc ;
# timing groups
for
accumulator outputs
in
fir
filter
INST f i r 0 / f i r / t a p g e n [ 2 9 ] . l a s t t a p . a c c D l a s t / a c c o u t TNM = FFS a c c D 2 9 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 8 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 7 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 6 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 6 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 5 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 4 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 3 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 2 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 1 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 0 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 0 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 9 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 9 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 8 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 7 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 6 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 6 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 5 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 4 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 3 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 2 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 1 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 0 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 0 o u t ; INST f i r 0 / f i r / t a p g e n [ 9 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 9 o u t ; INST f i r 0 / f i r / t a p g e n [ 8 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 7 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 6 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 6 o u t ; INST f i r 0 / f i r / t a p g e n [ 5 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 4 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 3 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 ] . m i d t a p s . a c c D m i d / a c c o u t TNM = FFS a c c D 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 0 ] . f i r s t t a p . a c c D 0 / a c c o u t TNM = FFS a c c D 0 o u t ; # combine all above g r o u p s i n t o one b i g g r o u p accD29 out accD28 out accD27 out accD26 out accD25 out accD24 out accD23 out accD22 out accD21 out accD20 out accD19 out accD18 out accD17 out accD16 out accD15 out accD14 out accD13 out accD12 out accD11 out accD10 out accD9 out accD8 out accD7 out accD6 out accD5 out accD4 out accD3 out accD2 out accD1 out accD0 out ;
TIMEGRP a c c o u t p u t s =
# timing groups
f o r tmp r e g i s t e r s
i n accD modules o f
fir
filter
INST f i r 0 / f i r / t a p g e n [ 2 9 ] . l a s t t a p . a c c D l a s t / tmp TNM = FFS accD29 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 8 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD28 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 7 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD27 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 6 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD26 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 5 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD25 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 4 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD24 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 3 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD23 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 2 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD22 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 1 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD21 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 0 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD20 tmp ;
46
INST f i r 0 / f i r / t a p g e n [ 1 9 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD19 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 8 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD18 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 7 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD17 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 6 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD16 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 5 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD15 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 4 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD14 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 3 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD13 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 2 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD12 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 1 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD11 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 0 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD10 tmp ; INST f i r 0 / f i r / t a p g e n [ 9 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD9 tmp ; INST f i r 0 / f i r / t a p g e n [ 8 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD8 tmp ; INST f i r 0 / f i r / t a p g e n [ 7 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD7 tmp ; INST f i r 0 / f i r / t a p g e n [ 6 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD6 tmp ; INST f i r 0 / f i r / t a p g e n [ 5 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD5 tmp ; INST f i r 0 / f i r / t a p g e n [ 4 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD4 tmp ; INST f i r 0 / f i r / t a p g e n [ 3 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD3 tmp ; INST f i r 0 / f i r / t a p g e n [ 2 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD2 tmp ; INST f i r 0 / f i r / t a p g e n [ 1 ] . m i d t a p s . a c c D m i d / tmp TNM = FFS accD1 tmp ; INST f i r 0 / f i r / t a p g e n [ 0 ] . f i r s t t a p . a c c D 0 / tmp TNM = FFS accD0 tmp ; # group all above g r o u p s i n t o a big timegroup
TIMEGRP accD tmps = accD29 tmp accD28 tmp accD27 tmp accD26 tmp accD25 tmp accD24 tmp accD23 tmp accD22 tmp accD21 tmp accD20 tmp accD19 tmp accD18 tmp accD17 tmp accD16 tmp accD15 tmp accD14 tmp accD13 tmp accD12 tmp accD11 tmp accD10 tmp accD9 tmp accD8 tmp accD7 tmp accD6 tmp accD5 tmp accD4 tmp accD3 tmp accD2 tmp accD1 tmp accD0 tmp ;
# timing groups
for
tap output
registers
in
fir
filter
INST f i r 0 / f i r / t a p g e n [ 2 9 ] . l a s t t a p . r e g l a s t / o u t p TNM = FFS f i r t a p 2 9 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 8 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 7 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 6 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 6 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 5 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 4 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 3 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 2 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 1 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 0 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 0 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 9 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 9 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 8 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 7 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 6 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 6 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 5 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 4 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 3 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 2 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 1 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 0 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 0 o u t ; INST f i r 0 / f i r / t a p g e n [ 9 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 9 o u t ; INST f i r 0 / f i r / t a p g e n [ 8 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 7 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 6 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 6 o u t ;
47
INST f i r 0 / f i r / t a p g e n [ 5 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 4 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 3 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 ] . m i d t a p s . r e g m i d / o u t p TNM = FFS f i r t a p 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 0 ] . f i r s t t a p . r e g 0 / o u t p TNM = FFS f i r t a p 0 o u t ; # group all above g r o u p s i n t o one t i m e g r o u p firtap29 out firtap28 out firtap27 out firtap26 out firtap25 out firtap24 out firtap23 out firtap22 out firtap21 out firtap20 out firtap19 out firtap18 out firtap17 out firtap16 out firtap15 out firtap14 out firtap13 out firtap12 out firtap11 out firtap10 out firtap9 out firtap8 out firtap7 out firtap6 out firtap5 out firtap4 out firtap3 out firtap2 out firtap1 out firtap0 out ;
TIMEGRP t a p o u t p u t s =
# timing groups
f o r rom o u t p u t s
in
fir
filter
# # # USE THESE GROUPS IF BLOCK RAMS ARE USED INST f i r 0 / f i r / t a p g e n [ 0 ] . f i r s t t a p . r o m 0 / Mrom rom out mux00001 TNM = RAMS r o m 0 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 3 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 4 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 5 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 6 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 6 o u t ; INST f i r 0 / f i r / t a p g e n [ 7 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 8 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 9 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 9 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 0 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 0 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 1 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 2 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 3 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 4 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 5 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 6 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 6 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 7 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 8 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 1 9 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 1 9 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 0 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 0 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 1 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 1 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 2 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 2 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 3 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 3 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 4 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 4 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 5 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 5 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 6 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 6 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 7 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 7 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 8 ] . m i d t a p s . r o m m i d / Mrom rom out mux00001 TNM = RAMS r o m 2 8 o u t ; INST f i r 0 / f i r / t a p g e n [ 2 9 ] . l a s t t a p . r o m l a s t / Mrom rom out mux00001 TNM = RAMS r o m 2 9 o u t ; # group all above g r o u p s i n t o one b i g t i m e g r o u p
TIMEGRP r o m o u t p u t s
= rom29 out rom28 out rom27 out rom26 out rom25 out rom24 out rom23 out rom22 out rom21 out rom20 out rom19 out rom18 out rom17 out rom16 out rom15 out rom14 out rom13 out rom12 out rom11 out rom10 out rom9 out rom8 out rom7 out rom6 out rom5 out rom4 out rom3 out rom2 out rom1 out rom0 out ;
48
# # # USE THESE GROUPS IF DISTRIBUTED ROMS ARE USED #INST f i r 0 / f i r / t a p g e n [ 2 7 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 7 o u t ; #INST f i r 0 / f i r / t a p g e n [ 2 6 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 6 o u t ; #INST f i r 0 / f i r / t a p g e n [ 2 5 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 5 o u t ; #INST f i r 0 / f i r / t a p g e n [ 2 4 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 4 o u t ; #INST f i r 0 / f i r / t a p g e n [ 2 3 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 3 o u t ; #INST f i r 0 / f i r / t a p g e n [ 2 2 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 2 o u t ; #INST f i r 0 / f i r / t a p g e n [ 2 1 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 1 o u t ; #INST f i r 0 / f i r / t a p g e n [ 2 0 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 0 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 9 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 9 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 8 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 8 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 7 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 7 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 6 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 6 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 5 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 5 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 4 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 4 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 3 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 3 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 2 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 2 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 1 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 1 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 0 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 0 o u t ; #INST f i r 0 / f i r / t a p g e n [ 9 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 9 o u t ; #INST f i r 0 / f i r / t a p g e n [ 8 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 8 o u t ; #INST f i r 0 / f i r / t a p g e n [ 7 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 7 o u t ; #INST f i r 0 / f i r / t a p g e n [ 6 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 6 o u t ; #INST f i r 0 / f i r / t a p g e n [ 5 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 5 o u t ; #INST f i r 0 / f i r / t a p g e n [ 4 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 4 o u t ; #INST f i r 0 / f i r / t a p g e n [ 3 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 3 o u t ; #INST f i r 0 / f i r / t a p g e n [ 2 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 2 o u t ; #INST f i r 0 / f i r / t a p g e n [ 1 ] . m i d t a p s . r o m m i d / r o m o u t TNM = FFS r o m 1 o u t ; #INST f i r 0 / f i r / t a p g e n [ 0 ] . f i r s t t a p . r o m 0 / r o m o u t TNM = FFS r o m 0 o u t ; ## g r o u p all above g r o u p s i n t o one b i g t i m e g r o u p
# TIMEGRP r o m o u t p u t s = r o m 2 7 o u t r o m 2 6 o u t r o m 2 5 o u t r o m 2 4 o u t # # # # # # rom23 out rom22 out rom21 out rom20 out rom19 out rom18 out rom17 out rom16 out rom15 out rom14 out rom13 out rom12 out rom11 out rom10 out rom9 out rom8 out rom7 out rom6 out rom5 out rom4 out rom3 out rom2 out rom1 out rom0 out ;
# multi
cycle
path
specifications
f o r CIC f i l t e r TO comb0 out T S c l k 1 2 5 ; TO comb0 out T S c l k 1 2 5 ; TO comb1 out T S c l k 1 2 5 ; TO comb1 out T S c l k 1 2 5 ; TO comb2 out T S c l k 1 2 5 ; TO comb2 out T S c l k 1 2 5 ; TO comb3 out T S c l k 1 2 5 ; TO comb3 out T S c l k 1 2 5 ; TO comb4 out T S c l k 1 2 5 ; TO comb4 out T S c l k 1 2 5 ;
TIMESPEC T S c i c m c p 1 = FROM d s a m p l e o u t TIMESPEC T S c i c m c p 2 = FROM c o m b 0 s r e g o u t TIMESPEC T S c i c m c p 3 = FROM comb0 out TIMESPEC T S c i c m c p 4 = FROM c o m b 1 s r e g o u t TIMESPEC T S c i c m c p 5 = FROM comb1 out TIMESPEC T S c i c m c p 6 = FROM c o m b 2 s r e g o u t TIMESPEC T S c i c m c p 7 = FROM comb2 out TIMESPEC T S c i c m c p 8 = FROM c o m b 3 s r e g o u t TIMESPEC T S c i c m c p 9 = FROM comb3 out TIMESPEC T S c i c m c p 1 0 = FROM c o m b 4 s r e g o u t
# multi
cycle
path
specifications
f o r FIR
TIMESPEC T S f i r m c p 1 = FROM comb4 out TIMESPEC T S f i r m c p 2 = FROM r o m o u t p u t s TIMESPEC T S f i r m c p 3 = FROM comb4 out
49
TIMESPEC T S f i r m c p 4 = FROM r o m o u t p u t s TIMESPEC T S f i r m c p 5 = FROM a c c o u t p u t s TO accD tmps T S c l k 1 2 5 ; TO t a p o u t p u t s T S c l k 1 0 0 0 ;
# assign
output
buffers
to use
fast
slew
rate
drivers
NET c a s c a d e o u t < SLEW = FAST ; # NET c a s c a d e o u t <1> SLEW = FAST ; # NET c a s c a d e o u t <2> SLEW = FAST ; # NET c a s c a d e o u t <3> SLEW = FAST ; # NET c a s c a d e o u t <4> SLEW = FAST ; # NET c a s c a d e o u t <5> SLEW = FAST ; # NET c a s c a d e o u t <6> SLEW = FAST ; # NET c a s c a d e o u t <7> SLEW = FAST ; # NET c a s c a d e o u t <8> SLEW = FAST ; # NET c a s c a d e o u t <9> SLEW = FAST ; # NET c a s c a d e o u t <10> SLEW = FAST ; # NET c a s c a d e o u t <11> SLEW = FAST ; # NET c a s c a d e o u t <12> SLEW = FAST ; # NET c a s c a d e o u t <13> SLEW = FAST ; # NET c a s c a d e o u t <14> SLEW = FAST ; # NET c a s c a d e o u t <15> SLEW = FAST ; # NET c a s c a d e o u t <16> SLEW = FAST ; # NET c a s c a d e o u t <17> SLEW = FAST ; # NET c a s c a d e o u t <18> SLEW = FAST ; # NET c a s c a d e o u t <19> SLEW = FAST ; # NET c a s c a d e o u t <20> SLEW = FAST ; # NET c a s c a d e o u t <21> SLEW = FAST ; # NET c a s c a d e o u t <22> SLEW = FAST ; # NET c a s c a d e o u t <23> SLEW = FAST ; NET c e o u t SLEW = FAST ;
The rst several lines of lt cascade.ucf set up the period constraint of the global clock and set up the input to pad and pad to output constraints as well. The next lines of lt cascade.ucf set up the muti-cycle path constraints of the design. The TNM -- NET syntax was used for this. This syntax uses the instantiation names of the synthesized nets in the design to create timing groups. After several of these groups are outlined for each path, the TIMEGRP statements group these individual groups into one big group. After each of these groups are set up, the TIMESPEC -- FROM -- TO statements dene how long each path is allowed to take based on the global clock period constraint. This was the general method used to specify the multi-cycle paths in the design due to the downsampling operations performed. The last section of the le tells the MAP tool to use fast slew rate drivers for the output signals. This speeds up the pad to out timing specications a great deal. It is important to note here that since the multi-cycle path constraints are based on the instantiation names of the design, they could possibly change if the generic values of
50 the design are changed. For example, if the number of stages in the CIC lter is modied, then some paths outlined in lt cascade.ucf would not be constrained or not exist anymore. This was a main reason for including this appendix. If the structure of the lter cascade is modied, the user constraints le needs to be modied or the design will not be constrained properly and the MAP tool will not be able to optimize the design suciently.
A.4
Conclusion The synthesis, MAP, and PAR options that were changed to make the design synthesize
and route correctly were outlined in this appendix. Also, the timing specications and the method for constraining the design was also outlined.
51
B.1
Main Script
des2.m
% % des2.m % Jake Talbot % June 2 1 , 2007 % d e s 2 . m ( d e s i g n #2) t h i s % frequency % des2.m % below : % % The major % o n l y two % because difference filters it in o f d e s 2 . m from d e s 1 . m the decimation cascade is the fact of that three. there This are is there is script is the second of for the the design of the intermediate receiver.
process except
software
radio
differences
outlined
instead
was f o u n d t h a t a t t h e p a s s b a n d e d g e o f attenuation ,
t h e CIC f i l t e r , filter
was deemed
That b e i n g t h e c a s e ,
% polyphase
and a d e c i m a t e by f o u r
d e c i m a t e by e i g h t
polyphase
filter
this
script
writes
the quantized
and
other
necessary
design
implementation.
frequency to t h e CIC f i l t e r
order
an e a s i e r
% on t h e FPGA. % % August 1 7 , 2007 % R e v i s i o n #2 : % of leaving it quantized at full the output o f This for the is cic so I filter could t o 26 test bits instead
precision.
the polyphase
% filter
t h e huge b i t
w i d t h coming from
% the output %
% September 8 , 2007 % R e v i s i o n #3 : % instead of quantized it at the output o f full the polyphase This is filter t o 24 bits
leaving
precision.
52
% element in the signal processing bits c h a i n ( p r o b a b l y a DSP) will n o t be a b l e
from t h e FPGA.
Instead all
of
overwriting gets
the data
% plotted %
a t t h e end i n one
% J anuary 1 5 , 2008 % R e v i s i o n #5 : % versions % % March 1 5 , 2008 % R e v i s i o n #6 : added some more p l o t s t h a t were i n c l u d e d i n my t h e s i s . of added t h e d e l e t e . t x t l i n e the .txt files are used i n to ensure that the newest
all
t h e VHDL i m p l e m e n t a t i o n .
delete .txt ;
stages factor
% number o f
f c n s = ( 0 : NFFT 1 ) F s a d c /NFFT ; NFFT2 = 2 1 8 ; % number o f f c n s 2 = ( 0 : NFFT2 1 ) F s a d c /NFFT2 ; Bin = 1 4 ; Bcoeffs = 14; Bcicout = 26; Bfirout = 50; Bcascout = 2 4 ; f w a n t = 50 e 3 ; funwant = 75 e 3 ; % # of % # of % # of % # of % # of bits bits bits
continuous fft of
filter
% one s i d e d bandwidth ( Hz )
% f r e q u e n c y where a n o t h e r unwanted s i g n a l
% % Create a t e s t
signal
% s e c o n d unwanted f r e q u e n c y component % first % second % period of of of t h e wanted f r e q u e n c y component t h e wanted f r e q u e n c y component highest for f r e q u e n c y component
% time index
cosines
t e s t s i g = c o s d ( 2 p i F1 n ) + c o s d ( 2 p i F2 n ) + c o s d ( 2 p i Fo 1 n ) + c o s d ( 2 p i Fo 2 n ) + c o s d ( 2 p i ( F1 + 100 e 3 ) n ) ; if ( noise flag ) var = 0 . 0 1 ; n o i s e = v a r randn ( 1 , % add n o i s e % variance length (n ) ) ; into of signal noise
...
% vector
t e s t s i g = t e s t s i g + noise ;
% add n o i s e
t o modulated
signal
53
end
% quantize
test sig
and w r i t e
to a
file
f o r VHDL t e s t b e n c h
t e s t s i g 1 = t e s t s i g / ( max ( a b s ( t e s t s i g ) ) + 1 ) ; test sig q = floor (( test sig1 2 ( Bin 1 ) ) ) ; test sig q , Bin ) ;
test
length (n ) ) ;
% c o s ( p i / 2 ( 0 : 4 : end ) ) = 1 % c o s ( p i / 2 ( 2 : 4 : end ) ) = 1
b b s i g = mod sig
b b s i g q = mod sig
% write
q u a n t i z e d demodulated
signal
to a
file
f o r VHDL t e s t b e n c h Bin ) ;
bb sig q ,
% % D e s i g n d e c i m a t i n g CIC f i l t e r Bacc = Bin + c e i l (N l o g 2 ( R c i c M) ) ; h s i n g l e = ones (1 , hcic = hsingle ; for j = 1 :N 1 ; h c i c = conv ( h c i c , end hsingle ) ; % cascade N stages of s i n g l e CIC f i l t e r s R c i c M) ; % # of bits required in accumulators
% impulse
response
o f a s i n g l e CIC
% % F i l t e r and downsample s i g n a l w/ CIC b b s i g = conv ( b b s i g , hcic ); hcic ); % filter the baseband signal signal
b b s i g q = conv ( b b s i g q ,
% filter
the quantized
i n t s i g 1 = downsample ( b b s i g ,
R cic ) ;
% downsample t h e
filtered
signal
i n t s i g 1 q = downsample ( b b s i g q ,
R cic ) ;
% quantize
the
values
of
i n t s i g 1 q down t o 26
bits
i n t s i g 1 q = f l o o r ( ( i n t s i g 1 q / 2 B c i c o u t ) ) ;
% write
the quantized ,
decimated
signal
to a
file
f o r VHDL t e s t b e n c h e s Bcicout ) ;
int sig1 q ,
cutoff filter
% d e s i g n an l p f
% q u a n t i z e and w r i t e
filter
coefficients
to a
file
f o r VHDL i m p l e m e n t a t i o n
h p r a c = h p r a c / ( max ( a b s ( h p r a c ) ) + 1 ) ; hprac q = f l o o r ( ( hprac 2( B c o e f f s 1 ) ) ) ; f i l e p r i n t ( [ ' p o l y c o e f f s L ' , num2str ( L ) , ' B ' , num2str ( B c o e f f s ) ] , hprac q , Bcoeffs );
polyphase 0);
filter %p o l y p h a s e d e c i m a t e 1);
Bcoeffs , R fir ,
hprac q ,
Bcoeffs ,
% quantize
the polyphase
filter
output to Bcascout
/ 2( B f i r o u t Bcascout + 2 ) ) ;
54
% write
final
q u a n t i z e d downsampled s i g n a l
to
file
f o r VHDL t e s t b e n c h Bcascout ) ;
fin sig q ,
% % Plot
spectra
of
all
intermediate
signals
% plot
the spectrum o f
t h e modulated
signal
x l a b e l ( ' C o n t i n u o u s F r e q u e n c y ( Hz ) ' , y l a b e l ( ' | FFT | ' , ' fontsize ' , 14); t i t l e ( ' Modulated S i g n a l ' , x l i m ( [ ( 2 5 e 6 100 e 3 ) ,
14);
( 2 5 e 6 + 100 e 3 ) ] ) ;
% plot
the spectrum o f
the demodulated
signal
figure (2); plot ( fcns2 , a b s ( f f t ( b b s i g , NFFT2 ) ) , ' linewidth ' , 14); 14); 2);
t i t l e ( ' Demodulated S i g n a l ' , y l a b e l ( ' | FFT | ' , xlim ( [ 0 , ' fontsize ' ,
14);
150 e 3 ] ) ;
% plot
signal
figure (3); plot ( fcns , a b s ( f f t ( i n t s i g 1 , NFFT) ) , ' linewidth ' , ' fontsize ' , 2);
x l a b e l ( ' C o n t i n u o u s F r e q u e n c y ( Hz ) ' , y l a b e l ( ' | FFT | ' , ' fontsize ' , 14); t i t l e ( [ ' CIC d e c i m a t e d xlim ( [ 0 , 125150 e3 ] ) ;
14);
s i g n a l , R { c i c } = ' num2str ( R c i c ) ] ,
14);
% plot
t h e p o l y p h a s e FIR d e c i m a t e d
signal
figure (4); plot ( fcns , a b s ( f f t ( f i n s i g , NFFT) ) , ' linewidth ' , ' fontsize ' , 2); 14);
x l a b e l ( ' C o n t i n u o u s F r e q u e n c y ( Hz ) ' , y l a b e l ( ' | FFT | ' , ' fontsize ' , filtered 14); t i t l e ( [ ' Polyphase
% plot
the
frequency
response
of
t h e CIC f i l t e r
figure (5); H c i c = a b s ( f f t ( h c i c , NFFT2 ) ) ; plot ( fcns2 , 10 l o g 1 0 ( H c i c /max ( H c i c ) ) , ' linewidth ' , 2); ...
t i t l e ( [ ' F r e q u e n c y R e s p o n s e o f CIC F i l t e r , N = ' , num2str (N ) ] , ' fontsize ' , y l a b e l ( ' | FFT | xlim ( [ 0 7 e5 ] ) ; y l i m ([ 80 5]); ( dB ) ' , 14); ' fontsize ' , 14); x l a b e l ( ' C o n t i n u o u s F r e q u e n c y ( Hz ) ' , ' fontsize ' ,
14);
leprint.m
function
[ ] = f i l e p r i n t ( name ,
vector ,
numbits )
% Jake Talbot % June 2 1 , 2007 % fileprint.m this script is u s e d t o open a file with the filename
% n a m e . t x t , and d e p e n d i n g % on t h e both f l a g , % % INPUT ARGUMENTS % % % name : a s t r i n g numbits : that will is be t h e name o f t o be w r i t t e n that the the file written to. writes the values t o t h e opened file.
vector : a vector
that
to the
file. to.
t h e number o f
bits
v e c t o r h a s been q u a n t i z e d
fname = [ name ,
% create % open
file
' . 0 f \n ' ] ,
vector ) ;
lp r.m
function
[ l p f c o e f f s ] = l p f i r ( Fc , Fs , L )
% Jake Talbot % June 2 0 , 2007 % lp fir.m ( low p a s s f i r ) this function designs a lowpass in filter using a
% c h e b y s h e v window w i t h 65 o r more dB a t t e n u a t i o n % INPUT ARGUMENTS % % % % % % % Fc : the desired that cutoff frequency i n Hz.
the stopband.
Note t h a t
this it
is is
frequency frequency
specifies
desired
frequency.
t h e s y s t e m i n Hz t a p s , must be d i v i s i b l e by 2
filter
hid = f c s i n c ( f c ( ( 0 : L 1) L / 2 ) ) ;
% i d e a l LPF i m p u l s e
56
% % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % win = window ( @chebwin , L , win = win ' ; l p f c o e f f s = hid . win ; % window i d e a l filter t o make a p r a c t i c a l one 65); % c r e a t e a Chebyshev window
polylt.m
function
f i r f i l t , D,
Bcoeffs ,
print )
% Jake Talbot % June 2 0 , 2007 % polyfilt.m ( polyphase f i l t e r ) t h i s MATLAB f u n c t i o n it ' s decimating is used to take a
decompose i n t o filter
polyphase signal.
and downsample t h e i n c o m i n g
signal
coefficients decimation
bits the
printing
coeffs
several
files
o u t s i g the decimated
signal
% o f a tapped d e l a y % note that % implied % % REVISIONS % August 1 3 , 2007 % % % % % % % September 5 , 2007 % % changed t h e function so added c o d e t o files filter
polyfilt.m
does not
r e c o v e r from t h e process.
s c a l i n g by D t h a t
occurs
t h e downsampling
the polyphase i
to
several
To do t h i s , to
t h e number o f
( B c o e f f s ) , and a f l a g
( p r i n t ) were added t o
this
as input arguments.
filtering I
o p e r a t i o n from t h e test
filter
function
t o t h e conv
c o u l d more t h o r o u g h l y
t h e VHDL i m p l e m e n t a t i o n .
% % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % S e t up g e n e r a l parameters
z e r o s ( 1 , D c e i l (N/D)N ) ] ; % e n s u r e % f i n d new l e n g t h % length % find of of filter filters signal % ensure input signal
N = length ( f i r L = N/D;
polyphase of input
length
z e r o s ( 1 , D c e i l (M/D) M) ] ; % f i n d new l e n g t h of
that D divides K
M = length ( i n s i g ) ;
57
K = M/D; out len = K + L 1; p o l y f i l t s = z e r o s (D, L ) ; p o l y i n = z e r o s (D, K ) ; p o l y o u t = z e r o s (D, out len ); % # o f columns i n commutator a r r a y % length of output array for for polyphase filters , e a c h row is a filter
% array % array
fname = [ ' rom ' , num2str ( i 1 ) ] ; printbinary ( end end polyfilts (: , i ) , Bcoeffs , fname ); % print coeffs to file in binary
filter
% % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % ind = 1 ; polyin (1 , 1) = i n s i g ( ind ) ; % first row o f first column is o n l y non z e r o value i n column
ind = ind + 1 ; for i = 2 :K for j = D: 1 : 1 polyin ( j , % l o o p t h r o u g h columns % l o o p t h r o u g h rows backwards i ) = i n s i g ( ind ) ; % d e a l o u t s a m p l e s commutator style
% % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % Filter the dealt out input signals with the polyphase filters
: ) = conv ( p o l y f i l t s ( i ,
% % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % out sig = zeros (1 , ind = 1 ; for i = 1: out len out len ); % vector % index for to hold the output signal signal
output
% l o o p t h r o u g h columns
58
for j = 1 :D % l o o p t h r o u g h rows i ); % add up a l l numbers i n column
r e a d y t o be o u t p u t by t h e e n d .
printbinary.m
function
PRINTBINARY t a k e s
values
prints
coefficients
polyphase process
the
intermediate
frequency
to a
s o t h a t t h e y can be u s e d t o l o a d t h e ROM
t h e VHDL i m p l e m e n t a t i o n .
vector
t h a t you d e s i r e bits in
to
in
binary format
B t h e number o f fname a s t r i n g be w r i t t e n to
representing
file
file
in
vector
into B bit
% l o o p t h r o u g h rows
j = 1: col i f ( x ( i , j ) == ' / ' ) x( i , j ) = '1 ' ; end f p r i n t f ( fid , '%c ' , x ( i , j ) ) ; % p r i n t ' ' ); elements of vector to a file , one c h a r a c t e r at a time % if number i s negative , convert '/ ' s to 1 ' s
end f p r i n t f ( fid , end fclose ( fid ); % close the file '%c \ n ' , % print a newline character to the file
59
C.1
lt cascade.vhd
Company : Utah S t a t e E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool N poly taps D cic Generics B casc in B cic out : # of : # of for b i t s on i n p u t of cascade , of which is also the input of t h e CIC . bit the versions : D e s c r i p t i o n : f i l t c a s c a d e . vhd T h i s VHDL e n t i t y the the intermediate features of is the top signal level in the hierarchy of 10:36:44 08/20/2007 University
Jake Talbot
processing
chain .
Some o f clock
follows :
signals
are
generated ,
n o t an i n t e r n a l l y are used to
Generic of
s u b t r a c t o r s , and m u l t i p l i e r s
facilitate
easy changes
b i t s on t h e o u t p u t the
t h e CIC ,
the accumulator
width
The a c c u m u l a t o r
b i t width ,
and t h u s t h e # o f equation :
d e t e r m i n e d by t h e
following
decimation followed ,
factor
than t h e a c c u m u l a t o r s factor of
t h e CIC ,
note that
width o f
N stages cic
: # of
stages
t h e number o f : # of taps in
filter .
this
d e p e n d s on t h e
length
original
prototype
filter
and t h e
60
R e v i s i o n : R e v i s i o n 0.01 File Created design . signal . R e v i s i o n 1 November 4 , 2007 I added t h e d e m o d u l a t o r t o t h e T h i s module is what t a k e s cycle the output of latency of Internal Signals : The o u t p u t of the demodulator , i n p u t t o CIC f i l t e r . first quantizer . first quantizer . quantizer . flip flops that ce out : rst h Ports clk : The g l o b a l the clock for the filter c a s c a d e . The p a r a m a t e r s above and / o r have t o be s u c h t h a t t h e of at least 100 MHz . This reset input design D fir : decimation f o r eqn . ) . B poly coeffs B poly in : # of bits in the polyphase of filter coefficients . filter . This is to before factor of the polyphase filter ( see D fir description
: # of
b i t s on t h e i n p u t
the polyphase
effectively
what you want t h e CIC o u t p u t t o be q u a n t i z e d filter processes of the data . the polyphase overflow the filter .
b i t s on t h e o u t p u t
Full
precision
usually : # of
maintained to avoid of
b i t s on t h e o u t p u t is
filter
precision
filter ,
factor is
the polyphase
Note t h a t t h e number o f
taps
filter
g i v e n by t h e e q u a t i o n :
n taps = c e i l ( n prototype taps / D fir ) where n t a p s is t h e number o f is taps in taps the polyphase in the filter , f i l t e r , and
original
: number o f This
the polyphse
filter .
g i v e n by t h e
B rom = c e i l ( l o g 2 ( D f i r ) ) This equation t a p ROM o f holds because there are D fir elements i n each
the polyphase
filter .
asserted
high
reset
input .
resets cascade in in
the
software of
radio . the cascade . enabled This clock that filter enable are
This is
signal
meant t o operate
clock
f l i p f l o p s of the
a t t h e same r a t e
as the output
: The o u t p u t o f
the
filter
cascade .
This
is
usually
the
quantized
polyphase
filter
output .
demod out
: Output o f CIC f i l t e r ,
input to
I n p u t t o p o l y p h a s e FIR f i l t e r , : Output o f :
output o f
p o l y p h a s e FIR f i l t e r ,
C l o c k e n a b l e o u t p u t o f CIC f i l t e r , a t t h e same s a m p l e r a t e
as the output
p o l y p h a s e FIR f i l t e r , final ,
flops also
s l o w e s t sample r a t e .
This
ce out
signal
the block .
D e p e n d e n c i e s :
T h i s added an e x t r a
to the system .
61
A d d i t i o n a l Comments : l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; the value that the counter in the start cnt module o f the c i c / decimator
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
filt cascade (
is : i n t e g e r := 1 2 ;
generic
B casc in :
i n t e g e r := 5 2 ;
i n t e g e r := 1 2 5 ; : : i n t e g e r := 5 ; i n t e g e r := 3 0 ; : i n t e g e r := 1 4 ;
i n t e g e r := 2 6 ; i n t e g e r := 5 0 ; i n t e g e r := 2 4 ;
i n t e g e r := 8 ; : i n t e g e r := 3 ) ;
i n STD LOGIC ;
rst h
i n STD LOGIC ; : i n STD LOGIC VECTOR ( B c a s c i n 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B c a s c o u t 1 downto
cascade in ce out :
architecture
struc
of
filt cascade
is
i n STD LOGIC ;
end component d e m o d i ;
integer ; integer ;
i n STD LOGIC ; i n STD LOGIC VECTOR ( B c i c i n 1 downto 0 ) ; o u t STD LOGIC ; o u t STD LOGIC VECTOR ( B c i c o u t 1 downto 0));
cic out
62
end component c i c ;
component generic
i n STD LOGIC ;
rst h ce in
i n STD LOGIC ; i n STD LOGIC ; : i n STD LOGIC VECTOR ( B i n p u t 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B o u t p u t 1 downto
insample ce out :
B out port
( inp outp :
end component q u a n t i z e r ;
demod out
: STD LOGIC VECTOR ( B p o l y i n 1 downto 0 ) ; : STD LOGIC VECTOR ( B p o l y o u t 1 downto 0 ) ; tmp ce2 : STD LOGIC ;
begin
demod0 :
demod i
g e n e r i c map ( B = > B casc in ) p o r t map ( clk = > clk , rst h = > rst h , inp = > cascade in , outp = > demod out ) ;
cic0
cic B cic in = > B casc in , B cic out = > B cic out , cic in = > demod out , D factor = > D cic , ce out = > tmp ce1 ,
g e n e r i c map (
N = > N stages cic ) p o r t map ( clk = > clk , > rst h , rst h = > tmp cic out ) ; cic out =
q0 :
fir0
poly fir top N cic stages = > N stages cic , D cic = > D cic , B coeffs = > B poly coeffs , D fir = > D fir ,
> N poly taps , g e n e r i c map ( N t a p s = > B poly in , B input = clk = > clk ,
> B rom addr ) B rom addr = p o r t map ( rst h = > rst h , ce in = > tmp ce1 , outsample = > fir out ); insample = > fir in , ce out = > tmp ce2 ,
63
q1 : quantizer B out = > B casc out )
> B poly out , g e n e r i c map ( B i n = p o r t map ( i n p = > fir out , c e o u t tmp ce2 ;
end s t r u c ;
of
filt cascade
is
f o r demod0 : use
demod i
e n t i t y work . d e m o d i ( behv ) ;
end f o r ;
for
cic0
cic
use
c o n f i g u r a t i o n work . c i c c o n ;
end f o r ;
f o r q0 , q1 : use
quantizer
e n t i t y work . q u a n t i z e r ( behv ) ;
end f o r ;
for
fir0
use
c o n f i g u r a t i o n work . p o l y f i r t o p c o n ;
C.2
demod i.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool Below a r e D e s c r i p t i o n : 10:26:13 07/06/2007
v e r s i o n s : ISE 9 . 1 i T h i s VHDL e n t i t y chain . is is a demodulator the carrier because for the i n phase branch o f is the
Since
frequency
1/4 t h e s a m p l i n g f r e q u e n c y ,
multiplierless
{ 1,
n = 0 ,4 ,8 ,... n = 1 ,3 ,5 ,...
c o s ( 2 p i /n ) = { 0 ,
64
I n t e r n a l D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : cnt Signals : This signal is used as a counter to count the # o f the demodulator decides clock cycles . outp rst h inp Ports clk : The c l o c k signal for the flip flops of t h i s module . These f l i p f l o p s filter Generics B : The # o f b i t s on t h e i n p u t and o u t p u t o f Since t h i s module this is the first t h e module . in the processing chain of the module .
thing
cascade ,
s h o u l d match t h e # o f
bits
t h a t t h e ADC o u t p u t s .
must o p e r a t e : The g l o b a l
high
: The i n p u t ADC.
signal
to the demodulator ,
this
: The o u t p u t filter .
signal
of
the demodulator ,
this
is
t h e i n p u t t o t h e CIC
Based on t h i s , ( n odd ) ,
or the input
( n= 2 , 6 , 1 0 , . . . ) .
m u l t i p l y by 1 i s
complement n e g a t i o n
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
demod i
generic port
( B : ( clk :
i n STD LOGIC ;
65
c n t 00 ; outp ( o t h e r s = > else case cnt is '0 ');
when 00 = > outp i n p ; when 01 | 11 = > outp ( o t h e r s = > when 10 = > outp ( n o t i n p ) + 1 ; when o t h e r s = > outp ( o t h e r s = > 'Z ' ) ; end c a s e ; cnt cnt + 1 ; end end if ; i n c r e m e n t c n t on p o s e d g e of clock '0 '); 2 ' s compliment n e g a t e t h e number
r s t h = ' 1 '
cic.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool Ports clk : The g l o b a l clock for the design . The d e s i g n p a r a m e t e r s a bove have t o D factor N : This of where N i s decimation this : is t h e number o f the stages in the filter , D factor is the Bacc = B c i c i n + c e i l (N l o g 2 ( D f a c t o r M) ) Generics B cic in B cic out : # of : # of b i t s on t h e i n p u t of the of cic cic . This is also t h e number o f o f both t h e following integrator versions : T h i s VHDL e n t i t y uses a clock is the top level of t h e CIC d e s i g n enabled uses is hierarchy . rather adder / s u b t r a c t o r s differential filter . D e s c r i p t i o n : cic struc 07:36:20 08/03/2007
This d e s i g n
enable
registers generic
than an i n t e r n a l l y
divided
clock .
design
and p o r t s
the
the accumulator is
registers
This value
d e t e r m i n e d by t h e
r a t e , and M i s
differential
delay ( f i x e d
at 2 f o r
This
t h e number o f
i n both t h e
t h e CIC f i l t e r . .
66
D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : tmpce : Internal Signals : Output o f the integrator cascade , i n p u t t o downsample module . these are output at the rst h of cic in be s u c h t h a t t h e : A global d e s i g n can run a t 100 MHz o r more ( 1 0 n s c l k asserted high reset . This goes to all period ) flip flops
synchronous ,
t h e CIC f i l t e r . : The s a m p l e s for t h e CIC t o process . These a r e input at the high sample
rate . ce out : This is a clock This enable signal signal is that is used to drive clock enabled registers this
after
t h e CIC .
g e n e r a t e d by t h e downsample module i n
design . cic out : The o u t p u t there is of t h e CIC f i l t e r . ( of These a r e o u t p u t a t t h e clock c y c l e s ) that is d i v i d e d sample r a t e . e q u a l t o t h e number of t h e CIC i s pipelined .
Also , of
a latency This is
divided fact
s t a g e s N.
due t o t h e
t h a t t h e comb s e c t i o n
downsample out
: Output o f
d i v i d e d sample r a t e .
C l o c k e n a b l e o u t p u t from downsample b l o c k . Used t o in t h e comb c a s c a d e and any o t h e r of t h e CIC . This is flip also flops the that
at the the
downsampled r a t e CIC f i l t e r .
ce out
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
cic
is ( B cic in : : : i n t e g e r := 1 2 ;
generic
i n t e g e r := 5 2 ; i n t e g e r := 1 2 5 ;
i n STD LOGIC ; i n STD LOGIC VECTOR ( B c i c i n 1 downto 0 ) ; o u t STD LOGIC ; o u t STD LOGIC VECTOR ( B c i c o u t 1 downto 0));
architecture
struc
of
cic
is
67
B int out N : port ( : integer ;
rst h
i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B i n t i n 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B i n t o u t 1 downto 0));
end component i n t c a s c a d e ;
D factor N : port (
integer ;
rst h
i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B downsample 1 downto 0 ) ; o u t STD LOGIC ; : o u t STD LOGIC VECTOR ( B downsample 1 downto 0));
data in clk en
data out
component c o m b c a s c a d e generic ( B comb cascade integer ); clk : i n STD LOGIC ; : i n STD LOGIC ; : integer ;
N : port (
rst h ce :
i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B c o m b c a s c a d e 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B c o m b c a s c a d e 1 downto 0));
end component c o m b c a s c a d e ;
i n t e r n a l signal signal
downsample out
o f downsample b l o c k
begin
struc
of
cic
i n s t a n t i a t e integrators :
stages
B int out = > B cic out , N = > N) casc in = > cic in , casc out = > int casc out );
downsample b l o c k
> B cic out , g e n e r i c map ( B downsample = p o r t map ( c l k = > clk , > rst h , rst h = > downsample out ) ; data out = i n s t a n t i a t e comb s t a g e s combs : comb cascade
> B cic out , N = > N) g e n e r i c map ( B c o m b c a s c a d e = p o r t map ( c l k = > clk , > rst h , rst h = ce = > tmpce , casc in = > downsample out , > cic out ); casc out = a s s i g n
the
clock
internal
s i g n a l tmpce
c e o u t tmpce ;
68
end s t r u c ;
declaration of cic
for is
cic
entity
cic con
for
integrators
int cascade
use
c o n f i g u r a t i o n work . i n t c a s c a d e c o n ;
end f o r ;
for
decimator
: downsample
use
end f o r ;
f o r combs : use
comb cascade
c o n f i g u r a t i o n work . c o m b c a s c a d e c o n ;
end f o r ;
quantizer.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool Internal Signals signals in this entity . Ports inp outp : The f u l l precision input . of the input signal . B out Generics B in : The b i t FIR width o f the input , either t h e CIC o u t p u t o r t h e p o l y p h a s e versions : T h i s VHDL e n t i t y o u t p u t and t h e is used to precision is q u a n t i z e both t h e p o l y p h a s e FIR full p r e c i s i o n CIC o u t p u t . The of the D e s c r i p t i o n : filter q u a n t i z e r behv 10:38:16 08/20/2007
full
filter
signals
filter
: The b i t
width o f
: The q u a n t i z e d
representation
There a r e no i n t e r n a l
69
D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments :
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
quantizer
is : i n t e g e r := 5 2 ; : i n t e g e r := 2 6 ) ;
generic
( B in
a r c h i t e c t u r e behv o f begin
quantizer
is
t r u n c a t e
the i n p u t to B out b i t s ,
taking
t h e MSB' s
outp i n p ( B i n 1 downto ( B i n B o u t ) ) ;
end behv ;
poly r top.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool versions : T h i s VHDL e n t i t y t h a t was d e s i g n e d is for a structural this description This of t h e p o l y p h a s e FIR consists of several D e s c r i p t i o n : filter poly fir top struc 14:29:56 08/08/2007
project .
entity
control
t h e t a p ROM a d d r e s s e s , after
one t o of
the
processing
g e n e r a t e an e n a b l e includes the
signal
for
enable
a c t u a l FIR
filter
structure of
filtering
and d e c i m a t i o n . Below a r e
descriptions
70
D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : addr Internal tmp ce Signals : The c l o c k enable signal used to filter drive output flip flops This t h a t need t o is also ce out Ports clk : The g l o b a l clock signal . asserted used for high logic reset signal . operate at B rom addr = c e i l ( l o g 2 ( D f i r ) ) D cic D fir B coeffs B input B output Generics N taps : The Number o f taps in t h e FIR in filter . the p r e c e d i n g CIC f i l t e r . inherent in the This is and i n t e r n a l signals that this entity uses .
N cic stages
: The Number o f
latency
pipelined
width o f width o f
: The f u l l
precision
filter . : The d e c i m a t i o n : The d e c i m a t i o n factor factor of of t h e CIC f i l t e r . t h e p o l y p h a s e FIR required generic for the filter . of t h e t a p ROMs . elements
B rom addr
: The number o f is
bits
address since
This
d e p e n d e n t on t h e
D fir ,
the # of
i n e a c h t a p rom i s c a l c u l a t e d by t h e
equal to following
D f i r . Thus t h i s equation :
g e n e r i c can be
rst h ce in
: The g l o b a l , : The c l o c k
synchronous , signal
enable rate .
that needs to
t h e CIC o u t p u t insample
: The i n p u t s a m p l e s , rate .
they are
i n p u t t o t h e p o l y p h a s e FIR
filter
at
t h e CIC o u t p u t : The c l o c k
enable
signal
used
for
logic
that needs to
operate
at the
polyphase outsample
filter
output of
: The o u t p u t
a l s o , any l o g i c be d r i v e n by t h e
that
follows
this
output needs to
clock
signal
ce out .
rate .
ce out
: The e n a b l e clock
signal
used to This
counting of
signals . of
needed to account
latency
t h e comb c a s c a d e signal
that
used to
a d d r e s s data i n
t h e t a p ROMs o f
71
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
is : i n t e g e r := 3 0 ; : i n t e g e r := 5 ;
generic
i n t e g e r := 1 4 ; i n t e g e r := 2 6 ; i n t e g e r := 4 8 ;
i n t e g e r := 1 0 ; i n t e g e r := 8 ; : i n t e g e r := 3 ) ;
i n STD LOGIC ; : : i n STD LOGIC ; i n STD LOGIC ; : i n STD LOGIC VECTOR ( B i n p u t 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B o u t p u t 1 downto
rst h ce in
insample ce out :
architecture
struc
of
is
component generic
i n STD LOGIC ; : i n STD LOGIC ; : : : i n STD LOGIC ; i n STD LOGIC ; i n STD LOGIC VECTOR ( B i n p u t 1 downto 0 ) ; : : i n STD LOGIC VECTOR ( B rom addr 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B o u t p u t 1 downto 0));
rst h
rst h
72
en in ce in : : i n STD LOGIC ; i n STD LOGIC ; : o u t STD LOGIC VECTOR ( B addr 1 downto 0));
tmp ce addr
tmp en
begin
ctrl0
en ctrl N cic stages = > N cic stages ) > rst h , rst h = ce in = > ce in , en out = > tmp en ) ;
g e n e r i c map ( p o r t map (
ctrl1
ce ctrl > D cic , D cic = D fir = > D fir ) en in = > tmp en , ce out = > tmp ce ) ;
g e n e r i c map ( p o r t map (
ctrl2
addr ctrl
> B rom addr ) g e n e r i c map ( B addr = p o r t map ( clk = > clk , > tmp en , en in = ce in = > ce in , rst h = > rst h , addr out = > addr ) ;
fir
fir taps D factor = > D fir , B coeffs = > B coeffs , B rom addr = > B rom addr ) ce slow = > tmp ce ,
ce fast = > ce in ,
end s t r u c ;
of
is
for
ce ctrl
use
e n t i t y work . c e c t r l ( behv ) ;
end f o r ;
for
ctrl2
addr ctrl
use
e n t i t y work . a d d r c t r l ( behv ) ;
end f o r ;
for
fir
fir taps
use
c o n f i g u r a t i o n work . f i r t a p s c o n ;
end f o r ;
73
end f o r ; end c o n f i g u r a t i o n poly fir top con ;
C.3
int cascade.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n 0.01 File Created Internal Signals : This is an a r r a y of standard bit logic vectors that are equal is in rst h Ports clk : Global clock for e n t i r e CIC , the registers in the integrator stages operate B int out N : # of Generics B int in : # of b i t s on t h e i n p u t t o t h e number o f : # of integrator cascade , this is the versions : T h i s VHDL e n t i t y of is a structural This entity description resides sign in of the integrator level of the D e s c r i p t i o n : cascade int cascade struc 11:36:29 07/30/2007
the second
hierarchy
This cascade
t o t h e number o f
a description
b i t s on t h e i n p u t t o t h e of the
filter
cascade .
b i t s on t h e o u t p u t stages
integrator
cascade .
integrator
to cascade
together .
registers
b e c a u s e t h e y need t o
asserted
reset
signal .
integrator
cascade . cascade .
the
integrator
intrn sig
length
to the accumulator
the array
extended to the
accumulator
width .
74
A d d i t i o n a l Comments : l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ;
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
int cascade (
generic
i n t e g e r := 5 ) ; : i n STD LOGIC ; : i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B i n t i n 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B i n t o u t 1 downto 0));
port
clk
rst h
architecture
struc
of
int cascade
is
i n STD LOGIC ; : : : i n STD LOGIC ; i n STD LOGIC VECTOR ( B i n t 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B i n t 1 downto 0));
rst h int in
int out
end component i n t e g r a t o r ;
i n STD LOGIC VECTOR ( Bin 1 downto 0 ) ; : o u t STD LOGIC VECTOR ( Bout 1 downto 0));
output
end component s i g n e x t e n d ;
i n t e r n a l subtype type
signals i s STD LOGIC VECTOR( B i n t o u t 1 downto 0 ) ; array (0 to N 2) : : intrn arr ; intrn bus ; of intrn bus ;
intrn bus is
intrn arr
signal signal
begin
a r c h .
struc
of
u s e t h e i f casc gen :
g e n e r a t e form o f
f o r J in 0 to N 1 generate
: :
if
signextend
> B int out ) g e n e r i c map ( Bin = > B i n t i n , Bout = p o r t map ( i n p u t = > casc in , output = > sgn ext in );
75
integrator1
integrator
to
o p e r a t e on s i g n
extended input
g e n e r i c map ( B i n t = > B int out ) p o r t map ( c l k = > clk , end g e n e r a t e first int ; int in = > sgn ext in , int out = > intrn sig (J ));
mid ints
if :
ints mid
> B int out ) g e n e r i c map ( B i n t = p o r t map ( c l k = > clk , end g e n e r a t e mid ints ; rst h = > rst h , int in = > i n t r n s i g (J 1) , int out = > intrn sig (J ));
last int
if :
int last
> B int out ) g e n e r i c map ( B i n t = p o r t map ( c l k = > clk , end g e n e r a t e last int ; > rst h , rst h = int in = > i n t r n s i g (J 1) , int out = > casc out );
end g e n e r a t e end s t r u c ;
casc gen ;
declaration
for of
entity is
for
for
for
use
e n t i t y work . s i g n e x t e n d ( behv ) ;
end f o r ;
for
integrator1
integrator
use
c o n f i g u r a t i o n work . i n t e g r a t o r c o n ;
for
for
for
use
c o n f i g u r a t i o n work . i n t e g r a t o r c o n ;
for
for
for
use
c o n f i g u r a t i o n work . i n t e g r a t o r c o n ;
76 downsample.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool I n t e r n a l D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n 0.01 File Created A d d i t i o n a l Comments : Signals : Output o f counting start ctrl , cycles the of this the signal tells the clk ctrl module when t o clk en Ports clk : Global clock , : used to generate asserted integrator clock high enable reset signal b a s e d on D f a c t o r . Generics B downsample D factor N : # of : : # of b i t s on i n p u t and o u t p u t o f downsample b l o c k . is t o d e c i m a t e by . versions : T h i s VHDL e n t i t y is a structural description of t h e downsample b l o c k . The first controller integrator first sample D e s c r i p t i o n : downsample s t r u c 13:37:51 08/02/2007
consists used is
o f two c o n t r o l l e r s / c o u n t e r s . needed to grab the there are is multiple not the cycles correct
c a s c a d e upon a r e s e t .
Since
integrator
first
s i m p l y c o u n t s t h e number o f
equivalent signal
the incoming
c l o c k and t h e n o u t p u t s an in
enable is to
controller
the
clk ctrl
block .
D f a c t o r and o u t p u t s a c l o c k
registers
after
With t h e s e two c o n t r o l l e r s ,
d r i v e n by t h e the generics ,
a description
p o r t s , and i n t e r n a l
t h e downsample b l o c k .
F a c t o r t h a t downsample b l o c k in
stages
i n t e g r a t o r and comb c a s c a d e .
rst h
signal . every D f a c t o r t h s a m p l e is
data in
stages ,
only
at the incoming
clock
input sample .
fsm en
start tmp en
fast ,
global This is
: Output o f
clk ctrl
module .
downsample b l o c k .
77
l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ;
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
e n t i t y downsample generic
is : : i n t e g e r := 5 2 ; i n t e g e r := 1 2 5 ;
( B downsample D factor N :
i n t e g e r := 5 ) ;
port
clk
i n STD LOGIC ; : i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B downsample 1 downto 0 ) ; o u t STD LOGIC ; : o u t STD LOGIC VECTOR ( B downsample 1 downto 0));
rst h
data in clk en
architecture
struc
o f downsample
is
component d e c l a r a t i o n s component generic port clk ctrl ( D : ( clk integer ); : i n STD LOGIC ; : : : i n STD LOGIC ; i n STD LOGIC ; o u t STD LOGIC ) ;
clk ctrl ;
o u t STD LOGIC ) ;
start ctrl ;
i n STD LOGIC ; i n STD LOGIC VECTOR ( B c e r e g 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B c e r e g 1 downto 0));
i n t e r n a l signal signal
signals : STD LOGIC ; : STD LOGIC ; e n a b l e c l o c k signal for the clock enable s t a t e machine
fsm en tmp en
enable output
for
divided
clock
begin
78
counter to enable
clock
divider
state
machine
en = > fsm en ) ;
clock for
divider all
s t a t e machine . in
T h i s module o u t p u t s
registers
t h e comb c a s c a d e .
dsampler
clk ctrl
g e n e r i c map (D = > D factor ) p o r t map ( c l k = > clk , r e g i s t e r > rst h , rst h = en in = > fsm en , en out = > tmp en ) ;
the output
of
t h e downsample b l o c k w i t h a c l o c k s i g n a l by D f a c t o r
enabled
register ,
e f f e c t i v e l y outreg : ce reg
downsampling t h e
> B downsample ) g e n e r i c map ( B c e r e g = p o r t map ( c l k = > clk , a s s i g n rst h = > rst h , ce = > tmp en , inp = > data in , outp = > data out ) ;
output
clock
enable
signal
to
internal
signal
tmp en
c l k e n tmp en ;
end s t r u c ;
declaration
f o r downsample e n t i t y is
for
start cnt
start ctrl
use
e n t i t y work . s t a r t c t r l ( behv ) ;
end f o r ;
for
dsampler
clk ctrl
use
e n t i t y work . c l k c t r l ( behv ) ;
end f o r ;
for
outreg
ce reg
use
e n t i t y work . c e r e g ( behv ) ;
end f o r ;
comb cascade.vhd
79
P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal Signals : This this signal array is is an a r r a y of standard logic v e c t o r s . Each row rst h ce : Ports clk : Global of : this clock clock signal . The comb s t a g e s o n l y have t o operate at the rate Generics B comb cascade : # of b i t s on i n p u t and o u t p u t o f to cascade together . comb cascade block . versions : T h i s VHDL e n t i t y is a structural description uses of t h e comb c a s c a d e g e n e r e r a t e form o f together . the D e s c r i p t i o n : of
the i f
generate
o f comb s e c t i o n s
Note t h a t of 2.
t h e s e comb s t a g e s
differential
delay
descriptions
are used i n
entity .
N : # o f comb s t a g e s
I n p u t t o t h e comb c a s c a d e , : Output o f
t h e comb c a s c a d e ,
filter .
intrn sig of
u s e d a s an o u t p u t o f a comb e n t i t y .
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
comb cascade
is : i n t e g e r := 5 2 ;
generic
( B comb cascade N :
i n t e g e r := 5 ) ;
port
clk
rst h ce :
i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B c o m b c a s c a d e 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B c o m b c a s c a d e 1 downto 0));
80
architecture
struc
of
comb cascade
is
rst h ce :
i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B comb 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B comb 1 downto 0));
i n t e r n a l subtype type
signals i s STD LOGIC VECTOR( B c o m b c a s c a d e 1 downto 0 ) ; array (0 to N 2) : intrn arr ; of intrn bus ;
intrn bus is
intrn arr
signal
intrn sig
begin
a r c h .
struc
of
comb cascade
comb gen
f o r K in 0 to N 1 generate
cmb1 :
i f K = 0 generate : comb
first cmb
g e n e r i c map ( B comb = > B comb cascade ) p o r t map ( c l k = > clk , > rst h , rst h = ce = > ce , > casc in , comb in = end g e n e r a t e cmb1 ; comb out = > i n t r n s i g (K ) ) ;
mid cmbs :
cmb mids : comb > B comb cascade ) g e n e r i c map ( B comb = p o r t map ( c l k = > clk , > rst h , rst h = ce = > ce , > i n t r n s i g (K 1 ) , comb out = > i n t r n s i g (K ) ) ; comb in = end g e n e r a t e mid cmbs ;
last cmb
i f K = N 1 generate : comb
cmb last
> B comb cascade ) g e n e r i c map ( B comb = p o r t map ( c l k = > clk , rst h = > rst h , ce = > ce , > i n t r n s i g (K 1 ) , comb out = > casc out ); comb in = end g e n e r a t e last cmb ;
end s t r u c ;
declaration
for of
entity is
use
81
end f o r ; end f o r ; end f o r ;
f o r comb gen ( 1 t o N 1 ) f o r mid cmbs f o r cmb mids : comb use c o n f i g u r a t i o n work . comb con ;
for
use
r taps.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool Generics N taps : The number o f : The f a c t o r taps in t h e FIR filter . will decimate . versions : This entity is a structural description of a transposed filter , direct D e s c r i p t i o n : form FIR f i r t a p s struc 14:36:40 08/08/2007
i n s e r t e d and t h e o u t p u t o f
are accumulated
D factor
equivalent
filter
the prototype
f i l t e r . The r a t e . To s t o r e the
so the
outputs at a decimated
deals
filter to
values
files the
initialize
the
descriptions this
generics ,
p o r t s , and i n t e r n a l
used i n
entity .
D factor
a t which t h e
filter
82
D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal Signals : This signal the is an a r r a y for of standard logic of vectors ( SLVs ) t h a t fir in Ports clk : The g l o b a l clock signal . asserted that high reset flip signal operating B coeffs B input B output is : The b i t : The b i t : The b i t width o f width o f width o f the coefficients stored in t h e t a p ROMs . filter . filter . This
u s u a l l y made t o k e e p
multipliers the
This
bits
in
t h e t a p ROM a d d r e s s
inputs .
rst h
: The g l o b a l , : The c l o c k
ce fast
drives
flops
output
enable
signal filter
a t t h e p o l y p h a s e FIR
output
t h e p o l y p h a s e FIR
precision .
generate
loop as outputs
These a r e
multipliers
signal , : This
fir in . signal is of an a r r a y the tap o f SLVs t h a t multipliers . are used i n the generate
loop as outputs
These a r e t h e n
input to the accumulators . intrn accD sig for : This signal is of an a r r a y o f SLVs t h a t are used i n the generate
loop as outputs
These a r e t h e n i n p u t o u t p u t s from t h e
is
an a r r a y generate
of
the tap
registers
used i n
the
along with the accumulator outputs . is the an a r r a y generate o f SLVs u s e d a s o u t p u t s for loop . These a r e t h e n of the
signal
registers .
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
83
entity
fir taps
is : i n t e g e r := 3 0 ; : : : : i n t e g e r := 8 ; i n t e g e r := 1 4 ; i n t e g e r := 2 6 ; i n t e g e r := 4 0 ; : i n t e g e r := 3 ) ;
generic
( N taps
i n STD LOGIC ; : i n STD LOGIC ; : : : i n STD LOGIC ; i n STD LOGIC ; i n STD LOGIC VECTOR ( B i n p u t 1 downto 0 ) ; : : i n STD LOGIC VECTOR ( B rom addr 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B o u t p u t 1 downto 0));
rst h
architecture
struc
of
fir taps
is
rst h en :
i n STD LOGIC ; : i n STD LOGIC VECTOR ( B addr 1 downto 0 ) ; : o u t STD LOGIC VECTOR ( B d a t a 1 downto 0));
addr
i n STD LOGIC VECTOR ( B m u l t i n 1 1 downto 0 ) ; : : i n STD LOGIC VECTOR ( B m u l t i n 2 1 downto 0 ) ; o u t STD LOGIC VECTOR ( ( B m u l t i n 1 + B m u l t i n 2 ) 1 downto 0));
in2 prod
end component g e n m u l t ;
i n STD LOGIC ; : : : : i n STD LOGIC ; i n STD LOGIC ; i n STD LOGIC VECTOR ( B a c c i n 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B a c c o u t 1 downto 0));
rst h ce in acc in
rst h
84
ce inp outp end component c e r e g ; : : : i n STD LOGIC ; i n STD LOGIC VECTOR ( B c e r e g 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B c e r e g 1 downto 0));
i n STD LOGIC VECTOR ( B a d d e r 1 downto 0 ) ; i n STD LOGIC VECTOR ( B a d d e r 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B a d d e r 1 downto 0));
add2 : sum :
end component g e n a d d e r ;
i n t e r n a l
signals i s STD LOGIC VECTOR ( B c o e f f s 1 downto 0 ) ; i s STD LOGIC VECTOR ( ( B c o e f f s + B i n p u t ) 1 downto 0 ) ; i s STD LOGIC VECTOR ( B o u t p u t 1 downto 0 ) ; array (0 to N taps 1) array (0 to N taps 1) array (0 to N taps 1) array (0 to N taps 2) array (1 to N taps 1)
type rom sig type type type type mult sig accD sig reg sig add sig
is is is is is
o f rom bus ; of of of of mult out ; accD out ; accD out ; accD out ;
intrn rom sig intrn mult sig intrn accD sig intrn reg sig intrn add sig
: : : : :
rom sig ; mult sig ; accD sig ; reg sig ; add sig ;
begin
a r c h .
struc
of
fir taps
f o r J in 0 to N taps 1 g e n e r a t e
if
J = 0 generate
coeffrom B data = > B coeffs , en = > ce fast , B addr = > B rom addr , addr = > rom addr ,
fname = > ( rom & i n t e g e r ' image ( N t a p s J 1 ) & . t x t ) ) p o r t map ( rst h = > rst h , > intrn rom sig (J )); rom out =
mult 0
accD 0
: accum D > D factor , D factor = B acc out = > B output ) B acc in = > ( B c o e f f s + B input ) , ce in = > ce fast , acc out = > intrn accD sig (J ));
g e n e r i c map (
p o r t map (
reg 0
g e n e r i c map ( p o r t map (
85
inp = > i n t r n a c c D s i g ( J ) , outp = > intrn reg sig (J )); end g e n e r a t e first tap ;
if
rom mid :
coeffrom B data = > B coeffs , en = > ce fast , B addr = > B rom addr , addr = > rom addr ,
fname = > ( rom & i n t e g e r ' image ( N t a p s J 1 ) & . t x t ) ) p o r t map ( > rst h , rst h = rom out = > intrn rom sig (J ));
mult mid
accD mid
: accum D D factor = > D factor , > B output ) B acc out = B acc in = > ( B c o e f f s + B input ) , ce in = > ce fast , acc out = > intrn accD sig (J ));
g e n e r i c map (
p o r t map (
add mid
gen adder
> B output ) g e n e r i c map ( B a d d e r = > i n t r n r e g s i g (J 1) , p o r t map ( add1 = > i n t r n a c c D s i g ( J ) , add2 = sum = > intrn add sig (J ));
reg mid
ce reg B ce reg = > B output ) > rst h , rst h = ce = > ce slow , inp = > intrn add sig (J) ,
g e n e r i c map ( p o r t map (
if
J = N taps 1 g e n e r a t e
rom last
coeffrom B data = > B coeffs , en = > ce fast , B addr = > B rom addr , addr = > rom addr ,
fname = > ( rom & i n t e g e r ' image ( N t a p s J 1 ) & . t x t ) ) p o r t map ( > rst h , rst h = > intrn rom sig (J )); rom out =
mult last
accD last
: accum D > D factor , D factor = > B output ) B acc out = B acc in = > ( B c o e f f s + B input ) , ce in = > ce fast , acc out = > intrn accD sig (J ));
g e n e r i c map (
p o r t map (
add last
gen adder
> B output ) g e n e r i c map ( B a d d e r = p o r t map ( add1 = > i n t r n a c c D s i g ( J ) , add2 = > i n t r n r e g s i g (J 1) , sum = > intrn add sig (J ));
86
reg last : ce reg > B output ) B ce reg = clk = > clk , rst h = > rst h , ce = > ce slow , inp = > intrn add sig (J) , outp = > fir out ); end g e n e r a t e last tap ;
end g e n e r a t e
tap gen ;
end s t r u c ;
of
fir taps
is
for
for
for
use
e n t i t y work . c o e f f r o m ( behv ) ;
end f o r ;
for
mult 0
gen mult
use
e n t i t y work . g e n m u l t ( behv ) ;
end f o r ;
for
accD 0
: accum D
use
end f o r ;
for
reg 0
ce reg
use
e n t i t y work . c e r e g ( behv ) ;
for
for
e n t i t y work . c o e f f r o m ( behv ) ;
end f o r ;
for
mult mid
gen mult
use
e n t i t y work . g e n m u l t ( behv ) ;
end f o r ;
for
accD mid
: accum D
use
end f o r ;
for
add mid
gen adder
use
e n t i t y work . g e n a d d e r ( behv ) ;
end f o r ;
for
reg mid
ce reg
use
e n t i t y work . c e r e g ( behv ) ;
end f o r ; end f o r ;
87
end f o r ;
for
for
for
use
e n t i t y work . c o e f f r o m ( behv ) ;
end f o r ;
for
mult last
gen mult
use
e n t i t y work . g e n m u l t ( behv ) ;
end f o r ;
for
accD last
: accum D
use
end f o r ;
for
add last
gen adder
use
e n t i t y work . g e n a d d e r ( behv ) ;
end f o r ;
for
reg last
ce reg
use
e n t i t y work . c e r e g ( behv ) ;
C.4
integrator.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool versions : T h i s VHDL e n t i t y of of is this a structural entity is description of a single is integrator D e s c r i p t i o n : integrator struc 11:11:48 07/30/2007
there
greatly
increases
Below a r e
of
the
generics ,
p o r t s , and i n t e r n a l
88
I n t e r n a l D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Signals : This is the output o f of the of the accumulator but it register . This signal Ports clk : Global : : clock signal . asserted stage . stage . high reset signal . Generics B int : # of b i t s on i n p u t and o u t p u t of integrator stage .
rst h int in
int out
: Output t o
integrator
reg out is
the output
also
f e e d s back i n t o
the output o f
the adder in
the
integrator .
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
integrator ( (
is : i n t e g e r := 5 2 ) ;
generic port
B int clk :
i n STD LOGIC ; : : : i n STD LOGIC ; i n STD LOGIC VECTOR ( B i n t 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B i n t 1 downto 0));
rst h int in
architecture
struc
of
integrator
is
component d e c l a r a t i o n s component g e n r e g generic port ( B : ( clk integer ); : i n STD LOGIC ; : i n STD LOGIC ;
end component g e n r e g ;
add2 :
89
sum : o u t STD LOGIC VECTOR ( B a d d e r 1 downto 0));
end component g e n a d d e r ;
i n t e r n a l signal signal
begin
a r c h .
struc
of
integrator
i n s t a n t i a t e adder :
gen adder
g e n e r i c map ( B a d d e r = > B int ) > r e g o u t , sum = > add out ) ; p o r t map ( add1 = > i n t i n , add2 = i n s t a n t i a t e acc reg :
accumulator
register
gen reg
g e n e r i c map (B = > B int ) p o r t map ( c l k = > clk , a s s i g n > rst h , rst h = inp = > add out , outp = > reg out ) ;
output o f
block to
internal
signal
reg out
end s t r u c ;
declaration
of of
integrator integrator
entity is
integrator con
for
gen adder
use
e n t i t y work . g e n a d d e r ( behv ) ;
end f o r ;
for
acc reg
gen reg
use
e n t i t y work . g e n r e g ( behv ) ;
comb.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool versions : T h i s VHDL e n t i t y of is a structural description entity is o f a s i n g l e comb s t a g e pipelined with output D e s c r i p t i o n : of comb s t r u c 16:13:49 08/02/2007
t h e comb c a s c a d e
t h e CIC f i l t e r .
This
90
D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : subout Internal Signals : This the This signal is the output is of the delayby2 shift register . This comb in comb out : Ports clk : Global : clock signal . asserted high reset signal . are of d r i v e n by t h i s the input rate . Generics B comb : # o f b i t s on i n p u t and o u t p u t o f comb s t a g e s . registers registers , has a f i x e d value that t o r e d u c e t h e c o m b i n a t i o n a l path o f there is o n l y one s u b t r a c t o r shift register of the cascade . With t h e nodes . pipeline T h i s comb s t a g e delay signals
i n between
registered fixed
differential
o f two .
descriptions
p o r t s , and i n t e r n a l
are used i n
entity .
rst h ce :
Clock e n a b l e
all
registers operate
i n comb c a s c a d e
b e c a u s e t h e y have t o I n p u t t o comb s t a g e .
o n l y a t 1/ D f a c t o r
: Output o f comb s t a g e .
delayout is :
signal is
that
the output
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
rst h ce :
i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B comb 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B comb 1 downto 0));
architecture
struc
o f comb i s
rst h
91
ce : i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B d e l a y b y 2 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B d e l a y b y 2 1 downto 0));
( sub1
i n STD LOGIC VECTOR ( B s u b t r a c t o r 1 downto 0 ) ; : : i n STD LOGIC VECTOR ( B s u b t r a c t o r 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B s u b t r a c t o r 1 downto 0));
sub2 diff
end component g e n s u b t r a c t o r ;
i n STD LOGIC ; i n STD LOGIC VECTOR ( B c e r e g 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B c e r e g 1 downto 0));
i n t e r n a l signal signal
delayout subout
subtractor
begin
a r c h .
struc
o f comb
i n s t a n t i a t e a b l o c k t o d e l a y delay : delayby2
input
s i g n a l by two s a m p l e s
> B comb ) g e n e r i c map ( B d e l a y b y 2 = p o r t map ( c l k = > clk , > rst h , rst h = ce = > ce , del in = > comb in , del out = > delayout ) ;
subtractor
gen subtractor
> B comb ) g e n e r i c map ( B s u b t r a c t o r = p o r t map ( sub1 = > comb in , r e g i s t e r outreg : sub2 = > delayout , diff = > subout ) ;
t h e o u t p u t t o r e d u c e t h e c o m b i n a t i o n a l path
ce reg
> B comb ) g e n e r i c map ( B c e r e g = p o r t map ( c l k = > clk , rst h = > rst h , ce = > ce , inp = > subout , outp = > comb out ) ;
end s t r u c ;
c o n f i g u r a t i o n
declaration
f o r comb e n t i t y
for
delay
delayby2
use
c o n f i g u r a t i o n work . d e l a y b y 2 c o n ;
end f o r ;
for
subtractor
gen subtractor
use
e n t i t y work . g e n s u b t r a c t o r ( behv ) ;
end f o r ;
92
for outreg : ce reg
use
e n t i t y work . c e r e g ( behv ) ;
end f o r ;
C.5
delayby2.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; 0.01 File Created A d d i t i o n a l Comments : Internal Signals : This signal is the output of the first register , input to the Ports clk : A global clock signal . asserted that is high reset . drive the registers . Generics B delayby2 : # of bits in each register of this entity . versions : This entity is is simply a cascade o f two c l o c k of enabled registers D e s c r i p t i o n : This delayby2 s t r u c 16:06:20 08/02/2007
entity
t o implement t h e Below a r e
delay
descriptions this
generics ,
p o r t s , and i n t e r n a l
signals
are used i n
entity .
rst h ce
: A global
syncronous , input
: The c l o c k
enable
used to
delayby1
second
register .
93
u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ;
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
delayby2
is : i n t e g e r := 5 2 ) ;
generic port
( B delayby2 ( clk :
rst h ce :
i n STD LOGIC ; : : i n STD LOGIC VECTOR ( B d e l a y b y 2 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B d e l a y b y 2 1 downto 0));
architecture
struc
of
delayby2
is
i n STD LOGIC ; i n STD LOGIC VECTOR ( B c e r e g 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B c e r e g 1 downto 0));
i n t e r n a l signal
delayby1
begin
c r e a t e a delayreg1 :
register ce reg
t o d e l a y s a m p l e by one c y c l e
> B delayby2 ) g e n e r i c map ( B c e r e g = p o r t map ( c l k = > clk , c a s c a d e a s e c o n d delayreg2 : ce reg > rst h , rst h = ce = > ce , inp = > del in , outp = > delayby1 ) ;
register
t o d e l a y s a m p l e by two c y c l e s
> B delayby2 ) g e n e r i c map ( B c e r e g = p o r t map ( c l k = > clk , > rst h , rst h = ce = > ce , inp = > delayby1 , outp = > del out );
end s t r u c ;
declaration of
for
delayby2 is
entity
delayby2 con
delayby2
for
ce reg
use
e n t i t y work . c e r e g ( behv ) ;
ce ctrl.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal count Signals : The c o u n t e r signal gets signal reset that is used to count the ce out global clock c y c l e s . When Ports clk : The g l o b a l clock signal asserted signal high reset signal e n t i t y when t o Generics D cic D fir : The d e c i m a t i o n : The d e c i m a t i o n factor factor of of t h e CIC f i l t e r . t h e p o l y p h a s e FIR filter . versions : T h i s VHDL e n t i t y flip uses flops is used to generate the clock enable filter signal output rate . D e s c r i p t i o n : that This c e c t r l behv 18:07:41 08/07/2007
operating
a t t h e p o l y p h a s e FIR factor
t h e combined d e c i m a t i o n of trying
global
instead
to count the of
clock
t h e CIC f i l t e r .
This
entity
h a s an of
pipelined
structure counting
does not
start
until
asserted .
rst h en in
that
tells
the
start ce out
clock enable
: The c l o c k
that
is
used to output
drive rate .
flip
flops
that
operate
a t t h e p o l y p h a s e FIR
filter
this
to zero ,
output
gets
asserted .
95
Uncomment t h e any X i l i n x l i b r a r y UNISIM ; u s e UNISIM . VComponents . a l l ; following in library this declaration if instantiating
primitives
code .
entity
ce ctrl (
is D cic : i n t e g e r := 1 0 ; : i n t e g e r := 8 ) ;
generic
ce ctrl
is factor
D factor signal :
cycles
integer
D factor ;
process ( clk )
c l k ' e v e n t and c l k = ' 1 ' t h e n do e v e r y t h i n g on p o s e d g e if r s t h = ' 1 ' then count 0 ; ce out '0 '; elsif if e n i n = ' 1 ' then s t a r t c o u n t i n g when e n i n k e e p c o u n t i n g c r e a t e a s y n c h r o n o u s reset
of
clock
gets
asserted
until assert
c o u n t = D f a c t o r 1 ce out
c o u n t = 0 t h e n when c o u n t wraps t o z e r o ,
c o u n t = D f a c t o r 1
ce out '0 '; count count + 1 ; end else count 0 ; ce out '0 '; end end end i f ; c o u n t ( D f a c t o r 1) e n i n = ' 1 ' if ; c o u n t = 0
if ;
addr ctrl.vhd
96
D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal count Signals : A counter signal t h a t d e c r e m e n t s when t h i s rate . This internal entity is is e n a b l e d and the ce in Ports clk : The g l o b a l clock signal . asserted high reset signal . Generics B addr : The number o f bits in the address of t h e t a p ROMs . versions : T h i s VHDL e n t i t y generates the the a d d r e s s used to entity . this fetch coefficient address D e s c r i p t i o n : a d d r c t r l behv
t h e t a p ROMs i n
fir taps
This g e n e r a t e d entity is is
gets
reset .
signal
signal . is
This
entity
t h e same r e a s o n in
enabled , entity is
to account also
latency
t h e CIC f i l t e r . to operate
This
d r i v e by a c l o c k rate .
enable
a t t h e CIC f i l t e r
output
rst h en in
: The g l o b a l , : An e n a b l e
synchronous , telling
signal
t h a t makes t h e c o u n t e r d e c r e m e n t a t t h e
output
: The g e n e r a t e d the
t a p ROMs i n
fir taps
entity .
output
signal
actually
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
addr ctrl
is : i n t e g e r := 3 ) ;
generic port
( B addr ( clk :
rst h en in
97
ce in : i n STD LOGIC ; : o u t STD LOGIC VECTOR ( B addr 1 downto 0));
a r c h i t e c t u r e behv o f
process ( clk )
c l k ' e v e n t and c l k = ' 1 ' t h e n do e v e r y t h i n g on p o s e d g e if r s t h = ' 1 ' then count ( o t h e r s = > elsif count count 1 ; end if ; e n i n = ' 1 ' and c e i n = ' 1 ' count to output a d d r o u t c o u n t ; a s s i g n make a s y n c h r o n o u s '1 '); s e t address reset t o max .
of
clock
d e c r e m e n t when e n i n and c e i n
end
en ctrl.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool Ports clk : The g l o b a l : A global , : The c l o c k clock signal . asserted high in reset signal . of the Generics N cic stage : The number o f stages in t h e CIC f i l t e r that precedes this versions : T h i s VHDL e n t i t y in are is used to account It for the latency of the clock enable and This D e s c r i p t i o n : e n c t r l behv 13:43:31 09/01/2007
t h e CIC f i l t e r .
s i m p l y c o u n t s t h e number o f in
g e n e r a t e d by t h e downsample e n t i t y signal
t h e CIC f i l t e r that
exist .
then used to
e n t i t y when t o of the
start
counting ports ,
global signals
generics ,
and i n t e r n a l
p o l y p h a s e FIR
filter .
rst h ce in
t h e downsample b l o c k
CIC f i l t e r . en out
This
what g e t s
: The e n a b l e o u t p u t t h a t
tells
ce ctrl
module when t o
start
98
D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal count Signals : This signal is is used to hold the count o f b a s e d on t h i s signal . the ce in i n p u t . The e n o u t counting global clock cycles .
output
asserted
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
en ctrl ( (
generic port
en ctrl
to count
integer
range 0 to
N cic stages ;
process ( clk )
c l k ' e v e n t and c l k = ' 1 ' t h e n do e v e r y t h i n g on a p o s e d g e if r s t h = ' 1 ' then count 0 ; r e s e t en out ' 0 '; elsif if make a s y n c h r o n o u s , the counter the ce ctrl ce in entity pulses asserted high
of
clk
reset
d i s a b l e
c o u n t
c o u n t
N c i c s t a g e s 1 p u l s e s
else
c o u n t i n g and a s s e r t
e n o u t when N c i c s t a g e s 1 p u l s e s
are counted
count count ; en out '1 ' ; end end end i f ; c o u n t ( N c i c s t a g e s 1) r s t h = ' 1 '
if ;
99 signextend.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal Signals signals . Ports input output : Non s i g n : e x t e n d e d v a l u e from ADC. Generics Bin : # of b i t s on t h e i n p u t port o f module . o f module . versions : T h i s VHDL e n t i t y of is a simple sign extender . bit It is used to the sign D e s c r i p t i o n : s i g n e x t e n d behv 10:16:16 07/30/2007
width o f
g e n e r a t e form o f p o r t s , and i n t e r n a l
Below a r e
descriptions
generics ,
signals
are used i n
t h i s module .
Bout : # o f
b i t s on t h e o u t p u t p o r t
S i g n e x t e n d e d v a l u e from ADC.
T h i s module h a s no i n t e r n a l
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
signextend ( Bin
is : i n t e g e r := 1 3 ; i n t e g e r := 5 2 ) ;
generic
i n STD LOGIC VECTOR ( Bin 1 downto 0 ) ; : o u t STD LOGIC VECTOR ( Bout 1 downto 0));
output end s i g n e x t e n d ;
100
a r c h i t e c t u r e behv o f begin o u t p u t ( Bin 1 downto 0 ) i n p u t ; sgn ext : for j i n Bin t o Bout 1 g e n e r a t e o u t p u t ( j ) i n p u t ( Bin 1 ) ; end g e n e r a t e end behv ; sgn ext ; signextend is
clk ctrl.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n 0.01 File Created A d d i t i o n a l Comments : Internal count Signals : This signal is u s e d t o c o u n t t h e number o f appropriate times . the global clock signal Ports clk : Global : : clock signal . asserted high reset signal . start counting cycles Generics D : The d e c i m a t i o n factor of t h e CIC f i l t e r . versions : T h i s VHDL e n t i t y enable is a leaf node o f t h e downsample b l o c k . global enabled clock This entity D e s c r i p t i o n : c l k c t r l behv 11:48:33 08/02/2007
signal is
b a s e d on t h e i n c o m i n g , drive clock
enable
signal
registers
processing
chain .
c y c l e s and o u t p u t s descriptions of
this the
Below a r e
generics ,
p o r t s , and i n t e r n a l
used i n
t h i s module .
rst h en in
Global ,
synchronous ,
signal
T h i s i n p u t comes from t h e
start ctrl
module i n en out :
t h i s downsample e n t i t y . signal in that the is used to drive chain . all clock enabled is a registers
Clock e n a b l e this
following registered
block
processing
This output
output .
and a s s e r t
the output at
101
l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ;
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
clk ctrl
is i n t e g e r := 1 2 5 ) ;
generic port (
( D : clk :
clk ctrl
integer
r a n g e 0 t o D;
c l k ' e v e n t and c l k = ' 1 ' t h e n c o u n t if r s t h = ' 1 ' then count 0 ; en out ' 0 '; elsif if e n i n = ' 1 ' then don ' t i f
positive
edges
of
input
clock
signal
g e n e r a t e a s y n c r o n o u s ,
asserted
high
reset
start
counting
u n l e s s FSM i s is
enabled
c o u n t (D 2 ) t h e n c o u n t up t o D 2 b e c a u s e o u t p u t if count = 0 then en out ' 1 ' ; count count + 1 ; else en out ' 0 ' ; count count + 1 ; end i f ; c o u n t = 0 r e s e t c o u n t e r when i t reaches D 1 i f counter is less c o u n t e r h a s wrapped t o z e r o ,
registered
than D 2 , k e e p c o u n t i n g
i f ; c o u n t (D 2 ) e n i n = ' 1 '
if ;
start ctrl.vhd
Company : E n g i n e e r :
102
C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n A d d i t i o n a l Comments : l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created waits until it . . . N3 R e v i s i o n 1 November 4 , 2007 changed how l o n g t h e c o u n t e r creates to the enable signal . I n o t h e r words , line . . . N 2. design . into Ports clk : A global clock signal . asserted block high reset signal . for clk ctrl to keep . Generics N : # of stages in integrator until the cascade . This is t h e number o f cycles of t h a t need the versions : T h i s VHDL e n t i t y signal for is a leaf node o f t h e downsample b l o c k . clk ctrl . Since point It This job there are the creates D e s c r i p t i o n : s t a r t c t r l behv 12:00:00 08/02/2007
an e n a b l e multiple
integrator is
good s a m p l e from t h e
o f view o f
first
sample input
after a reset .
clock
the
first
stages .
This block
t h a t t h e s a m p l e coming
generics ,
p o r t s , and i n t e r n a l
signals
t o be c o u n t e d
first
good s a m p l e a p p e a r s a t t h e i n p u t
downsample b l o c k .
rst h en
: A global
synchronous , this
telling
which s a m p l e
T h i s c h a n g e was n e c e s s a r y
because
to the
cycle
be t a k e n
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
generic port
103
start ctrl
integer
range 0 to N;
process ( clk )
c l k ' e v e n t and c l k = ' 1 ' t h e n c o u n t if r s t h = ' 1 ' then count 0 ; en ' 0 ' ; else if count N 2 then count count + 1 ; en ' 0 ' ; else en ' 1 ' ; end end i f ; c o u n t N 3 r s t h = ' 1 ' i f count
positive
edges high ,
of
incoming
clock reset
c r e a t e an a s s e r t e d
synchronous
i s N 2 , keep c o u n t i n g
a s s o o n a s c o u n t r e a c h e s N 1 , s t o p
c o u n t i n g and a s s e r t en
if ;
end
end p r o c e s s
end behv ;
ce reg.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool inp outp Ports clk : A global clock signal . asserted This high is reset signal . Generics B ce reg : # of bits in the register . versions : T h i s VHDL e n t i t y is a general This b i t width , is used of for the positive all edge triggered , after the used i n D e s c r i p t i o n : clock c e r e g behv 11:42:25 08/02/2007
enabled D t y p e
register .
registers
Below a r e
descriptions
p o r t s and g e n e r i c s
rst h ce
: A global
synchronous , signal .
: A clock
enable
signal
d r i v e any this of
register
that needs to
register . register .
this
104
D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC SIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments :
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
ce reg ( (
is B ce reg clk : : i n t e g e r := 5 2 ) ;
generic port
i n STD LOGIC ; i n STD LOGIC VECTOR ( B c e r e g 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B c e r e g 1 downto 0));
ce reg
is
( clk )
c l k ' e v e n t and c l k = ' 1 ' t h e n c r e a t e a p o s i t i v e if r s t h = ' 1 ' then outp ( o t h e r s = > elsif ce = ' 1 ' then r s t h = ' 1 ' outp i n p ; end if ; i f ; c l k ' e v e n t and c l k = ' 1 ' en reg ; '0 '); c r e a t e a c l o c k
edge
triggered asserted
c r e a t e a s y n c h r o n o u s ,
high
enabled
register
end
coerom.vhd
105
T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal rom : Signals This that is a constant the signal that of is an ( N e l e m s ) by ( B d a t a ) filter . arra addr rom out Ports clk : The g l o b a l clock signal . asserted high reset signal . filter Generics N elems B data B addr : The number o f : The b i t : The b i t file elements in t h e ROM. stored in t h e ROM. versions : T h i s VHDL e n t i t y of a to file . in This is a ROM module t h a t is initialized with the D e s c r i p t i o n : contents
file
initialized
bit
vector
MATLAB s c r i p t
descriptions
p o r t s , and i n t e r n a l
signals
entity .
fname : The
be i n
t h e same d i r e c t o r y
as the
rst h en
: The g l o b a l
synchronous , that is
: The e n a b l e output
signal
u s e d t o o u t p u t new d a t a a t t h e CIC
rate . i n p u t t o t h e ROM.
: The a d d r e s s
stores
coefficients
the
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
coeffrom
is : i n t e g e r := 8 ; : : i n t e g e r := 1 4 ; i n t e g e r := 3 ; s t r i n g := rom0 . t x t ) ;
generic
( N elems
rst h en :
i n STD LOGIC ;
106
addr : i n STD LOGIC VECTOR ( B addr 1 downto 0 ) ; : o u t STD LOGIC VECTOR ( B d a t a 1 downto 0));
a r c h i t e c t u r e behv o f
coeffrom
array (0 to N elems 1)
( B d a t a 1 downto 0 ) ;
t o l o a d t h e ram w i t h a : in is string )
load rom ( l o a d f i l e :
load file ;
variable
line in
d e c l a r e a l i n e
r e a d i n g from
d e c l a r e a rom a r r a y t o
initialize
and t h e n r e t u r n
rom e l e m e n t t o v a l u e from
initialize
it
with c o n t e n t s
of
file
fname
process ( clk )
c l k ' e v e n t and c l k = ' 1 ' t h e n r e a d on a p o s e d g e if r s t h = ' 1 ' then en = ' 1 ' t h e n o u t p u t last value r o m o u t t o s t d l o g i c v e c t o r ( rom ( N e l e m s 1 ) ) ; elsif o u t p u t d a t a a c c o r d i n g
of
clock
o f ROM on a r e s e t
t o addr when en
is
asserted
r o m o u t t o s t d l o g i c v e c t o r ( rom ( c o n v i n t e g e r ( addr ) ) ) ; end end if ; r s t h = ' 1 ' i f ; c l k ' e v e n t and c l k = ' 1 ' read rom ;
gen mult.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool Generics versions : T h i s VHDL e n t i t y descriptions of is a generic , generics , signed , full precision multiplier . of this D e s c r i p t i o n : g e n m u l t behv 17:01:47 08/07/2007
Below a r e entity .
the
p o r t s , and i n t e r n a l
signals
107
D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC SIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal Signals signals in this entity . Ports in1 in2 prod : The first input to the multiplier . multiplier . the multiplier . B mult in1 : The b i t this width o f is the first input to the multiplier . filter . In this In this
: The b i t this
width o f is
multiplier .
design ,
the output
s i g n e d output o f
There a r e no i n t e r n a l
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
gen mult
is : i n t e g e r := 1 4 ; : i n t e g e r := 1 6 ) ;
generic
( B mult in1
i n STD LOGIC VECTOR ( B m u l t i n 1 1 downto 0 ) ; i n STD LOGIC VECTOR ( B m u l t i n 2 1 downto 0 ) ; o u t STD LOGIC VECTOR ( ( B m u l t i n 1 + B m u l t i n 2 ) 1 downto 0));
gen mult
is
( in1 ,
in2 )
accum D.vhd
Company : E n g i n e e r :
108
C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; 0.01 File Created A d d i t i o n a l Comments : count tmp : This of Internal Signals : This signal is used to keep the v a l u e of the accumulated Ports clk : The g l o b a l clock signal . asserted used to of high reset signal . Generics D factor : The d e c i m a t i o n factor of t h e p o l y p h a s e FIR filter . This is versions : T h i s VHDL e n t i t y This entity uses accumulates the input signed it arithmetic signal for D factor this entity has D e s c r i p t i o n : cycles . a clock rate , accum D behv 14:48:26 08/07/2007
t o do t h i s .
Also ,
enable
signal global
because clock
output
not the
rate .
the
in
o t h e r words ,
there
several of
guard the
bits
descriptions entity .
generics ,
signals
cycles
t h a t t h e i n p u t n e e d s t o be a c c u m u l a t e d . the input to the accumulator . the output o f the accumulator . This there is usually This is also
width o f width o f
the
width o f
larger
than
t h e i n p u t by s e v e r a l in
a r e some g u a r d
bits
overflow .
rst h ce in
: The g l o b a l , : The c l o c k
synchronous , signal
enable
output
rate
instead
the In
design ,
: The o u t p u t filter
This
is
FIR
output
accumulator
input . signal is a temporary register that is used to hold the value is necessary because
overflows .
This cycle
without
o c c u r s on t h e This
overflows of
register
the input is
cycle
overflows . cycle .
signal
o f how many
cycles
t h e i n p u t h a s been a c c u m u l a t e d .
109
u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC SIGNED . ALL ;
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
i n STD LOGIC ; : : : : i n STD LOGIC ; i n STD LOGIC ; i n STD LOGIC VECTOR ( B a c c i n 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B a c c o u t 1 downto 0));
rst h ce in acc in
function
( num short
r e t u r n STD LOGIC VECTOR i s v a r i a b l e tmp num : STD LOGIC VECTOR ( B a c c o u t 1 downto 0 ) ; begin tmp num ( B a c c i n 1 downto 0 ) := n u m s h o r t ; sign ext : for i in B acc in to B acc out 1 loop tmp num ( i ) := n u m s h o r t ( B a c c i n 1 ) ; end l o o p sign ext ;
r e t u r n tmp num ; end f u n c t i o n i n t e r n a l signal signextend ; signals : STD LOGIC VECTOR ( B a c c o u t 1 downto 0 ) ;
accumulator
s i g n a l tmp : STD LOGIC VECTOR ( B a c c i n 1 downto 0 ) ; signal begin accum : begin if c l k ' e v e n t and c l k = ' 1 ' t h e n do e v e r y t h i n g on p o s e d g e if r s t h = ' 1 ' then count 0 ; > acc out ( others = tmp ( o t h e r s = > elsif if c e i n = ' 1 ' then '0 '); c o u n t when c e i n c o u n t for i n c r e m e n t '0 '); is asserted D f a c t o r 2 c y c l e s c r e a t e a s y n c h r o n o u s , '0 '); asserted accumulator ( others = > of clock reset process ( clk ) count : integer range 0 to D factor ;
high
c o u n t = 0 t h e n when c o u n t e r
a c c u m u l a t o r s i g n e d ( s i g n e x t e n d ( tmp ) ) + s i g n e d ( s i g n e x t e n d ( a c c i n ) ) ; else when c o u n t e r hasn ' t o v e r f l o w e d , add t h e i n p u t t o t h e a c c u m u l a t o r c o u n t = 0 c o u n t e r when c o u n t = D f a c t o r 1 and o u t p u t a c c u m u l a t o r accumulator signed ( accumulator ) + signed ( signextend ( a c c i n ) ) ; end else if ; r e s e t
110
count 0 ; acc out accumulator ; accumulator ( others = > tmp a c c i n ; end end end i f ; c o u n t ( D f a c t o r 2) r s t h = ' 1 ' '0 ');
if ;
gen adder.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; 0.01 File Created A d d i t i o n a l Comments : Internal Signals signals . Ports add1 : The first i n p u t t o be added t o g e t h e r . Generics B adder : # of b i t s on i n p u t and o u t p u t o f generic adder . versions : T h i s VHDL e n t i t y node o f the is a generic entity . s i g n e d adder . This adder stages . It is is For This is the this D e s c r i p t i o n : a leaf g e n a d d e r behv 13:20:48 08/06/2007
integrator of the
used i n
accumulators
integrator in or is of
assumed
width
include
descriptions entity .
generics ,
p o r t s , and i n t e r n a l
T h i s module h a s no i n t e r n a l
111
u s e IEEE . STD LOGIC SIGNED . ALL ;
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
gen adder
is : i n t e g e r := 5 2 ) ;
generic port
( B adder ( add1 :
i n STD LOGIC VECTOR ( B a d d e r 1 downto 0 ) ; i n STD LOGIC VECTOR ( B a d d e r 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B a d d e r 1 downto 0));
a r c h i t e c t u r e behv o f begin
gen adder
is
add : begin
p r o c e s s ( add1 , add2 )
end behv ;
gen subtractor.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool D e p e n d e n c i e s : Ports sub1 sub2 diff : Number t h a t sub2 g e t s : Number t h a t is s u b t r a c t e d from . Generics B subtractor : # of b i t s on i n p u t s and o u t p u t o f module versions : T h i s VHDL e n t i t y a in leaf the node i n fourth is a generic B subtractor bit of in signed subtractor . entity D e s c r i p t i o n : This is g e n s u b t r a c t o r behv 13:23:00 08/06/2007
This
resides
create
Below a r e
descriptions
t h i s module .
: The d i f f e r e n c e
112
R e v i s i o n : R e v i s i o n l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created A d d i t i o n a l Comments :
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
gen subtractor (
is : i n t e g e r := 5 2 ) ;
generic port
i n STD LOGIC VECTOR ( B s u b t r a c t o r 1 downto 0 ) ; i n STD LOGIC VECTOR ( B s u b t r a c t o r 1 downto 0 ) ; o u t STD LOGIC VECTOR ( B s u b t r a c t o r 1 downto 0));
end g e n s u b t r a c t o r ;
a r c h i t e c t u r e behv o f begin
gen subtractor
is
sub
p r o c e s s ( sub1 ,
sub2 )
end behv ;
gen reg.vhd
Company : E n g i n e e r : C r e a t e Date : D e s i g n Name : Module Name : P r o j e c t Name : T a r g e t D e v i c e s : Tool Generics versions : T h i s VHDL e n t i t y asserted in the high is a B b i t positive This edge is triggered for register w i t h an D e s c r i p t i o n : g e n r e g behv 17:44:10 07/03/2007
reset
signal . of
used
integrator
cascade
t h e CIC f i l t e r . that
generics ,
p o r t s , and i n t e r n a l
signals
are used i n
113
I n t e r n a l D e p e n d e n c i e s : R e v i s i o n : R e v i s i o n A d d i t i o n a l Comments : l i b r a r y IEEE ; u s e IEEE . STD LOGIC 1164 . ALL ; u s e IEEE . STD LOGIC ARITH . ALL ; u s e IEEE . STD LOGIC UNSIGNED . ALL ; 0.01 File Created reset to synchronous reset , still 0 . 0 2 changed from a s y n c h r o n o u s asserted high . Signals signals in this entity . Ports clk : A global clock . synchronous , register . register . asserted high reset signal B : # of bits in register .
the
There a r e no i n t e r n a l
following in
library this
declaration
if
instantiating
primitives
code .
u s e UNISIM . VComponents . a l l ;
entity
gen reg
generic port
( B : (
gen reg
is
process ( clk )
begin if c l k ' e v e n t and c l k = ' 1 ' t h e n c r e a t e a p o s i t i v e if r s t h = ' 1 ' then outp ( o t h e r s = > else outp i n p ; end end i f ; r s t h = ' 1 ' i f ; c l k ' e v e n t and c l k = ' 1 ' reg ; copy i n p u t t o o u t p u t on a p o s i t i v e edge '0 '); edge triggered register high reset
c r e a t e a s y n c h r o n o u s ,
asserted