Journal of Mechanics Engineering and Automation 3 (2013) 731-738

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A New Approach to Cleave MEMS Devices from Silicon Substrates

Mehdi Rezaei, Jonathan Lueke, Dan Sameoto, Don Raboud and Walied Moussa
Mechanical Engineering Department, University of Alberta, Edmonton T6G 2G8, Canada

Received: August 16, 2013 / Accepted: September 13, 2013 / Published: December 25, 2013. Abstract: Dicing of fabricated MEMS (microelectromechanical system) devices is sometimes a source of challenge, especially when devices are overhanging structures. In this work, a modified cleaving technique is developed to precisely separate fabricated devices from a silicon substrate without requiring a dicing machine. This technique is based on DRIE (deep reactive ion etching) which is regularly used to make cleaving trenches in the substrate during the releasing stage. Other similar techniques require some extra later steps or in some cases a long HF soak. To mask the etching process, a thick photoresist is used. It is shown that by applying different UV (ultraviolate) exposure and developing times for the photoresist, the DRIE process could be controlled to etch specific cleaving trenches with less depth than other patterns on the photoresist. Those cleaving trenches are used to cleave the wafer later, while the whole wafer remains as one piece until the end of the silicon etching despite some features being etched all the way through the wafer at the same time. The other steps of fabricating and releasing the devices are unaffected. The process flow is described in details and some results of applying this technique for cleaving fabricated cantilevers on a silicon substrate are presented. Key words: Dicing, cleaving, microfabrication, dry release, exposure characterization, deep reactive ion etching.

1. Introduction
The packaging of MEMS devices seems to be equally or even more challenging than the fabrication such that it could dramatically decrease the yield of the MEMS devices [1-3]. The typical first step in packaging is to separate individual devices from the substrate. Usually dicing is used for this purpose, however, in the case of fragile and overhanging structures, a dicing machine could easily damage or break the devices [4]. Some techniques such as wafer bonding [5] and stacking devices [6] have been used to overcome this problem but dicing continues to be a challenge. Although improvement of dicing reliability has been reported [7, 8], researchers are still searching for dicing-free methods [9, 10] to alleviate this issue. Laser-based dicing and scribing [11, 12] is an
Corresponding author: Walied Moussa, Ph.D., professor, research fields: development of MEMS and NEMS in the biomedical, aerospace, mechanical and environmental fields. E-mail: walied.moussa@ualberta.ca.

alternative, however, it adds more fabrication steps and increase the fabrication cost. In some cases, a diamond scriber [13-15] was used to cleave individual devices, however, it is not sufficiently accurate to separate dense devices. Alternatively, DRIE (deep reactive ion etching) which is one of the main etching techniques for releasing MEMS structures [16], has widely been used to enhance the cleaving process [17, 18]. As etching too deep causes breaking the wafer, usually wafers are mounted on a carrier wafer [19, 20]. This mounting causes other challenges such as damaging fragile devices while removing them from the adhesive [6-21]. In some cases, DRIE has been used on SOI (silicon on insulator) to eliminate the supporting wafers [22, 23]. Apart from SOI wafers cost, this technique works well only for limited types of materials. The long HF immersion which is required for final separation, in this approach, could result in damaging or delaminating some previously fabricated layers. In addition, a

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A New Approach to Cleave MEMS Devices from Silicon Substrates

one-step DRIE process was used to cleave individual devices considering different aspect ratios in front side silicon etching [24]. It uses different etch areas to achieve a through-hole and partial thickness cracks. As novel as this approach is, it appears to be too specific to be used for general MEMS devices. To deal with the issues that arise with the reported methods, the DRIE-based cleaving technique is modified in this article for separating general MEMS devices in an accurate one-step etch process. The paper is organized as follows: Section 2 presents the new cleaving technique; Section 3 introduces the fabrication process flow in details; Section 4 and 5 provide the results and discussions; Section 6 gives conclusions.

Proof Mass

Cleaving Trenches

Front side patterns boundary

Gap for releasing

Backside of the wafer

(a)

2. Modified Cleaving Technique

The modified cleaving technique is based on a single differential depth DRIE using a soft photoresist mask. This technique can be used with any silicon wafer type including single-side-polished wafers. The technique is based on an atypical method of PR (photoresist) patterning [25]. The PR layer is exposed in two steps, both with separate masks and exposure times. This achieves two different depths of developed PR. The PR which is used to mask the etching process, would be etched under the DRIE process at a slower etch-rate depending on the etch selectivity. Typically, the removal of masking PR is an unwanted byproduct of the DRIE process. In this case, this phenomenon is used to produce secondary etch windows to obtain two separate etch depths in a single etch step. A schematic of the wafers backside is shown in Fig. 1a. The dashed lines represent the main devices (SU-8 cantilevers in this case) on the front side of the wafer. Several widths of cleaving trenches have been examined that would help determine the optimal features and depth that could result in appropriate cleaving without requiring excessive wafer area. Fig. 1b is an image of a completely fabricated wafer just before cleaving.
(b) Fig. 1 (a) Schematic of the cleaving technique; (b) A full wafer with released devices just before cleaving.

3. Process Flow
The process begins with a single-side-polished silicon wafer with fabricated devices (SU-8 cantilevers in this case) on the front side of the wafer (Fig. 2a). Next, a thick layer of PR is spun-coated on the backside of the wafer (Fig. 2b & 2c). The PR is then fully exposed using the first mask to open areas underneath the front side cantilevers (Fig. 2d). The second mask, containing the patterns for the cleaving trenches, is then used to partially expose the PR (Fig. 2e). The remaining thickness of the PR in the trenches pattern will create the desired etch delay in the next step when the wafer is etched with DRIE (Figs. 2f-2h). The depth of the cleaving trenches depends on the thickness of the remaining PR and the selectivity of PR: Si in the DRIE process (Fig. 2i). This ensures that once the devices are totally released, the silicon wafer is still strong enough to stay as one piece (not breaking inside the RIE chamber). The wafer has the required cleaving lines through which the devices could be precisely cleaved and separated from the substrate (Fig. 2j).

A New Approach to Cleave MEMS Devices from Silicon Substrates

30 25
(a) (f)

733

24.71m

Depth in PR Trenches (m)

20 15 10 5 0 1min develop 2min develop 3min develop

(b)

(g)

(c)

(h)

10

20 Exposure Time (s)

30

(d)

(i)

Fig. 3 Trenches depth on PR vs. exposure time for different exposure times.

(e) Si wafer Devices to be released Photoresist Exposed photoresist

(j) UV light RIE

Fig. 2

The process flow of the cleaving technique.

3.1 Photoresist Pattering In this work, two layers of AZ4620 (providing a thickness of 24.71 m), which is known as a thick PR, is used to mask the backside etch. The PR spin parameters are a 500 rpm spread for 10 s and 2,000 rpm spin for 25 s. The wafer was then baked using a non-contact hotplate at 100 C for 90 s and a contact hotplate for 60 s. The deposited PR needs to be dehydrated for at least 2 h before the exposure. Fig. 3 shows the patterns depth obtained by applying different exposures (under UV exposure intensity of 11.2 mW/cm2 at 365 nm light) and developing times. Exposure times were varied from 2 s to 32 s with the samples developed in AZ400K for 1, 2 and 3 min. In two cases after PR development, there were PR residues left in the trenches pattern: 30 s expose/2 min develop and 26 s expose/3 min develop. Since PR residue in etch areas may result in non-uniform silicon etching, over-exposure and over-development are recommended to ensure consistent etch in the device regions. Fig. 4 shows a SEM image of an alignment mark after developing the PR on the backside of the wafer. Depending on the exposure and development times which define the remaining thickness of the PR in the
Fig. 4 Depth differences in the PR pattern shown by an alignment mark.

trenches, the photoresist would result in various configurations. Fig. 5 shows three different trenches with three different depths. Non-uniformity in the remaining photoresist would transfer to the silicon at the silicon etching stage (Fig. 6). In addition, aiming for two thin remaining PR in the trenches may cause losing PR in some sections of the trenches. Also, under developing the exposed photoresist would leave some residues in the trenches. Either case would transfer the effect of PR residues to silicon at the DRIE stage. Fig. 7 shows microscopic images of PR residues and losing PR in some sections. Also, Fig. 8 demonstrates the transferred PR defects on silicon. 3.2 ICPRIE Process The ICPRIE (inductively coupled plasma reactive ion etching) process has been done exploiting STS (surface technology systems) equipment which uses Bosch and unswitched RIE processes to provide vertical sidewalls. The parameters used in this process are given in Table 1.

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A New Approach to Cleave MEMS Devices from Silicon Substrates

PR residues in trenches

(a) (a)

(b)

Losing PR in some sections

(b) Fig. 7 Microscopic image of PR defects in the trenches.

Etched Si sidewall Photoresist

(c) Fig. 5 Uniform (a) and non-uniform (b, c) configurations of PR in the cleaving trenches.

Effect of PR residues in DRIE

(a)

Non-characterized PR patterning results in stepped silicon patterns in DRIE

(b) Fig. 8 Effect of PR residues on etched trenches. Fig. 6 Non-uniformity of PR in the trenches transfers to silicon in the DRIE process.

The regular characterization was done for the etching process using 10 spots across the wafer. Same masks including both main and trenches patterns were

used for the characterization. Table 2 presents the etch-rate, selectivity and uniformity of the DRIE process used in this work. The etching process was run for 65 cycles producing an average silicon depth of 94.4 m.

A New Approach to Cleave MEMS Devices from Silicon Substrates

735

Table 1

DRIE process parameters. Etching 10 s SF6 450 sccm 2,200 W 22 mTorr 10 C Passivation 3s C4F8 200 sccm 1,600 W 9 mTorr 10 C

Table 3

Etching depth differences. Second measurement 286 453.7 m 247.9 m 205.8 m

Parameters Cycle time Gas ICP power Pressure Temperature Table 2

Parameters

First measurement Number of etching cycles 166 Depth in devices region* 290 m Depth in cleaving trenches* 20 m Differences in depths 270 m

*Measured depths include the remaining PR thickness.

500
Fully Developed ~1.5um Remaining PR ~7um Remaining PR ~8um Remaining PR ~10um Remaining PR ~12um Remaining PR

Regular etching characterization.

Etched Depth (m)

Etch-rate (m/cycle) Selectivity (Si:AZ4620) Uniformity

1.45 32:1 2.2%

400 300 200 100 0 0 50

It was also determined that the cleaving trenches etched faster than the device regions of the wafer due to the open area etch-rate dependency. Table 3 shows the etching cycles and resultant depths of the etching process. To provide the etching depth for each case, the average is taken among different locations across the wafer to account for etch uniformity. In a different experiment, only trenches were patterned on a 4'' wafer with various exposure and development times. Same trenches sizes were compared in terms of delaying in DRIE. Fig. 9 demonstrates the etched depth of fully developed trenches in comparison to the trenches with 1.5 m-12 m remaining PR. This graph clearly shows that by picking only one size for trenches and adjusting the thickness of the remaining PR, a proper final trench depth after DRIE could be designed for various scenarios.

100

150

200

250

300

350

Etching Cycles

Fig. 9 Comparing trenches depths in DRIE for fully and partially exposed/developed PR.
Narrow trenches Wide trenches

4. Results of the Process

This technique has been tested on a single-side polished silicon wafer with ~500 m thickness. SU-8 cantilevers were produced on the front side of the wafers previous to this process. AZ4620 was used to mask the backside DRIE. Fig. 10 depicts two SEM images of the backside of the wafer. The figure shows the backside of two cantilevers, an alignment mark and the cleaving trenches between the cantilevers. The rougher etch in the trenches versus the main patterns is clearly shown in this image.

(a)

(b) Fig. 10 Etching depth inspected in the middle (a) and the end (b) of etching process.

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A New Approach to Cleave MEMS Devices from Silicon Substrates

Fig. 11 shows SEM images of a released SU-8 cantilever with a silicon proof mass and an array of three SU-8 cantilevers, respectively. These devices are cleaved by using the technique explained in this article. Note that the curvature of these cantilevers is related to the fabrication of the SU-8 itself and is not due to the cleaving process described here. Taking advantage of the same technique, designing all trenches in a same size for a different mask and using a supporting wafer at the final cycles of the DRIE, deeper cleaving trenches could be obtained. Therefore, devices could be separated while the wafer was still in one-piece and possible to be handled (Fig. 12). Since the supporting wafer was added for a short period and at the end of DRIE process, the wafers were only taped on the edges and no adhesion layer was used in between.
(b) Fig. 11 SEM pictures of a released SU-8 cantilever with a silicon proof mass and an array of three SU-8 cantilevers which are separated from the silicon wafer. (a)

5. Discussion
It was observed that once the PR is completely removed in the cleaving trench areas, the silicon subsequently etches at a quicker rate than in the device area. Table 3 reveals that once the silicon etching begins in the trenches, the depth difference is 270 m, whereas, close to the end of the DRIE process, the difference decreases to 205.8 m. Same effect was observed in the second experiment by comparing etch-rates of fully and partially developed trenches (Fig. 13). This behavior is due to the etch-rate dependency on the patterns aspect ratio [24, 26] and the depth of the etched regions. On the cleaving trench pattern, there were a variety of trench widths ranging from 100 m-800 m. Taking into account the trench widths and the size of the devices examined in this study, the 400 m width trenches were the optimal cases. However, it was noticed that the etching was slower in narrow trenches. Fig. 14 shows 100 m trenches which were not fully etched while the rest of the cantilever was released. In addition, too wide trenches might result in breaking the wafer in the middle of DRIE process due to wafer holding mechanism of the equipment.

Fig. 12 Deeper cleaving trenches were obtained by utilizing a supporting wafer at final stages of the DRIE.
2.5
Fully Developed Patterns

Etch Rate (um/Cycles)

2 1.5 1 0.5 0 0 100 200 300

~1.5um Remaining PR

400

500

600

Etching Cycles (um)

Fig. 13 Comparison of etch-rate in fully and partially developed trenches.

A New Approach to Cleave MEMS Devices from Silicon Substrates

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Proof Mass

100 m trench to release proof mass

Fully etched

Cleaving trench

Backside of the wafer

Innovates-Technology Futures) for providing microfabrication funding. Also, the authors would like to thank Norcada for technical assistance in this work.

References
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Fig. 14

Etch-rate in the narrower trenches was slower.

Deep trenches may cause breaking the wafer and shallow trenches could make the final cleaving stage too difficult. In our study, approximately 400 m was the optimum trench depth for a 550 m thick silicon wafer. This depth allowed relatively easy cleaving, while keeping the substrate as one piece for handling prior to the final cleaving.

6. Conclusions
A new approach of cleaving is presented to improve dicing-free separating fabricated micro-devices from a silicon substrate. This modified cleaving technique is based on a single-step backside DRIE of silicon substrate which is normally done to release vibrating devices with large amplitude. Therefore, none of the process steps need to be replaced or changed for such an application eliminating any extra cost of dicing or laser cutting. This technique could even be used for a single-side polished wafer that keeps the process cheap by avoiding double side or SOI wafers. In addition, this technique avoids wet etching including HF immersion which potentially affects MEMS devices. In case of prototyping, this technique is advantageous since it does not need accurate and time-consuming characterization, although it could be precisely characterized for various academic and industrial requirements.

Acknowledgments
Authors would like to thank CMC Microsystems, NSERC (Natural Sciences and Engineering Research Council of Canada) and AITF (Alberta

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