PRELIMINARY ASSIGNMENT A1-001-A IZAIDI BIN WAN IBRAHIM - GIT 0763 PART 1: MOSFET Device Structure 1.

The advantages of CMOS over its Bipolar counterpart is: - Lower power dissipation - Small si e - !as" and cheap to fa#ricate -$ood switching %in digital& '. The cross section structure of the (MOS ) *MOS transistors with the Source %S&+ $ate %$& and the ,rain %,& gate clearl" state was shown #elow: gate
source drain n+ source drain n+ p-substrate

p+

p+ n+ p-substrate

(MOS -. !.planation of #od" effect:

*MOS

MOS #asicall" have four terminals which is source %S&+ gate %$&+ drain %,&+ and #od"/su#strate %B& terminals. (ormall"+ the su#strate is connected to the source and ma0ing it three terminal. 1hen the #od" is not connected to the source+ it will effect the value of threshold voltage+Vth and will cause #od" effect. PART 2: MOSFET Operation 1. Based on the (MOS structure a#ove+ the operation of the transistor for the following situations is e.plain #elow: (MOS will operate in cutoff region when there is no gate voltage applied. there will #e no current flow. 1hen positive voltage applied at the gate+ the channel will #e created under the gate that allow current to flow #etween source and drain. 1hen small ,rain to Source voltage+ 2 ,S applied+ the current will increase linearl" proportional to the 2,S. The (MOS is operate in linear region. 1hen 2 ,S is increased larger than .2,Ssat + the (MOS will operate in saturation region and the current will #e saturate. PART 3: MOSFET Characteristic The graph for 3,S42,S characteristic and e.planation for - main MOS operating regions are shown #elow:

Ids

The three main operating region for the MOS transistors is cutoff+ linear and saturation region. 5or 2$S 62T7 + the MOS is in cutoff region. ,uring this region+ there Vgs4 is no current flow+ 3,S 8 9:. 1hen 2$S ;2T7 and 2,S 62,S -2T7 + the MOS will Vgs3 operate in linear region. The current in this region is proportional with the 2 ,S. 1hen Vgs2 2$S ;2T7 and 2,S ;2,S -2T7 + the MOS will go to the saturation region. :t this Vgs1 Vds region+ the current will saturate although the 2 ,S is increasing. The e<uation for the current during linear and saturation region is shown #elow. Saturation region : PART 4: Fabrication Process Step

Linear region : 1. Terms e.planation:

a O!i"ation 4 *rocess to produce a thin la"er of o.ide on the surface of a wafer . b Thresho#" vo#ta$e i%p#ant 4 One wa" to ad=ust the threshold voltage #" using ion implantation. c Deposition 4 *rocess of grows+ coats+ or other material that transfer a material onto the wafer. " Etchin$ 4 *rocess of selectivel" removing a la"er of material.

e Dopin$ 4 3ntroduces impurities into a pure semiconductor for the purpose of modulating its electrical properties. & Spacer o!i"e 4 Conformal la"er of dielectric silicon o.ide is deposited over the entire wafer. $ 'on i%p#antation 4 *rocess accelerated the ioni ed particles through an electrical field and impacted into a solid. h Annea#in$ 4 7eat treatment that given to a semiconductor materials to repair the lattice damage. '. Ma=orit" carrier in the following materials: a) Phosphor s 4 !lectrons )) Ars'"$! 4 !lectrons !) A"#$%o"& 4 !lectrons *) Boro" - 7oles PART (: CMOS Circuit Desi$n an" Techno#o$) Sca#in$ 1. The scaling affect the performance of the transistors #" increasing the speed+ reduce the power consumption+ and reduce the cost for the fa#rication. This scaling also increased the gate-o.ide and =unction lea0age+ lowering output resistance and transconductance. '. Short Channel !ffect : : short channel effect is an effect where the channel length is the same order with magnitude of depletionla"er widths of the source and drain =unction. 1hen the length is reduced to increase the operation speed and num#er of components per chip+ short channel effect is said to arise. PART *: +sin$ CMOS &or Di$ita# 'C Desi$n 1. CMOS technolog" is a preferred technolog" for digital 3C #ecause it ena#les chips that are small in si e to have features li0e high speeds and efficient usage of energ". The" also have ver" low static power suppl" drain most of the time. *ower drain onl" occur when the transistors are switching #etween the two states. CMOS technolog" also have a high degree of noise immunit". '. Operation of an inverter using the Transistor Transistor Logic %TTL& and CMOS technolog" : TTL inverter 1hen low voltage applied at the input+ no #ase current flow to the >'. Thus+ >' also cutoff. Therefore+ the current will flow from the 2cc to the #ase of >-. Then >- is O( and the current will flow from the collector to the emitter of >-. >? is in off state. Therefore+ the output will #e high. 5or the 7igh voltage applied at the input+ the >1 will #e on and the current will flow through collector to on the >'. 1hen >' is on+ the current will not flow through #ase of >-. Therefore+ the >- will #e in off state and no current will flow from 2cc to the output #ut the current at the output will flow through the ground. Thus+ output will #e in low state. ') Ga(($ % - 7oles

TTL inverter 1hen low voltage applied at the input+ the *MOS transistor%M1& will #e O( and the (MOS transistor%M'& will #e in O55 state. Therefore+ the voltage 2dd will flow through *MOS and the output will #e high. 1hen high voltage applied at the input+ the *MOS transistor will #e O55 and (MOS transistor will #e O(. Therefore+ the output will flow to the ground. SO+ the output will #e low. CMOS inverter