IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO.

1, JANUARY 2010

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Self-Repairing SRAM Using On-Chip Detection and Compensation

Niladri Narayan Mojumder, Student Member, IEEE, Saibal Mukhopadhyay, Member, IEEE, Jae-Joon Kim, Member, IEEE, Ching-Te Chuang, Fellow, IEEE, and Kaushik Roy, Fellow, IEEE

AbstractIn nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause signicant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose a closed-loop compensation scheme using on-chip monitors that directly sense the global read stability and writability of the cell. Simulations based on 45-nm partially depleted silicon-on-insulator technology demonstrate the viability and the effectiveness of the scheme in SRAM yield enhancement. Index TermsDesign, failure, static RAM (SRAM), variation, yield.

I. INTRODUCTION

NDOM variations in the device characteristics can result in read and write failures in static-RAM (SRAM) cells, causing substantial yield degradation [9], [10]. Both systematic global variations (that affects all the nMOS and pMOS devices in an SRAM die identically, e.g., channel length variation) and random local variations (which results in mismatches between the devices in a particular cell, e.g., random dopant uctuations, line edge roughness) contribute to yield degradation [7], [8]. The conicting requirements for read stability and writability in SRAM cell limit the opportunity of cell transistor sizing and/or static assignment of cell terminal voltages in improving cell robustness. Hence, the majority of prior efforts [1], [2] in improving the cell robustness against local random variation focused on dynamic control of cell terminal voltages depending on read and write operations. The dynamic approaches suffer from
Manuscript received March 07, 2008; revised August 27, 2008. First published April 07, 2009; current version published December 23, 2009. The work of S. Mukhopadhyay, J.-J. Kim, and C.-T. Chuang was supported in part by the Defense Advanced Research Projects Agency under Contract HR0011-07-90002. N. N. Mojumder and K. Roy are with the Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 USA (e-mail: niladri@ecn.purdue.edu; kaushik@ecn.purdue.edu). S. Mukhopadhyay was with the High Performance Circuit Design Group, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. He is now with the Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 80523 USA (e-mail: saibal@ece.gatech. edu). J.-J. Kim is with the High Performance Circuit Design Group, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: jjkim2@us.ibm.com). C.-T. Chuang was with the High Performance Circuit Design Group, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. He is now with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (e-mail: chingte.chuang@gmail.com). Digital Object Identier 10.1109/TVLSI.2008.2008808

the limitations that, they may require two separate supply voltages, additional circuits, and complex timing to switch between two supply voltages depending on the read or the write operation. Finally, none of these methods exploit the dependence of cell failures on the global variability. While random within-die variation has been receiving attention as the major source of failures in the SRAM memory array, the combined effect of the random within-die variations and the systematic inter-die variations on the cell stability and margin has not been extensively studied. The effect of global threshold variations on the cell failure characteristics has voltage been rst studied and exploited in [3] and [5]. In [3] authors proposed a scheme to sense the global inter-die corner of a chip by monitoring leakage of an entire SRAM array or delay of a long inverter chain. Depending on the global inter-die corner, reverse or forward body bias is applied to reduce the total number of faulty cells in a die. However, this approach suffers from the limitation that, monitoring array leakage or inverter chain delay cannot distinguish between global variation in pMOS and nMOS devices [5]. As explained in Section III, the SRAM dies, which have different global corners of pMOS and nMOS devices are more vulnerable to parametric failures compared to the ones having same global corners for pMOS and nMOS. Further, it relies on the mathematical modeling of the dependence of cell failure on global process variation. Moreover, repairing using body bias is only applicable to bulk-CMOS devices and cannot be applied for partially depleted silicon-on-insulator (PD/SOI) technologies. The effectiveness of body bias also expected to reduce with scaling [13]. In this paper, we proposed a scheme for post-silicon adaptive repair of SRAM array considering the strong relationship that exists between systematic inter-die variations and random within-die variations. The novelty of the proposed scheme is to directly sense the global read stability and writability of an SRAM die and apply proper cell correction/compensation mechanism using cell and peripheral supply voltages to mitigate the dominant type of failure. Since the direct sensing of the global read stability and writability helps to successfully distinguish global corners of nMOS and pMOS devices, the proposed scheme becomes more effective in reducing the parametric failures. In brief, the salient features of the proposed compensation technique are as follows. 1) Direct detection of the global Read and Write corners. 2) Consideration of the pMOS and nMOS s as separate process parameters. 3) Cell corrections can be applied through the proper choice and/or )suitable for PD/SOI of voltage signals ( as well.

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4) No dynamic change in signalssimple design and timing. 5) Iterative closed loop compensation scheme improves the parametric process yield signicantly. In the context of our proposed self-repair approach, the phrase closed loop basically means that the compensation method is iterative in nature. As read and write failure mechanisms are disjoint, it is imperative to ensure that a read compensation does not actually degrade the cell writability and vice versa. Once a read or write correction is made, we adopt a second level of stability detection to avoid any cell overcorrection. The compensation algorithm has pictorially been presented later in Section IV. The proposed scheme can effectively be used in the current/future microprocessor products with large on-chip SRAM caches with minimal change in the cell and array for parametric yield enhancement. This paper is organized as follows. As a background, in Section II, we briey discuss the effect of systematic inter-die and random intra-die variations on SRAM stability. Section III presents the simulation framework for our analysis. Section IV presents the proposed adaptive repair scheme and the closed-loop compensation algorithm. Section V illustrates the design and analysis of the individual system components used in our proposed SRAM stability compensation methodology. Section VI includes some important discussions on the nature and performance of our designed compensation system. Finally, Section VII concludes the paper. II. BACKGROUND: JOINT IMPACT OF INTER-DIE AND SHIFT ON SRAM STABILITY INTRA-DIE The systematic (or global) variation equally modies the characteristics of all the nMOS and pMOS devices in an SRAM die. However, the global variation in nMOS and pMOS devices can be different from each other. On the other hand, local random variation results in mismatch between neighboring devices in a die. This is illustrated in Fig. 1 for threshold voltage variation in a process. First, the of all nMOS (and pMOS) devices in a die is shifted from its designed value by a certain amount due to global systematic variation. Next, of different devices in an if a single die is considered, the SRAM cell in that die can vary from its global value due to local random variation. The local random variation results in mismatch between different devices in the cell and is the primary cause of parametric (read and write) failures in SRAM of all the nMOS [3]. The global variation modies the devices in the cell by same amount and all the pMOS devices by same amount. However, the global shift in nMOS and pMOS devices can be different. To illustrate the interaction of variations on SRAM the global inter-die and local random stability, we consider SRAM write failure. The write failure occurs if the node storing 1 in an SRAM cell cannot be discharged to 0 during the wordline ON time. The write failure becomes more probable if the discharge current through the access transistor in an SRAM cell (Fig. 1) reduces. Consider two SRAM dies from two different global corners and assume that the local variations in both dies are the same. Further, and die B from a high consider die A from a low nMOS global corner. Write failure in an SRAM cell is a strong
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Fig. 1. Global systematic and local random variation in device threshold voltage degrades yield of SRAM design.

function of the strength of access transistors (AL, AR in Fig. 1) [12]. Assume that the time required discharging the node L from logic 1 to logic 0 for two different dies A and and , respectively. The global variation shifts the B be nominal value of the write time and due to higher of nMOS, . The local variation results in a variation in the write time for different cells in the array. Hence, for the same amount of local variation, SRAM array which has a higher nominal write time is expected to have a larger number of cells with faulty write operation as illustrated in Fig. 2. Thus, the total number of faulty cells in an SRAM array is not only a function of the local within-die variation, but, also a strong function of the global inter-die variations. III. RELATIONSHIP BETWEEN SYSTEMATIC INTER-DIE AND RANDOM WITHIN-DIE VARIATION In our simulation framework, we rst apply a certain amount shift to all the six transistors of a given SRAM of global cell (represents systematic inter-die shift). Then, on top of the global variations, we impose a certain amount of local random shifts ( for ) to the individual transistors of the cell. The standard deviation of the local shift for a is given by transistor (1) and are, respectively, the width and length of the where th transistor of the SRAM cell for . In our simulation framework, the threshold voltage for individual nMOS and pMOS devices being inuenced by both local and global variations can be expressed as:

(2a) (2b) s and s In (2a) and (2b), we assume the sign of both to be positive for the slower and negative for the faster process corners. The simulation model, described above, allows us to measure both the read and the write failure probabilities of the cell designed in 45-nm PD/SOI technology (say) for every possible process points over the global threshold voltage

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Fig. 2. Case study: Inter-die V variation pushes the cell towards the failure point but within-die variation causes the actual failure.

Fig. 3. Global variation amplies the effect of local variation.

plane. In our simulation framework, we have dened the read and the write stabilities as a logarithmic function of the corresponding cell failure probabilities obtained from statistical simulation based on importance sampling [4]. Throughout this paper, the read and write stability (writability) as dened in (3a) and (3b) will be our primary metric for SRAM stability analysis. (3a) (3b) The plot in Fig. 3 directly shows that, the stability of a cell due to local random variation depends on the global process corner. Cell read stability worsens at low- nMOS and highpMOS corners, whereas writability degrades at low- pMOS and high- nMOS corners. Fig. 3 also illustrates the fact that read and write failures in an SRAM cell are disjoint for most of the global process corners. Our essential goal in designing the self-repairing SRAM array is to properly exploit this failure amplifying property of the systematic inter-die variations by sensing the global read and write corner the cell is in. IV. OVERALL SYSTEM CHARACTERISTICS OF THE SELF-REPAIRING SRAM ARRAY Fig. 4 illustrates the overall system architecture of the proposed SRAM array with adaptive repair mechanism. It includes the conventional SRAM array with on-chip circuits for failure characterization, a global read stability and writability detector, a very simple digital logic circuit for making decision
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Fig. 4. System diagram of the self-repairing SRAM array with on chip monitor and compensation circuitry.

on whether read or write correction is required, and a circuit for generating the adaptation signals for the required cell corrections. The read stability and writability detectors detect the global read and write stabilities. They detect whether a read or a write correction is required, and accordingly generate proper digital signals (0 or 1) to actuate the Decision making and Adaptation signal generation block that applies a proper or ) to the wordline and cell supply voltage ( . terminal The proposed adaptive repair algorithm is illustrated in Fig. 5. First, the adaptive repair circuit detects whether an SRAM array requires a read or a write correction. If it does not require any correction (i.e., both the read stability and writability are above some threshold level or correction boundary), it is placed in the bin marked as CORRECT ARRAY. If it does require a read OR write correction, the terminal voltages are properly modied to apply that correction. In the unlikely case the system indicates the requirement for both types of corrections; the decision logic can be congured to give priority to any of the events. After the proper type of correction has been done, the read and write stabilities of the array with modied cell terminal voltages are redetected to avoid any overcorrections that might degrade the process yield. This second level of stability

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Fig. 5. Adaptive compensation algorithm.

Fig. 7. Performance of the read stability sensing metric. Fig. 6. SRAM global read stability sensor (V

0V

).

In Section V, we discuss the design of individual modules of the proposed self-repairing system. detection ensures the fact that an array corrected for read stability does not fail in terms of writability and vice versa. If the second level of stability detection shows that both the read stability and writability are above the correction boundaries, the array is placed in the CORRECT ARRAY bin, otherwise it is placed in the bin tagged as Array Suffering from Stability. A regular functional test of the memory array is performed for all the dies in CORRECT and Suffering from Stability bins before shipping. Interestingly, it is possible to apply the proposed scheme by applying full functional test to memory array multiple times. First to detect whether the number of read or write failures, next, to ensure that the adaptive repair scheme did not introduce any new failures and taking appropriate decisions, and nally, before shipping the products. It should be noted that the proposed read stability and writability detection scheme does not replace the regular functional tests; it only helps in correction of parametric read/write failures.
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V. DESIGN PRINCIPLES AND ANALYSIS OF INDIVIDUAL SYSTEM COMPONENTS In this section, we focus on the design issues associated with three major components of the self-repairing SRAM array and evaluate their effectiveness to the overall system yield improvement. As depicted in Fig. 4, the read stability detector, writability detector and the correction scheme using proper wordline and cell supply voltages constitute the heart of the system and accordingly, the overall system performance highly depends upon the efcient design of these individual building blocks. A. Design of the Read Stability Detector The major challenges in designing the read stability detector is the identication of a metric that accurately capture the global

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Fig. 8. SRAM global writability sensor.

read corner of the memory array. To capture the cell read stability, we propose a monitor to sense the difference between of the half-cell composed of PL, AL, NL, trip voltage of the half-cell composed of and read disturb voltage PR, NR, and AR (Fig. 6). To measure the trip voltage, the input and output of the inverter PL-NL are connected, the AL device and drain at , the feedback path connecting has gate at nodes L and R is eliminated, and the voltage at node L is measured. To measure the read disturb voltage, gates of PR , gate of AR is at , drain of and NR are connected to AR is at , the feedback connection for nodes R and L is removed, and the voltage at node R is measured. Next, and are connected to the drain and gate of pMOS (P0) of a differential pMOS pair, respectively. The other pMOS (P1) of the pair has gate at GND and drain at . The current through the two pMOSs are compared using a current comparator [11]. The differential pair needs to be properly matched. As illustrated in Fig. 7, SRAM cells with higher has larger read stability as dened in (3a)]. If the falls below a certain level ( in Fig. 6) which corresponds to a minimum tolerable value of normalized read stability, then current through the reference pMOS (P1) becomes larger than that through the sensing pMOS (P0), and the output of the current comparator indicates that read correction is required. The SRAM cell used for sensing read/trip voltages needs to be designed with large devices to minimize the effect of local variations on those voltages. This can also be achieved by properly conguring and connecting a large number of actual SRAM cells in parallel. Later we will discuss the impact of cell layout on global variation.
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B. Design of Writability Detector For writability sensor, the SRAM cell designed with large devices (or by connecting cells in parallel), is used to capture the feedback effect which plays an important role in write operation (Fig. 8). First, when the wordline signal is low, node L is precharged to 1 and node R is predischarged to 0. The bitwhereas a is applied at line R is held at the bitline L. When the WL signal goes high for write operation, node L discharges to 0 whereas node R is charged to 1. Voltages at both nodes are sampled at the negative edge of the wordline signal and compared. If node L voltage is less than node R voltage at that time, the comparator indicates that the write operation is correct. If a correct write operation can be performed at a higher value of , it indicates that the writability (write margin) of the cell is high. Hence, for global corners with good writability (i.e., less prone to write failures), the cell will be able to perform a correct write operation . This is illustrated in even with a high value of corFig. 9 which shows that, the higher value of responds to higher writability as dened in (3b)). From Fig. 9, one can select the reference value of which corresponds to a minimum tolerable writability. During measurevalue is applied to all the SRAM dies. For ment, SRAM arrays where proper write operation cannot be achieved with this reference value of , the sensor should indicate that a write correction is required. Note that, since the sensor operates using transient WL signal, it also captures the frequency dependence of write failures. As in case of global read stability detector, in this case the devices in the sensor cell

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Fig. 9. Performance of the writability sensing metric.

either need to be large or need to be designed by connecting a large number of actual cells in parallel to minimize the impact of local random variability. In order to sense the cell writability, we store a 0 at node connected to R and 1 at node L. This time we have the bitline R and a variable voltage on the bitline L. As soon as the wordline turns on, node R tries to get charged to 1 and node L tend to discharge to 0. The tendency of node L to discharge to zero is a strong function of the variable . Lower the value of (it can vary only voltage ), worse is the cell writability. The variable between 0 and is dened as weak write test output in Fig. 9. voltage The methodology is explained in detail in [6]. In our proposed on-chip detection scheme, we sense the SRAM cell writability as described as follows. required to ip the 1) First, we determine the voltage cell under nominal conditions. 2) Apply the voltage as predicted above to the port in Fig. 8. 3) If the cell ips, we conclude that no write correction is required (i.e., the cell is already in a good write corner), but if it does not, write correction is applied. C. Read and Write Failure Compensation in Self-Repairing Sram Array (Adaptation Signals) In the proposed self-repairing SRAM array, we chose to use variable cell terminal voltages as adaptation signals, due to signicantly less process and design overhead. Application of proper cell terminal voltages suitable for read operation at the worse read corners helps correcting the faulty dies. On the other hand, application of appropriate cell terminal voltages suitable for write operation at the worse write corners help correcting the faulty dies from that corner. Fig. 10 illustrates that lower wordline voltage (0.9 V instead of nominal 1.0 V) and nominal cell supply voltage improve read stability at the worst global read corner by 13%. On the other hand, writability gets improved by 37% with a lower cell supply voltage (0.9 V instead of nominal 1.0 V) with nominal wordline voltage at the worst global write corner. We have already observed that the cell read stability and the writability depend on the global inter-die process corner. Thus, the proposed adaptation signals have been chosen as the low-cell for arrays with bad writability and lowsupply voltage wordline voltage for arrays with bad read stability.
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Fig. 10. Low-wordline voltage (V ) improves read stability and low-cell supply voltage (V ) improves the writability.

Fig. 11. Parametric yield improvement using adaptive self-repair scheme with 3% column redundancies.

VI. STATISTICAL YIELD ANALYSIS The effectiveness of the proposed self-repairing SRAM array design is veried using statistical simulations based on 45-nm PD/SOI SRAM cell. The adaptation technique using the variable terminal voltages is used for the simulation. The simulation framework for yield analysis has been constructed in accordance with the adaptive compensation algorithm illustrated in Fig. 5. In Fig. 11, we have plotted parametric process yield as a function as dened in of global nMOS and pMOS variability [ (2b)]. It is evident from Fig. 11 that the proposed SRAM array with adaptive repair algorithm has an improved parametric yield compared to the SRAM array with no adaptive repair mechanism. Using the adaptive self-repair scheme, the parametric yield can be improved by up to 12% for a global variability of 60 mV (i.e., standard deviation of the Gaussian distribution for ). the systematic inter-die So far, we have seen that using variable cell terminal voltages (low-wordline voltage for read stability improvement and low-cell supply voltage for writability correction) as adaptation signals, we can signicantly reduce the number of functional failures within a given SRAM array. But, in an SRAM, the reduction of the functional failures using a lower supply voltage can potentially increase the number of access-delay failures.

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Fig. 14. Variation of array failure probability on overall cell stability for different column redundancies for a 512 512 SRAM array.

Fig. 12. SRAM access delay distribution over the global process plane.

Fig. 15. Absolute improvement in process yield (%) for different column re. dundancies (CR) at 

GLOBAL = 100mV

Fig. 13. Delay distribution for the compensated and uncompensated cells under variations.

As illustrated in Fig. 12, after read or write corrections using a reduced supply voltage, the SRAM access-delay increases slightly, if the cell is already in the slow nMOS corner. However, statistical analysis for the access-delay failures with and without self-repair scheme (Fig. 13) reveals that events where a cell is compensated for read or write failure, yet fails due to the access-delay are extremely rare. The proposed self-repair algorithm cannot recover these rare cases, unless, we slightly relax access-delay constraint. In the proposed self-repairing compensation technique, one of the major design issues is to properly choose a reference for the SRAM read and write stabilities (the design parameters that essentially determine the borderline between a correct cell and a faulty cell). In accordance with (3a) and (3b), we dene the overall cell stability as the sum of individual read and write stabilities with the assumption that the probability of joint occurrence of read and write failures in an SRAM cell is negligibly small and can easily be ignored. In our proposed design, read and write reference stabilities explicitly depend on the target process yield specication (or the memory array failure probability) and the redundancies available in the memory array architecture [3], [5]. This can be illustrated by considering an SRAM array having a certain number of rows and columns (512 512
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array for our analysis). Given a target array failure probability and percentage column redundancies available in the architecture, we can predict the tolerable overall cell failure probability (Fig. 14) [5]. In Fig. 14, we have plotted the array failure probability as a function of the overall cell stability dened as the sum of SRAM read and write stabilities. As expected, we observe that the overall array failure probability decreases for a xed cell stability as we increase the column redundancies (CR) from 0.2% to 10%. Fig. 15 shows the comparison of yield between the array with the proposed self-repair scheme and the conventional array. It can be seen that the overall yield increases with the proposed scheme regardless of the array column redundancy. It is worthwhile to note that the amount of yield improvement in the proposed array compared to the conventional one is not a monotonic function of the number of redundant columns. Yield improvement decreases as the number of column redundancies increases from 3% to 10% since the number of cells which should be corrected decrease as redundancy increases. On the other hand, yield improvement increases with the increase of column redundancy from 1% to 3%. This is due to the fact that the possibility of cell overcorrection with our proposed self-repair scheme goes higher for a smaller number of redundant columns. In such cases, we eventually end up degrading the cell writability while trying to improve the read stability of the cell and vice versa. As mentioned in Section V, the read and write stability sensors in our proposed self-repairing SRAM array can either be realized using larger lumped devices or by connecting a

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Fig. 16. Connecting 2000 cells in parallel gives more accurate information about the global read corner than using a single SRAM cell designed with lumped devices.

Fig. 17. Variation of SRAM yield improvement prole with sensor output variability using self-repair technique.

large number of actual cells in parallel to eliminate the effect of random local variations. However, our study reveals that the latter approach is more accurate in terms of sensing errors and capturing layout effects on global variations. As depicted in value for an SRAM cell using larger Fig. 16, lumped devices is almost 5% higher than that of an actual cell. On the other hand, connecting 2000 actual SRAM cells value as that of a in parallel gives us the same single cell. Similarly, connecting a substantial number of cells in parallel provides more accurate information about cell writability at a particular global corner than using single SRAM cell composed of large devices. The self-repairing SRAM array, proposed in this paper, suffers slightly from internal sensor output variations. Although, in our design, we have kept the sensor devices reasonably large and hence less prone to process parameter variations, still there exist some internal sensing errors when we shift from one global corner to the other. We have analyzed the sensing error handling capability of the proposed system and the results are shown in Fig. 17. We have plotted absolute process yield improvement as a function of the sensor output variability ( of the Gaussian random distribution). As shown in Fig. 17, the self-repair technique is capable of offering a reasonably good process yield (7%) even with a large parametric variability of the sensing devices ( as close as 50 mV). Finally, Fig. 18 explicitly emphasizes the fact that the yield estimations have been carried with a reasonably high degree of
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Fig. 18. (a) 95% condence band at CR 10% f3 4% ! 4 8g (b) 95% condence band at CR = 3% f11 51% ! 13 11%g (c) 95% condence band at CR 10% f5 83% ! 6 81%g.

>

>

; :

condence. For a given memory array, we have considered the absolute yield improvement results for three different column redundancies (viz. 1%, 3%, and more than 10% as depicted of 100 mV. in Fig. 14) and a global variability Fig. 18(a)(c) essentially predicts the error bands required to achieve a condence level of 95% for three different column redundancies. It is quite apparent from Figs. 15 and 18 that with 95% condence, the maximum possible error in our absolute . yield estimation stays within VII. CONCLUSION In this paper, we investigated the interaction between the variations on SRAM read and write inter-die and intra-die failures and proposed an efcient and reliable self-repairing closed-loop compensation scheme using on-chip monitors that sense the global readability and writability of the cell directly, without sensing the process corner itself. The proposed

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self-repairing SRAM arrays with the exclusive facility for fast detection of the global read and write corners and subsequent compensation with minimal design overhead can be effective in achieving high-parametric yield in nanometer technologies. REFERENCES
[1] K. Zhang, A 3-GHz 70 MB SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply, in Proc. Int. SolidState Circuits Conf. (ISSCC), 2005, vol. 1, pp. 474611. [2] S. Ohbayashi, A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits, in Proc. VLSI Circuits, 2006, pp. 1718. [3] S. Mukhopadhyay, Design of a process variation tolerant self-repairing SRAM for yield enhancement in nanoscaled CMOS, in Proc. IEEE Int. Test Conf., Nov. 2005, pp. 11261135. [4] R. Kanj, R. Joshi, and S. Nassif, Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events, in Proc. DAC, Jul. 2006, pp. 6972. [5] S. Mukhopadhyay, H. Mahmoodi, and K. Roy, Reduction of parametric failures in sub-100-nm SRAM array using body bias, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 1, pp. 174183, Jan. 2008. [6] A. Meixner and J. Banik, Weak write test mode: An SRAM cell stability design for test technique, in Proc. Int. Test Conf., Nov. 1997, pp. 10431052. [7] D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, Monte carlo modeling of threshold voltage variation due to dopant uctuations, in Proc. Symp. VLSI Tech., Jun. 1999, pp. 169170. [8] H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Estimation of delay variations due to random-dopant uctuations in nanoscale CMOS circuits, IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 17871796, Sep. 2005. [9] A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, The impact of intrinsic device uctuations on CMOS SRAM cell stability, IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658665, Apr. 2001. [10] B. Cheng, S. Roy, and A. Asenov, Impact of intrinsic parameter uctuations on SRAM cell design, in Proc. 8th Int. Conf. Solid-State Integr. Circuit Technol. (ICSICT), Oct. 2006, pp. 12901292. [11] S. Jae-Yoon, Y. Hongil, C. Ki-Chul, L. Hyun-Seok, H. Sang-Pyo, L. Kyu-Chan, Y. Jei-Hwan, S. Dong-Il, and C. Soo-In, A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplier, and dual-referenced adjustment scheme for temperature sensor, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 631640, Apr. 2003. [12] Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King, and B. Nikolic, FinFET-based SRAM design, in Proc. Low Power Electron. Design, Int. Symp., Aug. 2005, pp. 27. [13] A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, and V. De, Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, in Proc. Low Power Electron. Design, Int. Symp., Aug. 2001, pp. 207212.

Saibal Mukhopadhyay (S99M07) received the B.E. degree in electronics and telecommunication engineering from Jadavpur University, Kolkata, India, in 2000, and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2006. He was a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he was involved in high-performance circuit design. Since September 2007, he has been an Assistant Professor with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta. He is the author or coauthor of more than 50 papers published in refereed journals and conference proceedings. His current research interests include analysis and design of low-power and robust circuits in nanometer technologies. Dr. Mukhopadhyay was the recipient of the IBM Ph.D. Degree Fellowship Award for 2004 and 2005. He was also the recipient of the Semiconductor Research Corporation Technical Excellence Award in 2005, the Best in Session Award at the 2005 SRC TECNCON, and the Best Paper Awards at the 2003 IEEE Nano and the 2004 International Conference on Computer Design.

Jae-Joon Kim (S02 M04) received the B.S. and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1994 and 1998, respectively, and the Ph.D. degree from the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, in 2004. From 1998 to 1999 he was a Custom Circuit Designer with TLI, Inc., Korea. In 2000, he was an Intern at Intel Circuit Research Laboratory, Hillsboro, OR. In 2001 and 2002, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he was involved in silicon on insulator circuit research and has been a Research Staff Member since May 2004. His current research interests include technology/circuit co-design.

Niladri Narayan Mojumder (S05) received the B.E. degree in electronics and telecommunication engineering from Jadavpur University, Kolkata, India, in 2006. He is currently working toward the Ph.D. degree in electrical and computer engineering at Purdue University, West Lafayette, IN. In 2007, he was a Research Intern in the High-Performance Circuit Design and Design for Manufacturability Group. In 2008, he was an Intern at IBM T. J. Watson Research Center, Yorktown Heights, NY. His current research interests include device-circuit co-design for Si and non-Si structures in nanometer regime, robust, variation tolerant, low-power and high-performance very large scale integration (VLSI) circuit and memory design.

Ching-Te Chuang (S78M82SM91F94) received the B.S.E.E. degree from the National Taiwan University, Taipei, Taiwan, in 1975, and the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1982. From 1977 to 1982, he was a Research Assistant in the Electronics Research Laboratory, University of California, Berkeley, where he was involved in bulk and surface acoustic wave devices. In 1982, he joined the IBM T. J. Watson Research Center, Yorktown Heights, NY. From 1982 to 1986, he worked on scaled bipolar devices, technology, and circuits. In February 2008, he joined the Department of Electronic Engineering, National Chiao-Tung University, Hsinchu, Taiwan, as a Chair Professor. He studied the scaling properties of epitaxial Schottky barrier diodes, did pioneering work on the perimeter effects of advanced double-poly self-aligned bipolar transistors, and designed the rst subnanosecond 5-Kb bipolar emitter-coupled logic static-RAM (SRAM). From 1986 to 1988, he was the Manager of the Bipolar Very Large Scale Integration (VLSI) Design Group, working on low-power bipolar circuits, high-speed high-density bipolar SRAMs, multiGigabits per second ber-optic data-link circuits, and scaling issues for bipolar/BiCMOS devices and circuits. Since 1988, he has been managing the High-Performance Circuit Group, investigating high-performance logic and memory circuits. Since 1993, his group has been primarily responsible for the circuit design of IBMs high-performance CMOS microprocessors for enterprise servers, PowerPC workstations, and

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game/media processors. Since 1996, he has been leading the efforts in evaluating and exploring scaled/emerging technologies, such as partially depleted silicon-on-insulator (SOI) technology, universal time/SOI, strained-Si devices, hybrid orientation technology, and multigate/FinFET devices, for high-performance logic and SRAM applications. Since 1998, he has been responsible for the Research VLSI technology circuit codesign strategy and execution. His group has also been very active and visible in leakage/variation/degradation tolerant circuit and SRAM design techniques. He has authored or coauthored many invited papers and over 260 papers published in international journals such as the International Journal of High Speed Electronics, PROCEEDINGS OF IEEE, IEEE CIRCUITS AND DEVICES MAGAZINE, and Microelectronics Journal. He holds 27 U.S. patents with another 14 pending. Prof. Chuang has received one Outstanding Technical Achievement Award, one Research Division Outstanding Contribution Award, ve Research Division Awards, and 12 Invention Achievement Awards from IBM. He has received the Outstanding Scholar Award from Taiwans Foundation for the Advancement of Outstanding Scholarship for 20082013.In 1986 and 1987, he was a member of the Device Technology Program Committee for International Electron Devices Meeting, and the Program Committee for Symposium on VLSI Circuits from 1992 to 2006. He was the Publication/Publicity Chairman for Symposium on VLSI Technology and Symposium on VLSI Circuits in 1993 and 1994, and received the Best Student Paper Award Sub-Committee Chairman for Symposium on VLSI Circuits from 2004 to 2006. He has presented numerous plenary, invited, or tutorial papers/talks at international conferences such as the International SOI Conference, Design Automation Conference, VLSI-TSA, International Solid-State Circuits Conference Microprocessor Design Workshop, VLSI Circuit Symposium Short Course, International Symposium on Quality Electronic Design, International Conference on Computer Aided Design, Asia-Pacic Microwave Conference, VLSI-DAT, International Society for Computer Aided Surgery, MTDT, World Scientic and Engineering Academy and Society, and VLSI Design/CAD Symposium, etc.: He was a corecipient of the Best Paper Award at the 2000 IEEE International SOI Conference.

Kaushik Roy (S83M83SM95F02) received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana-Champaign, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments Incorporated, Dallas, where he worked on eld-programmable gate array architecture development and low-power circuit design. In1993, he joined the Electrical and Computer Engineering Faculty, Purdue University, West Lafayette, IN, where he is currently a Professor and holds the Roscoe H. George Chair of Electrical and Computer Engineering. He has published more than 450 papers in refereed journals and conferences, holds eight patents, and is a coauthor of two books on Low Power CMOS VLSI Design (Wiley and McGraw Hill). His current research interests include very large scale integration (VLSI) design/computer-aided design for nanoscale silicon and nonsilicon technologies, low-power electronics for portable computing and wireless communications, VLSI testing and verication, and recongurable computing. He received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, the ATT/Lucent Foundation Award, 2005 the SRC Technical Excellence Award, the SRC Inventors Award, the Purdue College of Engineering Research Excellence Award, and the Best Paper Awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics and Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems Best Paper Award. He is Purdue University Faculty Scholar. In 2002, he was a Research Visionary Board Member of Motorola Laboratories. He has been a member of the editorial board of the IEEE DESIGN AND TESt, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was a Guest Editor for Special Issue on LOW-POWER VLSI IN THE IEEE DESIGN AND TEST (1994) and IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000), IEEE PROCEEDINGSCOMPUTERS AND DIGITAL TECHNIQUES(July 2002).

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