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DS2430A EEPROM
FEATURES
256-bit Electrically Erasable Programmable Read Only Memory (EEPROM) plus 64-bit one-time programmable application register Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute identity because no two parts are alike Built-in multidrop controller ensures compatibility with other MicroLAN products EEPROM organized as one page of 32 bytes for random access Reduces control, address, data and power to a single data pin Directly connects to a single port pin of a microprocessor and communicates at up to 16.3 kbits per second 8-bit family code specifies DS2430A communication requirements to reader Presence detector acknowledges when reader first applies voltage Low cost TO-92 or 6-pin TSOC surface mount package Reads and writes over a wide voltage range of 2.8V to 6.0V from -40C to +85C
PIN ASSIGNMENT
TO-92
DALLAS DS2430A
TSOC PACKAGE
1 2 3 6 5 4
1 2 3
1 2 3
PIN DESCRIPTION
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 TO-92 Ground Data NC TSOC Ground Data NC NC NC
ORDERING INFORMATION
DS2430A DS2430AP DS2430AT DS2430AV DS2430AX TO-92 package 6-pin TSOC package Tape & Reel version of DS2430A Tape & Reel version of DS2430AP Chip Scale Pkg., Tape & Reel
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OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2430A. The DS2430A has four main data components: 1) 64-bit lasered ROM, 2) 256-bit EEPROM data memory with scratchpad, 3) 64-bit one-time programmable application register with scratchpad and 4) 8-bit Status Memory. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the four ROM Function Commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. The protocol required for these ROM Function Commands is described in Figure 8. After a ROM Function Command is successfully executed, the memory functions become accessible and the master may provide any one of the four memory function commands. The protocol for these memory function commands is described in Figure 6. All data is read and written least significant bit first.
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MEMORY
The memory of the DS2430A consists of three separate sections, called data memory, application register and status register (Figure 5). The data memory and the application register each has its own intermediate storage area called scratchpad that acts as a buffer when writing to the device. The data memory can be read and written as often as desired. The application register, however, is one-time programmable only. Once the application register is programmed, it is automatically write protected. The status register will indicate if the application register is already locked or if it is still available for storing data. As long as the application register is unprogrammed, the status register will read FFh. Copying data from the register scratchpad to the application register will clear the 2 least significant bits of the status register, yielding a FCh the next time one reads the status register.
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Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain connection or 3-state outputs. The 1-Wire port of the DS2430A is open drain with an internal circuit equivalent to that shown in Figure 7. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second and requires a pullup resistor of approximately 5 k . The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset.
*5 k is adequate for reading the DS2430A. To write to a single device, a 2.2 k resistor and VPUP of at least 4.0V is sufficient. For writing multiple DS2430As simultaneously or operation at low VPUP, the resistor should be bypassed by a low-impedance pullup to VPUP while the device copies the scratchpad to EEPROM. 9 of 16 102199
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Transaction Sequence
The sequence for accessing the DS2430A via the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS2430A is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section.
DS2430A
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example.
1-Wire Signaling
The DS2430A requires strict protocols to insure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data. All these signals except presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2430A is shown in Figure 9. A reset pulse followed by a presence pulse indicates the DS2430A is ready to accept a ROM command. The bus master transmits (TX) a reset pulse (tRSTL, minimum 480 s). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After detecting the rising edge on the data pin, the DS2430A waits (tPDH, 15-60 s) and then transmits the presence pulse (tPDL, 60-240 s).
In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 s.
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This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Logic 1 Logic 0 Output Logic Low @ 4 mA Output Logic High Input Load Current (DATA pin) Programming Current SYMBOL VIH VIL VOL VOH IL IP MIN 2.2 -0.3
VPUP 5
CAPACITANCE
PARAMETER Capacitance SYMBOL CD MIN TYP MAX 800 UNITS pF
(tA =25C)
NOTES 7
ENDURANCE
PARAMETER Write/Erase Cycles SYMBOL NCYCLE MIN 100k TYP
(VPUP=5.0V; tA =25C)
MAX UNITS NOTES 10
AC ELECTRICAL CHARACTERISTICS
PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low Programming Time SYMBOL tSLOT tLOW1 tLOW0 tLOWR tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL tPROG MIN 60 1 60 1 0 1 480 480 15 60
exactly 15 15
5 4 8
5000 60 240 10
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NOTES:
1. All voltages are referenced to ground. 2. VPUP=external pullup voltage. 3. Input load is to ground. 4. An additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 s of this falling edge. 6. VIH is a function of the external pullup resistor and VPUP. 7. Capacitance on the data pin could be 800 pF when power is first applied. If a 5 k resistor is used to pull up the data line to VPUP, 5 s after power has been applied the parasite capacitance will not affect normal communications. 8. tRSTL should be limited to maximum 5 ms. Otherwise the DS2430A may perform a power-on reset. 9. Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always guarantee a presence pulse. 10. The Copy Scratchpad takes 10 ms maximum, during which the voltage on the 1-Wire bus must not fall below 2.8V.
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