NARAYANA ENGINEERING COLLEGE::NELLORE/GUDUR DEPARTMENT OF ECE

ACADEMIC YEAR: 2013 2014 OBECTIVE QUESTIONS Subject: VLSI Desi ! "R#$% &C'(('! t' ECE )EIE C*+ss : III B,TEC- II SEM F+cu*t. : A, SURENDRA REDDY/S/,S-AGUFT-A

UNIT 0 1
Mu*ti2*e c3'ice 1. The speed power product of any MOS technology is measured in [ ] a)K !) M"#sec c) $ d) oules %. &or depletion mode MOS&'T( threshold )oltage [ ] a) *.% + ,, !) #*.% + ,, c) *.- + ,, d) #*.- + ,, .. The technology which is characteri/ed !y high speed [ ] a)0MOS !) 120MOS c) 3a4s d)'05 6. 5atch up in 0MOS de)ice can !e a)oided !y [ ] 4) 2ncreasing temp !) doping control c) increasing the su!strate resistance d)decreasing su!strate doping le)el 7. Material used for metalli/ation is [ ] a)4luminum !) copper c)sil)er d)tungsten 8. Material used for gate o9ide in MOS technology. [ ] a) Si !) 3e c) Sio% d) 4lO% :. $oly silicon is a ;;;;;;;;; material [ ] a) 0rystalline !) 4morphous c) $oly crystalline d) <one -. Silicide is com!ination of [ ] a) Metal poly !) Metal#Silicon c) Metal#3e d) Metal#SiO% =. 2n modern 0MOS fa!rication( the pattern on each layer is created !y a) 2on implantation !) O9idation c) $hoto lithography d) 'ncapsulation 1*. The ad)antage of twin# tu! process [ ] a) 5ow comple9ity !) 5ow cost depletion c) 5atch up immunity d) high mas> count Fi** i! t3e b*+!4s: 11. '9pansion of 0+, is ;;;;;;;;;;;;;; 1%.;;;;;;;;;;;;;;;;;;;;; lithography is preferred in su!micron de)ice dimension 1.. The >inetics of thermal o9idation is modeled !y ;;;;;;;;;;;;;;;;;;;;;;model. 16. The static power dissipation in 0MOS technology is ;;;;;;;;;;;;;;; 17. 2n normal mode of operation in 0MOS( su!strate terminal of <MOS is connected to ;;;;;;;;;;; and su!strate terminal of $MOS is connected to ;;;;;;;;;;; T5ue / F+*se : 18. 0MOS technology is high delay than ;;;;;;;;;;;;;;;;;;; Technology 1:. The deficiency of MOS technology is ;;;;;;;;;;;;;;;;;;;;;;;; 1-. ?nder ,'$5'T2O< mode <MOS is ;;;;;;;;;;;;;;;;state. 1=. <MOS &'T@s are ;;;;;;;;;;;;than $MOS &'T@s %*. $ower dissipation in <MOS technology is ;;;;;;;;;;;compared to 0MOS technology.

UNIT 0 6
Mu*ti2*e c3'ice 1. MOS&'T operated in saturation when [ ] Aa) +ds B )gs#)t A!) )ds C )gs#)t Ac) +ds D )gs#)t Ad) +ds C )t %. &or faster <MOS circuits( one would choose the following type of su!strate [ ] Aa) 11* Oriented n # type su!strate Ac) 111 Oriented p # type su!strate A!) 1** oriented p # type su!strate Ad) 111 oriented n# type su!strate .. $ull up to pull down ratio for n MOS in)erter dri)en !y another n MOS in)erter is [ ] Aa) 6E6 A!) 6E1 Ac) 1E6 Ad) -E1

6. The following de)ice is less li>ely to suffer latch up [ ] Aa)n MOS A!) 0MOS Ac) 120MOS Ad) $MOS 7. 2n 0MOS in)erter if FnBFp G if +tn B+tp( then the logic le)els are disposed a!out at a point where [ ] Aa)+2< B +out B *.1 +2< A! +2< B *.7 +,, Ac) +2< B +out B*.7 +,, Ad) +2< B +out B +,, 8. The figure of merit of MOS transistor can !e e9pressed as [ ] a) g m 0g !)

cg gm

c)

gm cg

d)

%
d) 6-* cm%H+.sec

:. Typical mo!ility of holes A1ul>) is a) 87*cm%H+.sec !) %6* cm%H+.sec

[ ] % c) 1%7* cm H+.sec

-. $ic>up the Itrue@ statement with respect to 1i#0MOS 2n)erter [ ] a) 5ow input impedance !) Jigh output impedance c) high noise margin d) 5ow dri)ing capa!ility =. To achie)e !est performance <MOS in)erter transfer characteristics( KpuHKpd ratio should !e a) Kero !) One c) 4s low as possi!le d) 4s high as possi!le [ ] 1*. <um!er of transistors to implement three#input 4<, gate using pass transistor logic is a) 8 !) . c) 7 d) = [ ] Fi** i! t3e b*+!4s: 11. 4n in)erter dri)en through one or more pass transistor should ha)e KpuHKpd ratio of;;;;;;;;;;;;;;;;; 1%. The threshold )oltage is increased due to ;;;;;;;;;;;;;;;;;;;; 1.. More lightly doped su!strate ;;;;;;;;;;;;;;;;;;;;;; will !e the !ody effect 16. The drain# source current A2,S) for <MOS under saturation can !e e9pressed as;;;;;;;;;;; 17. Transconductance of MOS transistor Ag m) is e9pressed as;;;;;;;;;; 18. &or de)ices of similar dimension n#channel is ;;;;;;;;;;; than the p channel 1:. 4 simple 120MOS in)erter has ;;;;;;;input impedance and;;;;;; output impedance 1-. The power dissipation is ;;;;;;;;;in 0MOS technology. 1=. 1i#0MOS in)erter has high dri)ing capa!ility than ;;;;;;;technology . %*. &or high performance 0MOS in)erter

n p

should !e;;;;;;;;

UNIT 7 8
Mu*ti2*e c3'ices 1. The color encoding for polysilicon is [ Aa) Led A!) 3reen Ac) 1lue Ad) Orange %. The color encoding of I+24@ in dou!le metal 0MOS p#well process [ a) Led !) 1lac> c) 1rown d) Mellow .. Metal 1 to metal 1 spacing in layout design is [ Aa) 6 A!) % Ac) . A d) 1 [ ] ] 6. The !uried contact is made !etween Aa) $oly to metal A!) poly to diff Ac) poly to diff using metal Ad) Metal to metal 7.2n <MOS layout design style( the colour of contact cut [ a) 1lac> !) 3reen c) 1lue d) Led ] ] ]

8. "hat is color of metal 1 A0MOS encoding) [ a) 1lac> !) 1lue c) Led d) Mellow :. The p#type transistors are placed a!o)e the [ a) $oly silicon !) diffusion c) ,emarcation line d) metal -. The minimum gap !etween diffusion and diffusion is [ a) % N !) 7 N c) : N d) 1* N =. The si/e of a transistor is usually designed in terms of [ a) ,rain !) source c) metal d) channel length 1*. 4ccording to %Om 0MOS technology( the minimum separation !etween contact cuts a) % Om !) 6 Om c) 8 Om d) 7 Om [

] ] ] ] ]

Fi** i! t3e b*+!4s 11. The layer preferred for glo!al distri!ution of power !uses is ;;;;;;;;;;;;;;;;;;;;;;;;; 1%.;;;;;;;;;;;;;;;;;;;;;;;; is used to con)ey layer information. 1.. &or 0MOS circuits stic> encodings for demarcation line is ;;;;;;;;;;;;;;;;;;;in color. 16. The power and ground lines often called ;;;;;;;;;;;;;;;;; 17. The minimum width of metal 1 layer is ;;;;;;;;;;;;;;;;;;;;;;; 18. 4 transistor is formed where)er polysilicon crosses ;;;;;;;;;;;;;;; 1:. Metal 1 for;;;;;;;;;;;; and metal % for ;;;;;;;;;of power lines in stic> notation 1-. The minimum polysilicon width is;;;;;;;;;;;;;;;;# 1=. 4s fa!rication technology impro)es( the heat sin> si/e;;;;;;;;;;;;; %*. 2n 0MOS design style( ,emarcation line is shown !y;;;;;;;;;;;;

UNIT 7 9
Mu*ti2*e c3'ice 1. $ower dissipation per unit area is scaled !y Aa) A!) Ac) Ad) d) *.191* % p&HOm% [ ] [ ]

%. Typical )alue of ,iffusion capacitorA0 area ) in 7 Om technology a) 1.*91* 6 p&HOm% !) 1.*P1* % p&HOm%B c) *.191* 6 p&HOm% .. The rise time of 0MOS in)erters is a) B A!) B Ac) B !) B

6. The typical )alue of load capacitance is a) 05 C 1* 6 cg A!) 05 1* 6 cg Ac) 05 B 1* 16 cg Ad) 05 1* 16

[ cg

7. The characteristics of a metal layer are [ ] a) 5ow LQ low 0 !) low LQ moderate 0 c) 5ow LQ moderate 0 d) moderate LQ high 0 8. The typical sheet resistance of polysilicon for 7Om is [ ] a) *#1* R !) 1*#16 R c) 1%* to 16*R d) 17 to 1** R :. The o)erall delay Td for n sections is gi)en !y [ ] % % % a) TdB nrc A ) !) TdB n rcA ) c) Td B n r cA ) d) TdB n r% cA ) -. ,eposition of the metalHsilicon alloy prior to sintering may !e done with [ ] a) Sputtering !) diffusion c) 2mplantation d) Metalli/ation =. "hat is the formula for Lise#time estimation [ ] a) TrB

p V DD

.C

!) Tr B

.C v
p

c) Tr B

.C

DD

p V DD %

d) Tr B

C V DD
L p

1*. The formula for fall#time estimation in 0MOS in)erter is

a) Tf B

.C

p V DD

!) Tf B

.C v
p

% L

c) Tf B

.C

DD

n V DD

.C d) V DD %
L n

Fi** i! t3e b*+!4s 11. The propagation delay of n sections is gi)en !y ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1%. The layer in which metal is deposited on poly silicon is called ;;;;;;;;;;;;;;;;;;;;; 1.. The sheet resistance of pdiff is ;;;;;;;;;;;;;; times that of n#diffusion. 16. The )alues for <#diffusion region are;;;;;;;;;; times the $#diffusion regions. 17. 1i#0MOS technology is reasona!ly good for;;;;;;;;;;;;;; 18. $ower consumption in 0MOS circuits depends on ;;;;;;;;;;;;;;;at which they operate. 1:. ;;;;;;;; layer is suita!le for routing + dd or +ss 1-. The ;;;;;;;;;;;;;;;;;;;;;load can@t !e dri)en !y a single in)erter. 1=. 2n 1i#$olar transistor collector current depends ;;;;;;;;;;;;;;;;on + !e. %*. The ,elay for 1i#0MOS in)erter is ;;;;;;;;;;;;;;;;;;;!y a factor of h f e compared with a 0MOS 2n)erter.

UNIT0V
Mu*ti2*e c3'ice 1. The heart of the 45? is [ ] a. Legister !. 4dder c. 0ontrol !us d. 2HO port %. 2n the comparator the two inputs if 4D1 then the outputs are [ ] a. 0iB* G ,iB1 !. 0iB1 G ,iB* c. 0iB1 G ,iB1 d. 0iB* G ,iB* .. &or a four !it word( a one#!it shift right is eSui)alent to a [ ] a. two !it shift left !. Three#!it shift left c. one !it shift left d. &our#!it shift left 6. The type of switch used in shifters is [ ] a. line switch !. Transistor type switch c. cross!ar switch d. 3ate switch 7. ,etecting all ones or all /eros on wide words reSuire [ ] a. large fan out 4<, or OL gates !. 5arge fan in 4<, or OL gates c. large fan in 'P#<OL or 'P#OL gates d. 5arge fan out <OL or <4<, gates 8. "hat is the sum of a full adder of two !its 4 and 1 with carry in of 0 [ ] a) S B 01A4 T 1 T 0) T 410 !) S B 41 T 10 T 04 c) S B 41 11 T 11 01 T 01 41 d) S B 0A4 T 1 T 0) T 410 :. Jow is the regularity of 0arry generate structures in 0arry 5oo> ahead addersU [ ] a) +ery high !) high c) medium d) poor -. "hat is the ad)antage of "allace tree multiplierU [ ] a) Leduces delay and area !) Leduction of area and comple9ity c) 2mpro)ed accuracy d) 2mpro)ed accuracy and delay =. 1augh "oolley method can !e used for multiplication ofVV. [ ] a) ?nsigned !inary num!ers !) Signed !inary num!ers c) Signed !inary data d) ?nsigned decimal num!ers 1*. Total time for multiplication of n !its in "allace compression techniSue is proportional to [ ] % a) n !) n c) 2n n d) log % n Fi** i! t3e b*+!4s 11. The standard cell for an n#!it parity generator is;;;;;;;;;;;;;;;;;;;;;;;;;; 1%. The following memory e9amines data word and compares this data with internally stored data is a ;;;;;;;;;;;;;;;;;;;;;;;;;;; 1.. ,L4M reSuires ;;;;;;;;;;;;;;;;;;;of data periodically

16. 0arry select adder selects the appropriate sum from two adders which ha)e input carriers of;;;;;;;;;;;;;;;;;;; 17. 1arrel shifter is a;;;;;;;;;;;;;;;; 18. $arity generator made with ;;;;;;;;; gates 1:. The cloc>ing of each stage of ripple counter is carried out !y the ;;;;;;;;;;;;;;;;stage. 1- SL4M contains ;;;;;;;;;; transistors 1=. Modified 1ooth encoding reduces the num!er of cells !y;;;;;;;;;;; %*. ;;;;;;;;;;;;;;;utili/es the Ladi9 6 num!er system to reduce the area and total time for multipliers.

UNIT0VI
Mu*ti2*e c3'ice 1. The $54 pro)ides a systematic and regular way of implementing multiple output functions of n )aria!les in [ ] a. $OS form !. SO$ form c. comple9 form d. Simple form %. 4 single time programma!le &$34 is the type of [ ] a. &use#!ased &$34 !. SL4M#&$34 c. '$LOM#&$34 d. &lash !ased &$34 .. 2n the standard cell( all the cells should ha)e [ ] a. identical heights and widths !. identical heights and the widths of the cells may )ary c. identical widths and the )aria!le heights d. )aria!le heights and widths 6. Semi custom design using standard cells ena!le the designs to use [ ] a. a functional modules Aa)aila!le in li!rary) !. a layout automatically generated c. an interconnections !etween cells d. Only !asic logic functions 7. $rogramma!le array logic pro)ides a con)enient way of reali/ing [ ] a. com!inational networ>s only !. SeSuential networ>s only c. !oth com!inational and seSuential networ> d. not used for reali/ation 8.% 6 M?P is repeated 7** times in a chip containing -*** transistors. "hat is the regularityU a) 18 !) .% c) 86 d) =8 [ ] :. "hat is the resistance of 4nti fuse !efore programmingU [ ] a) 1** M ohm !) 1* Mega ohms c) 1 Meg ohm d) 1** ohm -. "hat is the !asis for Standard cell or cell !ased designs a)aila!le in cell li!raryU[ ] a) Standardi/ation at functional le)el !) Standardi/ation at structural le)el c) Standardi/ation at physical le)el d) Leprogramma!le structures =. "hich of the following is I,i)ide and conSuer strategy@ in 0MOS designU [ ] a) Jierarchy !) Legularity c) Modularity d) 5ocality 1*. "hich of the following is I"ires first and modules ne9t@ strategyU [ ] a) Jierarchy !) Legularity c) Modularity d) 5ocality Fi** i! t3e b*+!4s 11. $rogramma!le array logic is made up of;;;;;;;;;;;;;;;;;;;;;;;; 1%. 5ogic gates are placed in rows of standard cells are interconnected using;;;;;;;;;;;;;; 1.. Semi custom design using standard cells ena!le the designers to use ;;;;;;;;;;;;;;;;;; 16. &ull custom designs are;;;;;;;;;;;;;;;;;;used at this time. 17. $rocessing time is least in Sea of 3ate due to the;;;;;;;;;;;;;;;;;;;;;;; 18.Standard cell design pro)ides an area ad)antage o)er gate array design at the cost of;;;;;;;;;;;;;;;;;;;;;;;;.

1:. $45%%+1*( here + denotes the;;;;;;;;;;;;;;; 1-. $45 has ;;;;;;;;;; OL array logic and ;;;;;;;;;; 4<, array logic 1=. ;;;;;;;;;;;;;;;;;is !ased on chips with programma!le logic structures( interconnect logic or reprogramma!le gate array logic. %*. ;;;;;;;;;;;;;;;;;use floating gate structure interposed !etween the regular MOS transistor gate and the channel.

UNIT:VII
Mu*ti2*e c3'ice 1. The primary a!straction in +J,5 is called [ ] a. interface description !. 1ody description c. structural description d. ,esign entity %. The design is commenced with a [ ] a. LT5 description !. 1eha)ioral description c. logic description d. &unctional description .. 5ogic optimi/ation is used to impro)e the logic to mean [ ] a. logic constraints !. Timing or area constraints c. power constraints d. $arasitic constraints 6. "hich of the following synthesis con)erts LT5 description to a set of registers and com!inational logic [ ] a. !eha)ioral synthesis !. LT5 synthesis c. logic le)el synthesis d. 5ayout synthesis 7. The case operator of +J,5 indicates the [ ] a. counters !. 5ogic gate c. multiple9er d. 0loc>ed register 8. <ame the step that results in data !ase suita!le for manufacture [ ] a) Mas> generation !) $attern generation c) 5ayer generation d) 5ayout generation :. "hat is the process of arrangement of !loc>s in a chip to minimi/e area and ma9imi/e speedU a) 1ac> annotation !) Louting [ ] c) Timing )erification d) &loor planning -. "hat are the operations specified !y the 1eha)ioral code fragment a B a T ! W cU [ ] a) 4ccumulate and multiply !) Multiply and accumulate c) 2terate and multiply d) 0ompare and multiply =. Jow is the propagation delay specified in a +J,5 statementU [ ] a) c CB 4 and 1 after 7 ns !) c B 4 and 1 after 7 ns c) c C 4 and 1 after 7 ns d) c DB 4 and 1 after 7 ns 1*. "hat is the characteristic eSuation for a K &lip#&lopU [ ] T 1 1 T T 1 T 1 1 1 1 a) X B X T K X !) X B X T KX c) X B X T K X d) X B X T K X Fi** i! t3e b*+!4s 11. The most detailed and accurate simulation techniSue is;;; ;;;;;;;;;;; 1%. Switch # le)el simulators are com!ination of; ;;;;;;;;;;;;;;;;;;;; 1.. 4 layout editor might interface to a design rule chec>ing program to allow interacti)e chec>ing of;;;;; ;;;;;;;;;;;;;;;;; 16.LS2M is an e9ample of ;;;;;;;;;;;;;;;le)el simulator. 17. ;;;;;;;;;;;;;;;;;;;;;.e9amines the interrelationship of mas> layers to infer the e9istence of transistors and other components. 18. The characteristic eSuation for a , &lip#&lop ;;;;;;;; 1:. ;;;;;;;;;;;;;;pro)ide graphical feed !ac> a!out si/e and placement of modules 1-. 4 design#rule#chec>er is used to )erify the ;;;;;;;;;;;;; 1=. ;;;;;;;;;;;;;simulators merge the good points of all the simulators. %*. ;;;;;;;;;;;;;;;are menu !ased graphic editors.

UNIT0VIII
Mu*ti2*e c3'ice 1. Manufacturing tests are used to )erify that [ ] a. function of a chip as a whole !. e)ery gate operates as e9pected c. function in the field d. the cloc> response of the chip %. +J,5 and +erilog hardware description languages are used for [ ] a. manufacturing tests !. &unctionality test c. ,esign testing d. 0hip testing .. &unctionality tests see> to )erify the [ ] a. function of a chip as a whole !. ')ery gate operates as e9pected c. function in the field d. The cloc> response of the chip 6. The two >ey concepts underlying all considerations for testa!ility are [ ] a. set and reset !. 0ontrolla!ility and o!ser)a!ility c. initial and final conditions d. $ads and lin>s 7. The faults occur due to thin#o9ide shorts or metal#to metal shorts are called [ ] a. stuc> at /ero faults !. Short#circuit faults c. open#circuit faults d. 1ridge faults 8. "hat is the num!er of input seSuences reSuired to test com!inational circuit with In@ inputsU [ ] n1 n a) n !) n 1 c) % d) % :. "hich of the following are most often tested !y 12STU [ ] a) ,ata path !) 2HOs c) 0ontrol circuits d) Memory -. "hat is the testing techniSue more suited for ,ata pathU [ ] a) 12ST !) 1oundary scan c) $arallel scan d) 2,,X =. "hich of the following test procedure uses $LS3 Apseudo random signal generator)U [ ] a) 1oundary scan !) $arallel scan c) 1251O d) 2,,X 1*. The principle used in 2,,X testing [ ] a) < MOS gates draw current in Suiescent state !) $ MOS gates draw current in Suiescent state c) 0 MOS gates do not draw current in Suiescent state d) 2t is a controlla!ility test Fi** i! t3e b*+!4s 11. Landom logic is pro!a!ly !est tested )ia;;;;;;;;;;;;;;;;;;;;;; ;; 1%. 3enerally memories are tested !y ;;;;;;;;;;;;;;; ;;;;;;;;;;;; 1.. 2n the structured testing techniSue( 5SS, means ;;;;;;;;;;;;;;;;;;;;;;;; 16.;;;;;;;;;;;;;;;;;fault occurs when two unconnected signal lines ate shorted together. 17. 2f the normal )alue has changed from 1 to *( the fault is >nown as ;;;;;;;;;;;; 18. 12ST stands for ;;;;;;;;;; 1:. 5&SL used to generate;;;;;;;;;;;;;;; seSuence 1-. The type of a fault should not distur! the functionality of the circuit is;;;;;;;;;;. 1=. Outputs of the flip flops in the state register are shifted out !it !y !it using a single serial output pin of 20 in;;;;;;;;;;;;;;;;;;;. %*. TLST signal in !oundary scan resets the;;;;;;;;;;;;;;;;.