MF5 Universal Monolithic Switched Capacitor Filter

February 1995

MF5 Universal Monolithic Switched Capacitor Filter

General Description
The MF5 consists of an extremely easy to use general purpose CMOS active filter building block and an uncommitted op amp The filter building block together with an external clock and a few resistors can produce various second order functions The filter building block has 3 output pins One of the output pins can be configured to perform highpass allpass or notch functions and the remaining 2 output pins perform bandpass and lowpass functions The center frequency of the filter can be directly dependent on the clock frequency or it can depend on both clock frequency and external resistor ratios The uncommitted op amp can be used for cascading purposes for obtaining additional allpass and notch functions or for various other applications Higher order filter functions can be obtained by cascading several MF5s or by using the MF5 in conjuction with the MF10 (dual switched capacitor filter building block) The MF5 is functionally compatible with the MF10 Any of the classical filter configurations (such as Butterworth Bessel Cauer and Chebyshev) can be formed

Features
Y Y

Y Y Y

Y Y

Y Y Y

Low cost 14-pin DIP or 14-pin Surface Mount (SO) wide-body package Easy to use Clock to center frequency ratio accuracy g 06% Filter cutoff frequency stability directly dependent on external clock quality Low sensitivity to external component variations Separate highpass (or notch or allpass) bandpass lowpass outputs fo c Q range up to 200 kHz Operation up to 30 kHz (typical) Additional uncommitted op-amp

Block and Connection Diagrams

TLH5066 1

All Packages

Order Number MF5CN See NS Package Number N14A Order Number MF5CWM See NS Package Number M14B

Top View

TLH5066 2

C1995 National Semiconductor Corporation

TLH5066

RRD-B30M115Printed in U S A

Absolute Maximum Ratings

If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications Supply Voltage (V a b V b ) 14V Power Dissipation TA e 25 C (note 1) Storage Temp Soldering Information N Package 10 sec SO Package Vapor phase (60 sec) Infrared (15 sec) 500 mW 150 C 260 C 215 C 220 C See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices Input Voltage (any pin) Vb s Vin s V a Operating Temp Range MF5CN MF5CWM TMIN s TA s TMAX 0C s TA s 70 C

Electrical Characteristics Va e 5V g 05% Vb e b5V g 05% unless otherwise noted Boldface limits
apply over temperature TMIN s TA s TMAX For all other limits TA e 25 C Parameter Supply Voltage (V a b V b ) Maximum Supply Current Clock Feedthrough Filter Output Op-amp Output Min Max Clock applied to Pin 8 No Input Signal 45 10 10 60 Conditions Typical (Note 6) Tested Limit (Note 7) Design Limit (Note 8) 8 14 Units V V mA mV mV

Filter Electrical Characteristics V a e 5V g 05% Vb e b5Vg 05% unless otherwise noted Boldface
limits apply over temperature TMIN s TA s TMAX For all other limits TA e 25 C Parameter Center Frequency Range (fo) Clock Frequency Range (fCLK) Clock to Center Frequency Ratio (fCLKfo) fCLKfo Temp Coefficient Max Min Max Min Ideal Q e 10 Mode 1 Vpin9 e a 5V FCLK e 250 kHz Vpin9 e b 5V FCLK e 500 kHz Conditions Typical (Note 6) 30 01 15 50 5011 g 02% 10004 g 02%
g 10 g 20 g 10 g 10

Tested Limit (Note 7)

Design Limit (Note 8) 20 02 10 10

Units kHz Hz MHz Hz

5011 g 15% 10004 g 15% ppm C ppm C % % ppm C ppm C

g 02

Vpin9 e a 5V (501 CLK ratio) Vpin9 e b 5V (1001 CLK ratio)

Q Accuracy (Max) (Note 2)

Ideal Q e 10 Mode 1

Vpin9 e a 5V FCLK e 250 kHz Vpin9 e b 5V FCLK e 500 kHz

b200 b70

Q Temperature Coefficient

Vpin9 e a 5V (501 CLK ratio) Vpin9 e b 5V (1001 CLK ratio)

DC Lowpass Gain Accuracy (Max) DC Offset Voltage (Max) Vos1 Vos2 Vos3 (Note 3) Vos2 Vos3

Mode 1 R1 e R2 e 10 kX
g 5 0

dB mV mV mV mV mV

Vpin9 e a 5V (501 CLK ratio) Vpin9 e b 5V (1001 CLK ratio) 2

b185 a 115 b310 a 240

Filter Electrical Characteristics Va e 5Vg 05% Vb e b5Vg 05% unless otherwise noted Boldface
limits apply over temperature TMIN s TA s TMAX For all other limits TA e 25C (Continued) Parameter Output Swing (Min) Dynamic Range (Note 4) Maximum Output Short Circuit Current (Note 5) Source Sink BP LP pins NAPHP pin Conditions RL e 5 kX RL e 35 k X Vpin9 e a 5V (501 CLK ratio) Vpin9 e b 5V (1001 CLK ratio) Typical (Note 6)
g 4 0 g 4 2

Tested Limit (Note 7)

g 38 g 38

Design Limit (Note 8)

Units V V dB dB mA mA

83 80 20 30

OP-AMP Electrical Characteristics V a e a5V g 05% Vb e b5V g05% unless other noted Boldface limits apply over temperature TMIN s TA s TMAX For all other limits TA e 25 C Parameter Gain Bandwidth Product Output Voltage Swing (Min) Slew Rate DC Open-Loop Gain Input Offset Voltage (Max) Input Bias Current Maximum Output Short Circuit Current (Note 5) Source Sink RL e 35 kX Conditions Typical (Note 6) 25
g 4 2 g 3 8

Tested Limit (Note 7)

Design Limit (Note 8)

Units MHz V V m s db

70 80
g 5 0 g 20

mV pA mA mA

10 20 30

Logic Input Characteristics Boldface limits apply over temperature TMIN s TA s TMAX
All other limits TA e 25 C Parameter CMOS Clock Input Min Logical 1 Input Voltage Max Logical 0 Input Voltage Min Logical 1 Input Voltage Max Logical 0 Input Voltage TTL Clock Input Min Logical 1 Input Voltage Max Logical 0 Input Voltage Conditions Typical (Note 6) Tested Limit (Note 7) 30
b 30

Design Limit (Note 8)

Units V V V V V V

V a e a 5V V b e b 5V VLSh e 0V V a e a 10V V b e 0V VLSh e a 5V V a e a 5V V b e b 5V VLSh e 0V

80 20 20 08

Note 1 The typical junction-to-ambient thermal resistance (iJA) of the 14 pin N package is 160 CW and 82 CW for the M package Note 2 The accuracy of the Q value is a function of the center frequency (fo) This is illustrated in the curves under the heading Typical Performance Characteristics Note 3 Vos1 Vos2 and Vos3 refer to the internal offsets as discussed in the Application Information section 34 Note 4 For g 5V supplies the dynamic range is referenced to 282V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 m V rms for the MF5 with a 501 CLK ratio and 280 m V rms for the MF5 with a 1001 CLK ratio Note 5 The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply These are the worst case conditions Note 6 Typicals are at 25 C and represent most likely parametric norm Note 7 Guaranteed and 100% tested Note 8 Guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels

Pin Description
LP(14) BP(1) NAPHP(2) The second order lowpass bandpass and notchallpasshighpass outputs The LP and BP outputs can typically sink 1 mA and source 3 mA The NAPHP output can typically sink 15 mA and source 3 mA Each output typically swings to within 1V of each supply The inverting input of the summing op amp of the filter This is a high impedance input but the non-inverting input is internally tied to AGND making INV1 behave like a summing junction (low impedance current input) S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5) The pin should be driven with a source impedance of less than 1 kX If S1 is not driven with a signal it should be tied to AGND (mid-supply) This pin activates a switch that connects one of the inputs of the filters second summer to either AGND (SA tied to Vb ) or to the lowpass (LP) output (SA tied to V a ) This offers the flexibility needed for configuring the filter in its various modes of operation This pin is used to set the internal clock to center frequency ratio (fCLKfo) of the filter By tying the pin to V a an fCLKfo ratio of about 501 (typically 5011 g 02%) is obtained Tying the 50100 pin to either AGND or Vb will set the fCLKfo ratio to about 1001 (typically 10004 g 02%) This is the analog ground pin This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation For a further discussion of mid-supply biasing techniques see the Applications Information (Section 32) For optimum filter performance a clean ground must be provided

V a (6) V b (10)

CLK(8)

INV1(3)

S1(4)

L Sh(7)

SA(5)

50100(9)

INV2(12)

AGND(11)

Vo2(13)

These are the positive and negative supply pins The MF5 will operate over a total supply range of 8V to 14V Decoupling the supply pins with 01 mF capacitors is highly recommended This is the clock input for the filter CMOS or TTL logic level clocks can be accomodated by setting the L Sh pin to the levels described in the L Sh pin description For optimum filter performance a 50% duty cycle clock is recommended for clock frequencies greater than 200 kHz This gives each op amp the maximum amount of time to settle to a new sampled input This pin allows the MF5 to accommodate either CMOS or TTL logic level clocks For dual supply operation (ie g 5V) a CMOS or TTL logic level clock can be accepted if the L Sh pin is tied to mid-supply (AGND) which should be the system ground For single supply operation the L Sh pin should be tied to mid-supply (AGND) for a CMOS logic level clock The mid-supply bias should be a very low impedance node See Applications Information for biasing techniques For a TTL logic level clock the L Sh pin should be tied to V b which should be the system ground This is the inverting input of the uncommitted op amp This is a very high impedance input but the non-inverting input is internally tied to AGND making INV2 behave like a summing junction (low-impedance current input) This is the output of the uncommitted op amp It will typically sink 15 mA and source 30 mA It will typically swing to within 1V of each supply

Typical Performance Characteristics

Deviation of FCLK Fo vs Nominal Q Deviation of FCLK Fo vs Nominal Q OPAMP Output Voltage Swing vs Temperature

TLH5066 3

Typical Performance Characteristics (Continued)

Supply Current vs Temperature

observed as the frequency of a notch at the allpass output (Figure 10 ) Q quality factor of the 2nd order filter Q is measured at the bandpass output of the MF5 and is equal to fo divided by the b 3dB bandwidth of the 2nd order bandpass filter (Figure 1 ) The value of Q determines the shape of the 2nd order filter responses as shown in Figure 6 Qz the quality factor of the second order complex zero pair if any Qz is related to the allpass characteristic which is written HOAP HAP(s) e s2 b s0 o a 0o2 Qz

s0o a 0o2 s2 a Q

TLH5066 4

10 Definitions of Terms
fCLK the frequency of the external clock signal applied to pin 8 fo center frequency of the second order function complex pole pair fo is measured at the bandpass output of the MF5 and is the frequency of maximum bandpass gain (Figure 1 ) fnotch the frequency of minimum (ideally zero) gain at the notch output fz the center frequency of the second order complex zero pair if any If fz is different from fo and if Qz is high it can be

where Qz e Q for an all-pass response HOBP the gain (in VV) of the bandpass output at f e fo HOLP the gain (in VV) of the lowpass output as f x 0 Hz (Figure 2 ) HOHP the gain (in VV) of the highpass output as f x fclk2 (Figure 3 ) HON the gain (in VV) of the notch output as f x 0 Hz and as f x fclk2 when the notch filter has equal gain above and below the center frequency (Figure 4 ) When the lowfrequency gain differs from the high-frequency gain as in modes 2 and 3a (Figures 11 and 8 ) the two quantities below are used in place of HON HON1 the gain (in VV) of the notch output as f x 0 Hz HON2 the gain (in VV) of the notch output as f x fclk2
0o s HOBP Q s0o 2 a 0 o2 s a Q
fo e 0fLfH
a

HBP(s) e

Qe

fo fH b fL
b1

fL e fo

2Q

(a)

5066 5

(b)

5066 6

fH e fo

1 a 2Q

0 2Q J 1 J 1 0 2Q J 1 J
2

0 o e 2qfo

FIGURE 1 2nd-Order Bandpass Response

HLP(s) e s2 a fc e fo c fp e fo HOLP0 o2 s0 o a 0 o2 Q
b

01 1 01 2Q
b

1 2Q2

J 0
1 4Q2

1b

1 2 a1 2Q2

(a)

TL H 5066 7

(b)

HOP e HOLP c
TL H5066 8

1 1 Q

1b

FIGURE 2 2nd-Order Low-Pass Response

HHP(s) e HOHPs2 s0o a 0o2 Q
b1

s2 a

fc e fo c fp e fo c

0
0

1b 1b

1 2Q2 1 2Q2

J0 (
b1

1b

1 2Q2

a1

(a)

066 9

(b)

5066 10

HOP e HOHP c

1 1 Q

FIGURE 3 2nd-Order High-Pass Response 5

1b

1 4Q2

10 Definition of Terms (Continued)

HN(s) e

HON(s2 a 0o2) s0 o a 0 o2 s2 a Q fo e 0fLfH

a

Qe

fo fH b fL
b1

fL e fo fH e fo
TLH5066 11 TLH5066 12

2Q

1 a 2Q

0 2Q J 1 J 1 0 2Q J 1 J
2

(a) FIGURE 4 2nd-Order Notch Response

(b)

HOAP HAP(s) e

s2 b

s0 o a 0 o2 Q

s2 a

s0 o a 0 o2 Q

TLH5066 13

TLH5066 14

(a)

(b)

FIGURE 5 2nd-Order All-Pass Response

(a) Bandpass

(b) Low-Pass

(c) High-Pass

(d) Notch

(e) All-Pass

TLH5066 15

FIGURE 6 Responses of various 2nd-order filters as a function of Q Gains and center frequencies are normalized to unity 6

20 Modes of Operation
The MF5 is a switched capacitor (sampled data) filter To fully describe its transfer functions a time domain approach is appropriate Since this is cumbersome and since the MF5 closely approximates continuous filters the following discussion is based on the well known frequency domain Each MF5 can produce a full 2nd order function See Table 1 for a summary of the characteristics of the various modes MODE 1 Notch 1 Bandpass Lowpass Outputs fnotch e fo (See Figure 7 ) fo
e center frequency of the complex pole pair

fo R3 e BW R2

BW e the b 3 dB bandwidth of the bandpass output Circuit dynamics HOBP or HOBP e HOLP c Q e HON c Q Q HOLP(peak) j Q c HOLP (for high Qs) HOLP e MODE 1a Non-Inverting BP LP (See Figure 8 ) f f e CLK or CLK fo 100 50 R3 e Q R2 HOLP e b 1 HOLP(peak) j Q c HOLP (for high Qs) R3 HOBP1 e b R2 HOBP2 e 1 (non-inverting)

100 50 fnotch e center frequency of the imaginary zero pair e fo R2 R1 R3 HOBP e Bandpass gain (at f e fo) e b R1 HOLP e Lowpass gain (as f x 0) e b HON e Notch output gain as f f

f f e CLK or CLK

x x

0 fCLK2

b R2

R1

Circuit dynamics HOBP1 e Q Note VIN should be driven from a low impedance (k 1 kX)

TLH5066 16

FIGURE 7 MODE 1

TLH5066 17

FIGURE 8 MODE 1a

20 Modes of Operation (Continued)

MODE 2 Notch 2 Bandpass Lowpass fnotch k fo (See Figure 9 ) fo
e center frequency

MODE 3 Highpass Bandpass Lowpass Outputs (See Figure 10 ) fo f e CLK c 100

f e CLK fnotch Q

100 R4 fCLK fCLK e or 100 50

R2

f a 1 or CLK 50

0R4

R2

a1

e quality factor of the complex pole pair e

0R4 or 50 0R4
c

R2

fCLK

R2

R2R3 HOLP e Lowpass output gain (as f

e b

e quality factor of the complex pole pair 0R2R4 a 1 e

0R4

R2

R3 R2 as f x fCLK 2

HOHP e Highpass gain

eb

R2 R1

0)

HOBP e Bandpass gain (at f e fo) e b HOLP e Lowpass gain (as f

R2R1 R2R4 a 1

HOBP e Bandpass output gain (at f e fo) e b R3R1 HON1 e Notch output gain (as f x 0)
e b

R2R1 R2R4 a 1 as f

R1 R2 HOHP e e Circuit dynamics HOBP 0HOHP c HOLP c Q R4 HOLP HOLP(peak) j Q c HOLP (for high Qs) HOHP(peak) j Q c HOHP (for high Qs)

0) e b

R3 R1 R4

HON2 e Notch output gain

fCLK 2

Filter dynamics HOBP e Q 0HOLP HON2 e Q 0HON1 HON2

e b R2R1

TLH5066 18

FIGURE 9 MODE 2

In Mode 3 the feedback loop is closed around the input summing amplifier the finite GBW product of this op amp causes a slight Q enhancement If this is a problem connect a small capacitor (10 pF 100 pF) across R4 to provide some phase lead

TLH5066 19

FIGURE 10 MODE 3

20 Modes of Operation (Continued)

MODE 3a HP BP LP and Notch with External Op amp (See Figure 11 ) f R2 fCLK R2 e CLK c c fo or 100 R4 50 R4 R2 R3 e c Q R4 R2 MODE 4 Allpass Bandpass Lowpass Outputs (See Figure 12 ) e center frequency fo f f e CLK or CLK 100 50 f z e center frequency of the complex zero pair j fo fo R3 e BW R2 Qz e quality factor of complex zero pair e For AP output make R1 e R2 Rh fCLK or Rl 50 Rh Rl HOAP e Allpass gain at 0 k f k fCLK 2 0) R3 R1

HOHP e b HOBP e b HOLP e b fn Hon Hn1 Hn2

R2 R1 R3 R1 R4 R1 100

f e notch frequency e CLK

e gain of notch at f e fo e Q e gain of notch (as f e gain of notch

Rg Rg HOLPb HOHP Rl Rh

HOLP e Lowpass gain (as f x R2 e b a 1 e b2 R1

eb

R2 e b1 R1

Rg c HOLP 0) e Rl fCLK 2

as f x

eb

Rg c HOHP Rh

HOBP e Bandpass gain (at f e fo) R3 R2 R3 e b e b2 1a R2 R1 R2 Circuit dynamics HOBP e (HOLP) c Q e (HOAP a 1) Q

Due to the sampled data nature of the filter a slight mismatch of fz and fo occurs causing a 04 dB peaking around fo of the allpass filter amplitude response (which theoretically should be a straight line) If this is unacceptable Mode 5 is recommended

TLH5066 20

FIGURE 11 MODE 3a

TLH5066 21

FIGURE 12 MODE 4

20 Modes of Operation (Continued)

MODE 5 Numerator Complex Zeros BP LP (See Figure 13 ) R2 fCLK R2 fCLK e c c fo 1a or 1 a R4 100 R4 50 R1 fCLK R1 fCLK e b c b c fz 1 or 1 R4 100 R4 50 MODE 6a Single Pole HP LP Filter (See Figure 14 ) e cutoff frequency of LP or HP output fc
e

0 0

0 0

R2 fCLK R2 fCLK or R3 100 R3 50

Q Qz H0z1 H0z2

e 01 a R2R4 c e 01 b R1R4 c

R3 R2 R3 R1

R3 R1 R2 HOHP e b R1 HOLP e b

e gain at CZ output (as f e gain at CZ output

0 Hz) e fCLK 2

b R2 (R4b R1)

R1 (R4 a R2)
e b R2

MODE 6b Single Pole LP Filter (Inverting and NonInverting) (See Figure 15 ) e cutoff frequency of LP outputs fc R2 fCLK R2 fCLK or R3 100 R3 50 HOLP1 e 1 (non-inverting) R3 HOLP2 e b R2 j

as f x

R1

HOBP eb e HOLP eb

R2 a1 R1

R2 a R2 a

J R1 R4 J

R3 R2

R4 R1

TLH5066 22

FIGURE 13 MODE 5

TLH5066 23

FIGURE 14 MODE 6a

TLH5066 24

FIGURE 15 MODE 6b 10

20 Modes of Operation (Continued)

TABLE I Summary of Modes Realizable filter types (eg low-pass) denoted by asterisks Unless otherwise noted gains of various filter outputs are inverting and adjustable by resistor ratios Mode 1 1a BP LP HP N AP Number of resistors 3 2 Adjustable fCLKfo No No Yes (above fCLK50 or fCLK100) Yes Universal StateVariable Filter Best general-purpose mode As above but also includes resistortuneable notch Gives Allpass response with HOAP e b 1 and HOLP e b2 Gives flatter allpass response than above if R1 e R2 e 002R4 Single pole Single pole May need input buffer Poor dynamics for high Q Notes

(2) HOBP1 e bQ HOBP2 e a 1

HOLP e a 1

(2) HOLP e a 1 bR3 HOLP2 e R2

3a

Yes

No

5 6a 6b

4 3 2

30 Applications Information
The MF5 is a general-purpose second-order state variable filter whose center frequency is proportional to the frequency of the square wave applied to the clock input (fCLK) By connecting pin 9 to the appropriate DC voltage the filter center frequency fo can be made equal to either fCLK100 or fCLK50 fo can be very accurately set (within g 06%) by using a crystal clock oscillator or can be easily varied over a wide frequency range by adjusting the clock frequency If desired the fCLKfo ratio can be altered by external resistors as in Figures 9 10 11 13 14 and 15 The filter Q and gain are determined by external resistors All of the five second-order filter types can be built using the MF5 These are illustrated in Figures 1 through 5 along with their transfer functions and some related equations Figure 6 shows the effect of Q on the shapes of these curves When filter orders greater than two are desired two or more MF5s can be cascaded The MF5 also includes an uncommitted CMOS operational amplifier for additional signal processing applications 31 DESIGN EXAMPLE An example will help illustrate the MF5 design procedure For the example we will design a 2nd order Butterworth low-pass filter with a cutoff frequency of 200 Hz and a passband gain of b 2 The circuit will operate from a g 5V power supply and the clock amplitude will be g 5v (CMOS) levels) 11 From the specifications the filter parameters are fo e 200 Hz HOLP eb 2 and for Butterworth response Q e 0707 In section 20 are several modes of operation for the MF5 each having different characteristics Some allow adjustment of fCLKfo others produce different combinations of filter types some are inverting while others are non-inverting etc These characteristics are summarized in Table I To keep the example simple we will use mode 1 which has notch bandpass and lowpass outputs and inverts the signal polarity Three external resistors determine the filters Q and gain From the equations accompanying Figure 7 Q e R3R2 and the passband gain HOLP e bR2R1 Since the input signal is driving a summing junction through R1 the input impedance will be equal to R1 Start by choosing a value for R1 10k is convenient and gives a reasonable input impedance For HOLP e b 2 we have R2 e b R1HOLP e 10k c 2 e 20k For Q e 0707 we have R3 e R2Q e 20k c 0707 e 1414k Use 15k For operation on g 5V supplies V a is connected to a 5V Vb to b 5V and AGND to ground The power supplies should be clean (regulated supplies are preferred) and 01 mF bypass capacitors are recommended

30 Applications Information (Continued)

TLH5066 25

FIGURE 16 2nd-Order Butterworth Low-Pass Filter of Design fCLK e 50 Connect Pin 9 to a 5V and Example For f0 Change Clock Frequency to 10 kHz

TLH5066 26

FIGURE 17 Butterworth Low-Pass Circuit of Example but Designed for Single-Supply Operation

12