Electronics III

- Power Dissipation in CMOS digital circuits Optimization at o o of C Chain a o of Inverters e te s - Opt

CMOS Power Dissipation

Trade offs Power Timing g Area
CMOS p power includes static and dynamic y components p

P = I DD VDD Ptotal = Pstatic + Pdynamic

CMOS Dynamic Power Dissipation

Dynamic Switching Currents
1. Dynamic Capacitive charging current
Pavg Pavg 1 = T

v(t ) i(t )dt

0

dVout Vout C L dt dt 0 T /2 2 2 Vout C L V 0 DD V out V DD Vout |0 |VDD Pavg = 2 T VDD 2 1 + 2 2 Pavg = C LV DD = C LV DD f clk = V DD I D , avg T + PU C L Vswing dV PD Vout I D , avg = C L = = C LV DD f clk lk dt t

1 = T

T /2

(VDD

dV out Vout ) + C L dt + dt

V + out -

Iswitch design factors Reduce CL Vswing VDD fclk

Pull up: t= 0 T/2 Vout =0 VDD

Pull down: t = T/2 T Vout = VDD 0

CMOS Dynamic Power Dissipation

Switching Activity Factor
Activity factor
HOWEVER Most gates do not switch (toggle) at each clock edge
2 Pdynamic = C LV DD f 0 1

Pdynamic = 01 CL VDD2 fclk

Where 0 1 is the activity factor

CMOS Dynamic Power Dissipation

Switching Activity Factor
Activity factor
= probability that an output transition 0 1 takes place
= p0p1 p0 = probability output = 0 p1 = probability output switches to 1

Determined from to truth table of specific gate Assuming equal probability for each combination of input
Example: 2 input NOR/NANDgates A 0 0 1 1 B 0 1 0 1 A+B 1 0 0 0 A.B 1 1 1 0

NOR2: p0=3/4, p1=1/4, = 3/16 NAND2: p0=1/4, , p1=3/4, , = 3/16

CMOS Dynamic Power Dissipation

Switching Activity Factor
Activity factor
Assuming equal probability for each input combination
E Example: l 2 input i t XOR gate: t p0=0.5, p1=0.5 = 0.25
A 0 0 1 1 B 0 1 0 1 XOR 0 1 1 0

Example: 3 input NOR gate: p0=7/8, p1=1/8 = 7/64

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A A+B+C B C 1 0 0 0 0 0 0 0

3 input NAND gate: p0 = 1/8, p1=7/8 = 7/64

CMOS Dynamic Power Dissipation

Short Circuit (Crowbar)
Ar = I sc , avg t sc , rise A f = I sc , avg t sc , fall I sc = t sc t sc , rise + t sc , fall T = t sc , rise i + t sc , fall f ll I sc , avg

Short circuit current when at No load PDN and PUN are both conducting during HL and LH transitions Duration depends on input rise and fall times tsc = time for VDD-IVtpI > VI > Vtn T

t I sc = sc I sc , avg T t Psc = sc I sc , avg V DD = t sc I sc , avg V DD f clk T dV I =C I t = C V dt Assume t sc I sc , avg = C scV DD

2 Psc = C scV DD f clk

Isc

Ar ISC,av tsc.rise

Af tsc.fall

Isc
t

where CSC is an equivalent short circuit capacitance

defined for analogy with dynamic power

CMOS Dynamic Power Dissipation

Short Circuit (Crowbar (Crowbar, Contd..)
Psc = I scV DD
2 Psc = C scV DD f clk

C sc = sc C L Another activity factor

2 Psc = sc C LV DD f clk 2 2 2 Pdynamic = 0 1C LV DD f clk + sc C LV DD f clk = C LV DD f clk

includes activity and short circuit effects

Minimum ISC : Rise and fall edges of input as sharp (minimum tsc) and as equal as possible. BUT This requires large currents in previous stage large transistors large CL large dynamic power Trade off between dynamic power of previous stage and short circuit power of next stage

CMOS Dynamic Power Dissipation

Glitches
Glitches
Extra output transitions due to asynchronous arrival of multiple inputs Leads to power consumption Minimized by managing input arrival time by adjusting - path delays -g gate delays y - right selection of gate and logic architecture SPICE:
0.25 m adjust the inputs of a 2 Input gate until a g glitch appears at the NOR g output during a transient analysis. What are the conditions for the glitch to occur .

CMOS Static Power Dissipation

Static Currents
2 Static 2. St ti Currents C t
Subthreshold Channel leakage current in "off" devices Junction Reverse bias current through pn junctions

Standby (DC) Current through normally on devices ( (Pseudo-NMOS) )

Pstatic = (I subthreshold + I junction + I standby ) VDD

CMOS Static Power Dissipation

St ti Currents Static C t
1. Subthreshold leakage current Isub
Most important static current loss N+
Source

N+
Drain

NMOS Bipolar action due to close proximity of source and drain Forward Bias of source junction Diffusion of minority carriers in the channel ( (base) ) region g [q (Vgs VT Voffset )/ nk BT ] ( qVDS / k BT )

I sub = I s e

1 e

To reduce Isub design factors 1. Larger VT trade off between ION and IOFF 2 Adjust 2. Adj VT during d i operation i ( (complex) l ) 3. Reduce VDS increase channel length 4. Add series R or Qs to PUN/ PDN to fragment VDS 5. Reduce temperature

CMOS Static Power Dissipation

St ti Currents Static C t
2. Junction leakage current Ipn
( qVbias / k BT ) ( qVbias / k BT ) Ip = I e 1 = A J e 1 pn pn S p 0

Negligible in most digital circuits To reduce Ipn design factor

Reduce junction area of source and drain (bottom and sidewall)

Standby Current IDC DC current in pseudo-NMOS gates when Vout = VOL Total Static Power Pstat= Ileak VDD= (Isub+ Ipn+ IDC)VDD

Power - Delay Trade-offs

Goal
Reduce power and delay Minimize Power-delay product (PDP)

PDP = Paverage x tp = Average power x average delay

Assume: Dominant source of dissipation Paverage = CVDD2f Propagation delay = 1/2f PDP = CVDD2f/2f = CVDD2/2

PDP = Energy per switching operation (per toggle)

Energy stored in C after a charging operation
2 VDD dvout CVDD vout (t )dt = Cvout (t )dvout = C 0 dt 2

EC ,01 = ic (t )vout (t )dt =

0

Design factors for PDP reduction Capacitance, Voltage swing, Supply voltage

PDP obscures effects of design modification delay

Power - Delay Trade offs

Energy Delay Product
Energy-Delay Energy Delay Product EDP
New metrics that show delay

EDP = average power x (average ( propagation ti delay) d l )2.

dV CV I =C t = dt I CV CVDD tp = I sat K 2 (VDD VT )

3 C 2VDD EDP = 2 K 2 (VDD VT )

No ormalize ed values

EDP = PDP t p

Energy Energy.delay gy y

Delay

3 EDP = 0 VDD ,opt = VT VDD 2

VDD

CMOS Inverter Delay

Hodges and Jackson, Chapter 6, Section 6.5.1, 6.5.2

Input (Gate) capacitance

Cin = CG(Wn+Wp) = CG(Wn + 2Wn) = 3 CGWn Reff = Reqn (Ln/Wn) Tinv = Reff Cin = Reqn (Ln/Wn) CG (3 Wn) = 3 ReqnCGLn
Vin Cin

VDD

Vout Cself Cout

No load: Capacitance at Output = inverter own capacitances at drain (CL = Cself) With load: Load capacitance = Cself + Cout capacitance due to a) input capacitance of load (Fan-out) gates at output b) wiring capacitance CL = Cself + Cout

CMOS Inverter Delay

Delay time constant Td
Td = Reff CL = Reff[Cout + Cself] = ReffCin [Cout/Cin + Cself/Cin] = Tinv i [Cout t/Cin i + in i ] Cout/Cin = f = fan out ratio (electrical effort) in = Cself/Cin depends on the gate layout
VDD

Vin Cin Cself

Vout Cout

Sizing Inverter for optimum delay

Required to drive a very large capacitance using inverter (s) To reduce the delay the effective resistance should be very small Solution:

1. Use one very big inverter with a very small resistance - It will have a very high input capacitance shifting the problem the previous stage - Its drain capacitance will also increase and adds to the load self loading capacitance
Cself loading

In

Out
CL

Cin high

Chain of Inverters
2. Use a chain of inverters to minimize the delay from input to output Design issue sizing of each inverter
In C1 1
N

Out j-1 j j+1

N

CL

Total delay Td = Tinv [Ci+1/Ci + inv] = Tinv[3CGWi+1/(3CGWi) + inv]

i=1 i=1

Consider delay of two consecutive inverters Dj = Tinv(Wj/(Wj-1 + inv) + Tinv(Wj+1/Wj + inv) To obtain the minimum delay derive Dj wrt Wj and equate to zero dDj/dWj = Tinv (1/Wj-1) Tinv (Wj+1/Wj2) = 0 Wj/Wj-1 = Wj+1/Wj Wj = VWj+1Wj-1)

Optimimum Chain of Inverters

2. Use a chain of inverters to minimize the delay from input to p Design g issue sizing g of each inverter output

In
Cin
1 f f2 fN-2 fN-1

Out
CL= fN Cin

Wj/Wj-1 = Cj/Cj-1 = Cout/Cin of inverter j = fj = f = constant for all inverters Each inverter is doing the same electrical effort CL/Cin = CL/CN x CN/CN-1 x CN-1/CN-2 X..X C2/Cin = fN = F = Total electric effort of chain At optimum sizing each gate delay = Tinv(Cj/Cj-1 + in)
1/N + ) Minimum path delay = NTinv i (f + in i ) = NTinv i (F i in

Optimum Chain of Inverters

Example: assume 3 inverters In
C1 1

f
3

f2

Out
CL = 8C1

f = 8 =2
Rewrite N in terms of fan-out/stage f ln (CL/C1) fN = CL/C1 N = ln f Need to find N that minimizesTd Td = NTinv [in + (CL/C1)1/N] = Tinv ln(CL/C1) [ in + f ] ln f

Optimum Chain of Inverters

To get minimum delay derive Td wrt to f
dTd/df = Tinv ln (CL/C1) x fopt = exp (1 + in/fopt)
If in = 0 (i.e. Cself = 0) f=e N = ln (CL/C1] If in = 1 f = 3.6 N = 0.78 . ln (CL/C1]

ln f 1 in/f (ln f )2

=0
5 4.5 4

fopt 3.5
3 2.5 0 0.5 1

fopt = 3.6 4

inv

1.5

2.5

Optimum Chain of Inverters

Delay D

(f = 3.6 6)

( f = e)

f
Practically in 1 Curve very flat for f 2 M t common used Most d value l used d f = 4 (magic ( i number) b )

Optimum Chain of Inverters

Td = N Tinv (in +
F (in i = 1) 10 100 1,000 10 000 10,000
N

F ), F = CL/C1

Unbuffered Two Stage Opt. Inverter 0.5) Chain = N.(1+3.6) Chain = 2(1+F ( ( ) = (1+F) 11 101 1001 10 001 10,001 8.3 22 65 202 8.3 16 5 16.5 24.8 33 1 33.1

Impressive p speed-ups p p with optimized p cascaded inverter chain for very large capacitive loads.

Optimum Chain of Inverters

Example of Inverter (Buffer) Staging (Assume in = 1)
1 C1 = 1 1 C1 = 1 1 C1 = 1 8 4 16 CL = 64 C1 8 CL = 64 C1 CL = 64 C1

N 1

f 64

tp 65

8
Optimum

18

15

1 C1 = 1

28 2.8

22 6 22.6

CL = 64 C1

2.8

15.3

Optimum Chain of Inverters: Energy vs Delay

driver
Cin

fCin

f2Cin

f3Cin

To be driven
CL = f4Cin

Overhead capacitances During g every y switching g cycle y all inverters are switching g Energy drawn from supply = CjV2DD Delay decreases but area and energy increases with number of inverters Trade-off (Compromise) Give up some delay for less energy / area Emin

tp,min