C:/Users/ASIC/Desktop/Project/MIPI LLI/TxDllTop.

//----------------------------------------------------------------------------------// Title : TxDllTop // Project : Janus //-----------------------------------------------------------------------------------// File : TxDllTop.v // Author : Vipul kumar <vipul_kumar@non.agilent.com> // Created : 28.October.2011 // Last modified : 28.October.2011 //-----------------------------------------------------------------------------------// *******SVN Revision History************* // Change for specific Revision Tool // $Date: // $Author: // $HeadURL: // $Revision: //-----------------------------------------------------------------------------------// Description : // TxDll is part of the Transmit Layer of the Exerciser .This Block follows the TxTLBlock in design. // The Output from the Transaction Layer is fed to this block. It takes packet (10 bytes data size) from the Transaction layer. // It implements following blocks // -- Sequence Inserter // -- Replay Buffer // -- RTT Timer // -- CRC Generator // 1 . Sequence no. Inserter block adds sequence no. to each incoming packet which is incremented per incoming packet. // This is fed to CRC block and Replay buffer. // 2. CRC block calculates CRC and adds 8 bit to incoming packet. So, now the 12 byte data which is called frame is transmitted // to PA layer block. As soon as packets are sent to CRC block, // 3. it is also stored in Replay buffer. Replay buffer retransmit its packets whenever there is a NACK received from RX Side. // For every stored packet, Round Trip timer generates a self acknowledgement by storing the time stamp of the packet and // compares its durability with RTT time. When RTT Timer sends acknowledgment, Replay buffer evict its packet corresponding to // the sequence no. When a NACK is received ,TxDLL sends a hold to TL and retransmit packets available in Replay buffer, // After successful acknowledgement of transmitted signal , it release hold for incoming TL packets and starts normal operation. // //-----------------------------------------------------------------------------------// Agilent Confidential // Copyright (c) 2010 by Agilent This model is the confidential and // proprietary property of Agilent and the possession or use of this // file requires a written license from Agilent. //-----------------------------------------------------------------------------------module TxDllTop ( clkTxDll resetAsync_n txTlData txTlDataValid txTlPktLcrcErr txTlPktDispErr txTlPktOffsetSeqNum rxDllNack SW_MAX_RTT_TIME rxPrepSync mrxInHibern8 txPaHold
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C:/Users/ASIC/Desktop/Project/MIPI LLI/TxDllTop.v

txDllHold txDllData txDllDataValid txDllPktDispErr );

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//--------------------- Input ports declaration------------------------------input clkTxDll input resetAsync_n input [79:0] txTlData from transaction layer input txTlDataValid data input txTlPktLcrcErr from transaction layer input txTlPktDispErr error from transaction layer input txTlPktOffsetSeqNum sequence number from transaction layer input rxDllNack acknowledgement from RX layer input [23:0] SW_MAX_RTT_TIME trip time input rxPrepSync PREPARE or SYNC state input mrxInHibern8 hibernate state input txPaHold not accept more data //--------------------- Output ports declaration-----------------------------output txDllHold data from Transaction layer output [95:0] txDllData layer output txDllDataValid valid data output txDllPktDispErr disparity error from DLL //-------------------- Internal variables declaration-----------------------wire [87:0] seqInserterOut_c after adding sequence number wire dataValid_c data wire [87:0] replayBufferData_c replay buffer wire [95:0] txDllData_c layer wire dataValid_out for PA layer wire selfAck_c acknowledgement signal from Rtt timer wire [5:0] seqNum_c Sequence number from Rtt timer wire [5:0] seqNumOut_c Sequence number from Sequence Inserter wire replayGrant_c NACK, take data from replay buffer wire replaywriteRead_c or read from replay buffer
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;// System clock ;// Async reset ;// Input data ;// Indicate valid ;// Lcrc error ;// Disparity ;// Offset ;// Negative ;// Maximum round ;// Link is in ;// Link is in ;// PA layer can

;// Stop taking ;// Data for PA ;// Qulifier for ;// Packet

;// Data packet ;// Qualifier for ;// Data from ;// Data for PA ;// Data Qulaifier ;// Self ;// Packet ;// Packet ;// Upon receiving ;// Either write
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C:/Users/ASIC/Desktop/Project/MIPI LLI/TxDllTop.v

wire bufferFull is full and stop taking data from TL wire fifoAlmostFull full and stop taking data from TL wire bufferNotEmpty buffer to seq inserter wire replayDone buffer to seq inserter wire getNack_d getNack wire dataValidBuffer from replay buffer reg txDllPktDispErr disparity error from DLL reg txTlPktDispErr_d delayed Packet disparity error from DLL

;// Replay buffer ;// Dpram almost ;// From replay ;// From replay ;// Delayed ;// data valid ;// Packet ;// 1 clock

//---------------------- Code starts here --------------------------------------

//**************************************************************************************

// Sequence inserter block adds sequence numer in incoming packetes , which increments sequentially. // // It passes data pacjets to CRC generator block ,It also sends same data to repaly buffer . // // Upon receiving NACK , it stops taking data from Transaction layer and start taking data // // from replay buffer. // //**************************************************************************************

SeqInserter inst_TxDllTop_SeqInserter ( . clkTxDll ( clkTxDll ), . resetAsync_n ( resetAsync_n & (!mrxInHibern8) ), . replayDataIn ( replayBufferData_c ), . dataInFromTl ( txTlData ), . packetEnable ( txTlDataValid ), . getNack ( rxDllNack ), . bufferFull ( bufferFull ), . fifoAlmostFull( fifoAlmostFull ), . bufferNotEmpty ( bufferNotEmpty ), . replayDone ( replayDone ), . dataValidBuffer( dataValidBuffer ), . txPaHold ( txPaHold ), . seqInsrtDataOut( seqInserterOut_c ), . txDllHold ( txDllHold ), . dataValid ( dataValid_c ), . replayGrant ( replayGrant_c ), . replaywriteRead( replaywriteRead_c ), . seqNumOut ( seqNumOut_c ), . getNack_2d ( getNack_d ) );

//************************************************************************************** // Replay buffer block Store same packets which is send to CRC block along with sequence number. // // It consists of RAM in which packets are being stored. It receives self acknowledgment signal from Round trip //
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// timer along with sequence no.RAM evicts its packets with the help of self acknowledgment signal. If NACK comes// // from receiver and then sequence inserter sends a stop request to RAM. Eviction of packets also got stopped. // // Replay buffer starts transmit its packets. // //************************************************************************************** xdlh_retrybuf_128b inst_TxDllTop_xdlh_retrybuf_128b ( .core_clk (clkTxDll .core_rst_n .cfg_bus_replay_timer_value .rbuf_timer_count_en .cfg_replay_num .rdlh_link_up .sm_in_l0s_recovery .tlpgen_rbuf_data .tlpgen_rbuf_dwen .tlpgen_rbuf_dv .tlpgen_rbuf_sot .tlpgen_rbuf_eot .tlpgen_rbuf_pkt_length .tlpgen_rbuf_seqnum .tlpgen_rbuf_badeot .tlpgen_reply_grant .rbuf_halt .rdlh_xdlh_rcvd_nack .rdlh_xdlh_rcvd_ack .rdlh_xdlh_rcvd_acknack_seqnum .rbuf_xmt_data .rbuf_xmt_dwen .rbuf_xmt_dv .rbuf_xmt_done .rbuf_xmt_eot .rbuf_xmt_seqnum .rbuf_xmt_pkt_length .rbuf_reply_req .rbuf_entry_cnt .rbuf_pkt_cnt .rbuf_par_err .xdlh_xmlh_start_link_retrain .xdlh_replay_timeout .xdlh_rbuf_not_empty .xdlh_not_expecting_ack .xdlh_rdlh_last_xmt_seqnum ); (resetAsync_n & (!mrxInHibern8) (16'hffff (1'b1 (8'd1 (1'b1 (1'b1 (seqInserterOut_c (4'hf (replaywriteRead_c (1'b1 (1'b1 (11'd0 (seqNumOut_c (1'b0 (replayGrant_c (1'b0 (getNack_d (selfAck_c (seqNum_c (replayBufferData_c ( (dataValidBuffer (replayDone ( ( ( ( ( ( ( ( ( (bufferNotEmpty ( (

), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), ), )

//**************************************************************************************

// RTT timer generates self acknowledgement signal along with sequence number to evict packet from replay buffer. // //************************************************************************************** RttTimer inst_TxDllTop_RttTimer ( . clkTxDll (clkTxDll . resetAsync_n (resetAsync_n & (!mrxInHibern8) . rxPrepSync (rxPrepSync . SW_MAX_RTT_TIME (SW_MAX_RTT_TIME . SnumfromInsrt (seqNumOut_c . pktEnable (dataValid_c . dataValidBuffer (dataValidBuffer . getNack (rxDllNack . bufferNotEmpty (bufferNotEmpty
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. txPaHold . selfAck . seqNum . TxDllHold . fifoAlmostFull );

(txPaHold (selfAck_c (seqNum_c (bufferFull (fifoAlmostFull

), ), ), ), )

//**************************************************************************************

// CRC block calculates CRC and adds 8 bit CRC information to incoming packet and sends it to PA layer. // //**************************************************************************************

CrcGenerator inst_TxDllTop_CrcGenerator ( .clkTxDll (clkTxDll .resetAsync_n (resetAsync_n & (!mrxInHibern8) .dataValidBuffer (dataValidBuffer .txPaHold (txPaHold .sqDataIn (seqInserterOut_c .crcEnable (dataValid_c .txTlPktLcrcErr (txTlPktLcrcErr .txTlPktOffsetSeqNum (txTlPktOffsetSeqNum .crcDataOut (txDllData_c .dataValid (dataValid_out ); assign txDllData = txDllData_c ; assign txDllDataValid = dataValid_out ;

), ), ), ), ), ), ), ), ), )

// Dll packet disparity error generation always @(posedge clkTxDll or negedge resetAsync_n) begin if(!resetAsync_n) begin txTlPktDispErr_d <= 1'b0 ; txDllPktDispErr <= 1'b0 ; end //(!resetAsync_n) else if(dataValidBuffer) begin txTlPktDispErr_d <= 1'b0 ; txDllPktDispErr <= 1'b0 ; end //(!resetAsync_n) else begin txTlPktDispErr_d txDllPktDispErr end // else end // always endmodule //TxDllTop //---------------------- Code ends here -------------------------------------<= txTlPktDispErr <= txTlPktDispErr_d ; ;

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