Part A Question & Answers

Unit-I : THE 8085 AND 8086 MICR PR CE!! R!

"# $i%e t&e si'ni(i)an)e o( !IM an* RIM instru)tion a%ai+a,+e in 8085# -N ./DEC 00061 Instruction SIM: Set Interrupt Mask. This is a 1 byte instruction and can be used three different functions as follows i)to set mask for RST 7. !". #$% . I$T&RR'(TS. ii) to reset RST 7. )lip )lop. iii)to implement serial I*+ operation. Instruction RIM: Read Interrupt Mask .this is a 1 byte instruction and can be used for the followin, three functions. i)to read interrupt masks. ii)to identify pendin, interrupts. iii)to recei-e serial data. $ote: draw the re,ister format 0# 2ist t&e *i((erent t34es o( (+a's a((e)te* ,3 t&e arit&5eti) an* +o'i) o4erations# -N ./DEC 00061 .arry fla,! au/illary carry fla,! parity fla,! si,n fla,! 0ero fla, 7# 2ist t&e interru4t si'na+s 4resent in 8085 4ro)essor in t&e 4riorit3 or*er# - A4r/5a3
00081

8#

5#

6#

6#

Interrupts (riority TR#( RST 7. RST ". RST . I$TR Co54are CA22 an* PU!H instru)tions 1hen .#22 is e/ecuted the microprocessor automatically stores the 1"3bit address of the instruction ne/t to .#22 on the stack. The pro,rammer uses the instruction ('S4 to sa-e the contents of accumulator on to the stack. 1hen .#22 is e/ecuted the stack pointer is decremented by two. 1hen ('S4 is e/ecuted the stack pointer re,ister is decremented by two 9&at is t&e use o( A2E: The #2& 5#ddress latch enable) is used to latch the lower order address so that it can be a-ailable in T6 and T7 and used for identifyin, the memory address. %urin, T1 the #2& ,oes hi,h. 1hen #2& ,oes low the lower order address is latched until the ne/t #2&. De(ine instru)tion )3)+e; 5a)&ine )3)+e an* T-state Instruction cycle is defined! as the time re8uired for completin, the e/ecution of an instruction. Machine cycle is defined as the time re8uired for completin, one operation of accessin, memory! I*+ or acknowled,in, an e/ternal re8uest. T3state is defined as one subdi-ision of the operation performed in one clock period 9&at is Mi)ro4ro)essor: $i%e t&e 4ower su44+3 & )+o)< (re=uen)3 o( 8085# # microprocessor is a multipurpose! pro,rammable lo,ic de-ice that reads binary instructions from a stora,e de-ice called memory accepts binary data as input and

processes data accordin, to those instructions and pro-ides result as output. The power supply of 9:9 is ; < and clock fre8uency in 7M40. 8# 9&at is an 4)o*e & 4eran*: The part of the instruction that specifies the operation to be performed is called the operation code or opcode. The data on which the operation is to be performed is called as an +perand ># 9&3 a**ress ,us is uni*ire)tiona+: The address is an identification number used by the microprocessor to identify or access a memory location or I * + de-ice. It is an output si,nal from the processor. 4ence the address bus is unidirectional. "0# 9&at are t&e (un)tions o( an a))u5u+ator: The accumulator is the re,ister associated with the #2' operations and sometimes I*+ operations. It is an inte,ral part of #2'. It holds one of data to be processed by #2'. It also temporarily stores the result of the operation performed by the #2'. ""# 9&at is t&e use o( a**ressin' 5o*es; 5ention t&e *i((erent t34es The -arious formats of specifyin, the operands are called addressin, modes! it is used to access the operands or data. The different types are as follows Immediate addressin, Re,ister addressin, %irect addressin, Indirect addressin, Implicit addressin,
Unit-II :8086 ! ?T9ARE A!PECT!

"# 9&at is t&e 4ur4ose o( se'5ent re'isters in 8086: There are = se,ment re,isters present in 9:9". They are 1. .ode Se,ment 5C!@ re,ister 6. %ata Se,ment 5D!@ re,ister 7. Stack Se,ment 5!!@ re,ister =. &/tra Se,ment 5E!@ re,ister The )o*e se'5ent re,ister ,i-es the se,ment address of the current code se,ment. The *ata se'5ent re,ister points out where the operands are stored in the memory. The sta)< se'5ent re,isters points out the address of the current stack. The EAtra se'5ent re,isters points out where the lar,e amount of data is stored in the memory. 0# 9&at *o 3ou 5ean ,3 4i4e+inin' in an 8086 4ro)essor:-N ./DEC 00061 In 9:9"! to speed up the e/ecution of pro,ram! the instructions fetchin, and e/ecution of instructions are o-erlapped each other. This techni8ue is known as pipelinin,. In pipelinin,! when the n instruction is e/ecuted! the 5n;1) instruction is fetched and thus the processin, speed is increased. 7# 9&at is interru4t ser%i)e routine:-No%/De) 000>1 Interrupt means to break the se8uence of operation. 1hile the .(' is e/ecutin, a pro,ram an interrupt breaks the normal se8uence of e/ecution of instructions > di-erts
th th

8#

5#

6#

6# 8#

>#

its e/ecution to some other pro,ram. This pro,ram to which the control is transferred is called the interrupt ser-ice routine. 9&at are Ma)ros: -No%/De) 00061 Macro is a ,roup of instruction. The macro assembler ,enerates the code in the pro,ram each time where the macro is called. Macros are defined by M#.R+ > &$%M directi-es. .reatin, macro is similar to creatin, new opcodes that can be used in the pro,ram I$IT M#.R+ M+< #?! data M+< %S M+< &S! #? &$%M 9&at is t&e nee* o( a (+a' re'ister in 8086#-No%/De) 000>1 It indicates the status of the accumulator. There are " one bit fla,s are present. They are! #) 3 #u/iliary .arry )la, .) 3 .arry )la, +) 3 +-erflow )la, S) 3 Si,n )la, () 3 (arity )la, @) 3 @ero )la, EA4+ain PUB2IC asse5,+er# )or lar,e pro,rams se-eral small modules are linked to,ether. In order that the modules link to,ether correctly any -ariable name or label referred to in other modules must be declared public in the module where it is defined. The ('A2I. directi-e is used to tell the assembler that a specified name or label will be accessed from other modules. 9&at are t&e two 5o*es o( o4erations 4resent in 8086: i. Minimum mode 5or) 'niprocessor system ii. Ma/imum mode 5or) Multiprocessor system !tate t&e si'ni(i)an)e o( 2 CC si'na+ in 8086: If 9:9" is workin, at ma/imum mode! there are multiprocessors are present. If the system bus is ,i-en to a processor then the 2+.B si,nal is made low. That means the system bus is busy and it cannot be ,i-en of any other processors. #fter the use of the system bus a,ain the 2+.B si,nal is made hi,h. That means it is ready to ,i-e the system bus to any processor. 9&at are t&e si'na+s in%o+%e* in 5e5or3 ,an< se+e)tion in 8086 5i)ro4ro)essor: The 9:9" based system will ha-e two sets of memory I.Cs. +ne set for e-en bank and another for odd bank. The data lines %:3%7 are connected to e-en bank and the data lines %93%1 are connected to odd bank. The e-en memory bank is selected by address line #: and odd memory bank is selected by control si,nal A4& .The memory banks are selected when these si,nals are acti-e low.

"0# 9&at *o t&ese 8086 instru)tions *o: -No%/De) 00061 ST%3 Set %irection )la,: when this instruction is e/ecuted! the direction fla, of 9:9" is set to 1.

IR&T3Interrupt Return: this instruction is used to terminate an interrupt ser-ice procedure and transfer the pro,ram control back to main pro,ram.
""# EA4+ain t&e 4ro)ess )ontro+ instru)tions

ST. D It sets the carry fla, > does not affect any other fla, .2. D it resets the carry fla, to 0ero >does not affect any other fla, .M. D It complements the carry fla, > does not affect any other fla, ST% D It sets the direction fla, to 1 so that SI and*or %I can be decremented automatically after e/ecution of strin, instruction > does not affect other fla,s .2% D It resets the direction fla, to : so that SI and*or %I can be incremented automatically after e/ecution of strin, instruction > does not affect other fla,s STI D Sets the interrupt fla, to 1. &nables I$TR of 9:9". .2I D Resets the interrupt fla,to:. 9:9" will not respond to I$TR.
Unit-III :MU2TIPR CE!! R C N?I$URATI N!

"# 9&at are ti'&t+3 )ou4+e* s3ste5s or )+ose+3 )ou4+e* s3ste5s: In a ti,htly coupled systems the microprocessor 5either coprocessor or independent processors may share a common clock and bus control lo,ic.. The two processors in a closely coupled system may communicate usin, a common system bus or common memory. 0# 9&at are +oose+3 )ou4+e* s3ste5s: In loosely coupled systems each .(' may ha-e its own bus control lo,ic. The bus arbitration is handled by an e/ternal circuit! common to all processors. The loosely coupled system confi,uration like 2#$ > 1#$ can be spreaded o-er a lar,e area. 7# 9rite so5e a*%anta'es o( +oose+3 )ou4+e* s3ste5s o%er ti'&t+3 )ou4+e* s3ste5s More number of .('s can be added in loosely coupled systems to impro-e the system performance. The system structure is modular and hence easy to maintain and troubleshoot. # fault in a sin,le module does not lead to a complete system breakdown. %ue to the independent processin, modules used in the system! it is more fault tolerant! more suitable to parallel applications due to its modular or,ani0ations. 8# 9rite so5e *isa*%anta'es o( +oose+3 )ou4+e* s3ste5s More complicated due to the re8uired additional communication hardware. They are less portable and more e/pensi-e due to the additional hardware and the communication media re8uirement. 5# 9&at are t&e 5u+ti 5i)ro4ro)essor )on(i'uration 5et&o*s#-a4r/5a3 000>1 Ti,htly coupled systems or closely coupled systems 2oosely coupled systems 6# 9&at is 5eant ,3 Dais3 )&ainin' 5et&o*: It does not re8uire any priority resol-in, network! rather the priorities of all the de-ices are essentially assumed to be in se8uence. #ll the masters use a sin,le bus re8uest line for re8uestin, the bus access. The controller sends a bus ,rant si,nal! in response to the re8uest! if the busy si,nal is inacti-e when the bus is free. The bus ,rant pulse ,oes to each of the masters in the se8uence till it reaches a re8uestin, master .The master then recei-es the ,rant si,nal!

acti-ates the busy line and ,ains the control of the bus. The priority is decided by the position of the re8uestin, master in the se8uence. 6# 9&at is in*e4en*ent ,us re=uest s)&e5e: &ach of the masters re8uires a pair of re8uest and ,rant pins which are connected to the controllin, lo,ic. The busy line is common for all the masters. . f the controllin, lo,ic recei-es a re8uest on a bus re8uest line! it immediately ,rants the bus access usin, the correspondin, bus ,rant si,nal! pro-ided the A'SE line is inacti-e! and then ,rants the re8uest. This is 8uite fast! because each of the masters can independently communicate with the controller. 8# 9&at is 5eant ,3 4o++in': In pollin, schemes! a set of address lines is dri-en by the controller to address each of the masters in se8uence. 1hen a bus re8uest is recei-ed from a de-ice by the controller! it ,enerates the address on the address lines. If the ,enerated address matches with that of the re8uestin, masters! the controller acti-ates the A'SE line. ># Na5e t&e *ata t34es o( 8086# Ainary inte,er o 1ord o Short o 2on, (acked decimal number5A.%) )loatin, point *real number o Short o 2on, o Temporary real "0# EA4+ain nu5eri) 4ro)essor 8086. $umeric processor 9:97 is a coprocessor which has been desi,ned to work under the control of the processor 9:9" and offer it additional numeric processin, capabilities. It supports 1"! 76! "=3bit inte,ers 76! "=! 9:3bit floatin, point and 1" di,it A.% data types. ""# 9&at are t&e (un)tiona+ units a%ai+a,+e in 8086: .'3control unit $&' 3 $umeric e/ecution unit.
Unit I.: I/ INTER?ACIN$

"# Na5e t&e t&ree 5o*es use* ,3 t&e DMA 4ro)essor to trans(er *ata: - N ./DEC
00061

Si,nal transfer mode 5cyclin, stealin, mode) Alock transfer mode %emand transfer mode 0# Na5e t&e 6 5o*es o( o4erations o( an 8057 4ro'ra55a,+e inter%a+ ti5er#- N ./DEC
00061

Mode ::interrupt on terminal count Mode 1:hardware re 3tri,,erable one3shot Mode 6 :rate ,enerator Mode7:s8uare wa-e rate ,enerator

7#

8# 5#

6#

6#

8#

Mode =:software tri,,ered strobe Mode :hardware tri,,ered strobe 9&at are t&e (eatures use* 5o*e " in 8055: Two ,roups D ,roup # and ,roup A are a-ailable for strobed data transfer. &ach ,roup contains one 93bit data I*+ port and one =3bit control*data port. The 93bit data port can be either used as input or output port. The inputs and outputs both are latched. +ut of 93bit port .! (.:3(.6 is used to ,enerate control si,nals for port A and (.7F(. are used to ,enerate control si,nals for port #. The lines (."! (.7 may be used as independent data lines. 9&at is 5e5or3 5a44in': The assi,nment of memory addresses to -arious re,isters in a memory chip is called as memory mappin,. 9&at is <e3 ,oun)in': Mechanical switches are used as keys in most of the keyboards. 1hen a key is pressed the contact bounce back and forth and settle down only after a small time delay 5about 6:ms). &-en thou,h a key is actuated once! it will appear to ha-e been actuated se-eral times. This problem is called Bey Aouncin,. 9&at are t&e *i((erent t34es o( 5et&o*s use* (or *ata trans5ission: The data transmission between two points in-ol-es unidirectional or bi3directional transmission of meanin,ful di,ital data throu,h a medium. There are basically there modes of data transmission 5a) Simple/ 5b) %uple/ 5c) 4alf %uple/ In simple/ mode! data is transmitted only in one direction o-er a sin,le communication channel. )or e/ample! a computer 5.(' is recei-ed by the computer 5i.e the computer is recei-er). 4owe-er! it is not possible to transmit data from the computer to terminal and from terminal to the computer simultaneously. 9&at are t&e %arious 4ro'ra55e* *ata trans(er 5et&o*s: i) Synchronous data transfer ii) #synchronous data transfer iii) Interrupt dri-en data transfer 9&at are t&e ,asi) 5o*es o( o4eration o( 8055: Mode : 3 Aasic I*+ mode Mode 1 3 Strobed I*+ mode Mode 6 3 Strobed bi3directional I*+ 9&at is an U!ART: 'S#RT stands for uni-ersal synchronous*#synchronous Recei-er*Transmitter. It is a pro,rammable communication interface that can communicate by usin, either synchronous or asynchronous serial data.

># 9&at is t&e use o( ter5ina+ )ount re'ister:

&ach of the four %M# channels of 96 7 has one terminal count re,ister. This 1"3 bit re,ister is used for ascertainin, that the data transfer throu,h a %M# channel ceases or stops after the re8uired number of %M# cycles. "0# De(ine HRQ: The hold re8uest output re8uests the access of the system bus. In non3 cascaded 96 7 systems! this is connected with 4+2% pin of .('. In cascade mode! this pin of a sla-e is connected with a %RG input line of the master 96 7!while that of the master is connected with 4+2% input of the .('.
Unit-.: MICR C NTR 22ER!

"# EA4+ain DDNE instru)tions o( inte+ 805" 5i)ro)ontro++er: a) %H$@ Rn! rel %ecrement the content of the re,ister Rn and Iump if not 0ero. b) %H$@ direct ! rel %ecrement the content of direct 93bit address and Iump if not 0ero. 0# !tate t&e (un)tion o( R!" an* R!0 ,its in t&e (+a' re'ister o( inte+ 805"5i)ro)ontro++er: RS1 ! RS: D Re,ister bank select bits RS1 RS: Aank Selection : : Aank : : 1 Aank 1 1 : Aank 6 1 1 Aank 7 7# $i%e t&e a+ternate (un)tions (or t&e 4ort 4ins o( 4ort7: R% D Read data control output. 1R D 1rite data control output. T1 D Timer * .ounter1 e/ternal input or test pin. T: D Timer * .ounter: e/ternal input or test pin. I$T13 Interrupt 1 input pin. I$T : D Interrupt : input pin. T?% D Transmit data pin for serial port in '#RT mode. R?% 3 Recei-e data pin for serial port in '#RT mode 8# EA4+ain t&e (un)tion o( t&e 4ins P!EN an* EA o( 805". (S&$: (S&$ stands for pro,ram store enable. In 9: 1 based system in which an e/ternal R+M holds the pro,ram code! this pin is connected to the +& pin of the R+M. &# : &# stands for e/ternal access. 1hen the &# pin is connected to <cc! pro,ram fetched to addresses ::::4 throu,h :)))4 are directed to the internal R+M and pro,ram fetches to addresses 1:::4 throu,h ))))4 are directed to e/ternal R+M*&(R+M. 1hen the &# pin is ,rounded! all addresses fetched by pro,ram are directed to the e/ternal R+M*&(R+M. 5# EA4+ain t&e "6-,it re'isters DPTR an* !P o( 805"# DPTR: %(TR stands for data pointer. %(TR consists of a hi,h byte 5%(4) and a low byte 5%(2). Its function is to hold a 1"3bit address. It may be manipulated as

a 1"3bit data re,ister or as two independent 93bit re,isters. It ser-es as a base re,ister in indirect Iumps! lookup table instructions and e/ternal data transfer. !P: S( stands for stack pointer. S( is a 93 bit wide re,ister. It is incremented before data is stored durin, ('S4 and .#22 instructions. The stack array can reside anywhere in on3chip R#M. The stack pointer is initialised to :74 after a reset. This causes the stack to be,in at location :94.
6# 2ist t&e a44+i)ations o( 5i)ro)ontro++er# -MAF/DUNE 000>1

Stepper motor interfacin, 2en,th measurement S8uare wa-e ,enerator 6# De(ine GTA2" an* GTA20. -MAF/DUNE 000>1 Inbuilt oscillator which deri-es the necessary clock fre8uency for the operation of the controller. ?T#21 is the input of amplifier and ?T#26 is the output of the amplifier. 8# Co54are Mi)ro4ro)essor an* Mi)ro)ontro++er# -N ./DEC 00061 Mi)ro4ro)essor Mi)ro)ontro++er Microprocessor contains Microcontroller contains the circuitry #2'! ,eneral purpose of microprocessor and in addition it re,isters! stack pointer! has built3 in R+M! R#M! I*+ pro,ram counter! clock timin, de-ices! timers and counters. circuit and interrupt circuit. It has many instructions to It has one or two instructions to mo-e mo-e data between memory data between memory and .('. and .(' It has one or two bit handlin, It has many bit handlin, instructions. Instructions = #ccess times for memory and 2ess access times for built3in memory I*+ and I*+ de-ices de-ices are more. Microprocessor based system re8uires more hardware. Microcontroller based system re8uires less hardware reducin, (.A si0e and increasin, the reliability.

># 9&at are t&e a*%anta'es o( 5i)ro)ontro++er o%er 5i)ro4ro)essor: The o-erall system cost is low! as the peripherals are inte,rated in a sin,le chip. Si0e is small. &asy to troubleshoot and maintain. System is more reliable.

"0# Na5e t&e (i%e interru4t sour)es o( 805": The interrupts are: <ector address &/ternal interrupt : : I&: : :::74 Timer interrupt : : T): : :::A4 &/ternal interrupt 1 : I&1 : ::174 JTimer Interrupt 1 : T)1 : ::1A4

Serial Interrupt