Memory

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL
Chapter 9
Memory Devices
his chapter is an introduction to computer memory devices. We discuss the random-access memory (RAM), read-only memory (ROM), row and column decoders, memory chip organization, static RAMs (SRAMs) dynamic RAMs (DRAMs), volatile, nonvolatile, programmable ROMs (PROMs), Erasable PROMs (EPROMs), Electrically Erasable PROMs (EEPROMs), flash memories, and cache memory.
9.1 Random-Access Memory (RAM)

Random access memory (RAM) is the best known form of computer memory. RAM is considered "random access" because we can access any memory cell directly if we know the row and column that intersect at that cell. In a typical RAM, the access time is independent of the location of the data within the memory device, in other words, the time required to retrieve data from any location within the memory device is always the same and can be accessed in any order. RAM is volatile, that is, data are lost when power is removed. Another type of memory is the serial access memory (SAM). This type of memory stores data as a series of memory cells that can only be accessed sequentially (like a cassette tape). If the data is not in the current location, each memory cell is checked until the required data is found. SAM works very well for memory buffers, where the data is normally stored in the order in which it will be used such as the buffer memory on a video card. One advantage of SAM over RAM is that the former is nonvolatile memory, that is, stored data are retained even though power is removed. Our subsequent discussion will be restricted to RAM devices. In a RAM device, the access time, denoted as t a , is illustrated with the timing diagram of Figure 9.1.
Address changes Address lines Data lines Data become available
ta Figure 9.1. Access time defined
Digital Circuit Analysis and Design with an Introduction to CPLDs and FPGAs Orchard Publications
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JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Chapter 9 Memory Devices

Figure 9.2 shows a block diagram of the input and output lines of a typical RAM device.
A0 Address inputs A1 A2 AN
D0 D1
RAM
D2 DN
Data inputs outputs
RW
Read Write
R W = 0 Write R W = 1 Read
Figure 9.2. Block diagram of a typical RAM device
The bits on a memory device can be either individually addressed, or can be addressed in groups of 4, 16, 64, and so on. Thus, a 64M -bit device in which all bits are individually addressed, is known as 64M 1 , that is, the device is configured as a 26-bit address where 2 26 = 67, 108, 864 , and for convenience it is referred to as 64M words 1 bit memory device. The bulk part of a memory device consists of cells where the bits are stored. We may think of a cell being a D-type flip flop, and the cells are organized in a square matrix. Figure 9.3 shows a block diagram of a 67, 108, 864 (8192 8192) words by 1 bit, referred to as 64M 1 RAM device arranged in a 8192 by 8192 square matrix.
A0 Address inputs Row A 2 decoder A 12 A1 D0
8192 8192 cell matrix
D1 Data flow D 2 controller DN Enable R W
Data inputs outputs
Column decoder A 13 A 14 A 15 A 25
Figure 9.3. A 64M words by 1 bit RAM device
In Figure 9.3, during a read operation, a cell is selected for reading or writing by enabling its row through the row-address decoder, and its column through the column-address decoder. A sense
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Read-Only Memory (ROM)
amplifier (not shown) detects the contents of the selected cell and provides it to the data-output terminal of the device. A similar operation is used for a write operation. Example 9.1 We have an abundance of RAM chips each with 4096 rows and 256 columns and we want to construct a 16M bit memory. a. How many RAM chips do we need to form this memory? b. How many row address lines, column address lines, and lines for the RAM chips do we need for this memory? Solution: a. The actual size of a 16M bit memory is 16, 772, 216 and thus we will need
16 , 772, 216 ----------------------------- = 16 of 4096 256 RAM chips 4096 256
b. 4096 = 2 12 so for 12 bits we will need 12 row lines and since 256 = 2 8 , we will need 8 column lines. We will also need one line for each RAM chip for a total of 16 RAM chip select lines. RAMs are classified as static or dynamic. Static RAMs, referred to as SRAMs, use flip flops as the storage cells. Dynamic RAMs, referred to as DRAMs, use capacitors of the storage cells but the charge in the capacitors must be periodically refreshed. The main advantage of DRAMs over SRAMs is that for a given device area, DRAMs provide much higher storage capacity.
9.2 Read-Only Memory (ROM)

Read-Only Memories (ROMs) are memories in which the binary information is prewritten by special methods and the contents cannot be changed by the programmer or by any software. ROMs are also nonvolatile so that they need not be reprogrammed after power has been removed. ROMs are used to perform tasks such as code conversions, mathematical table look-up, and to control special purpose programs for computers. As with RAMs, ROMs are arranged as N words by M bits, and when the user provides an address the ROM outputs the data of the word which was written at that address. Access time for a ROM is the time between the address input and the appearance of the resulting data word. Present day ROMs are constructed with Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).* However, for simplicity, we will illustrate the operation of a typical ROM with resistors and diodes. A simplified ROM circuit is shown in Figure 9.4.
* For a detailed discussion of MOSFETs, refer to Electronic Devices and Amplifier Circuits, ISBN 0-97442394-7.
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V CC Resistor Diode
X2 ROM inputs
3 to 8 X 1 decoder
X0 Outputs are active Low Y3 Y2 Y1 Y0
ROM outputs
Figure 9.4. Simplified ROM circuit
The ROM circuit of Figure 9.4, consists of a decoder, a diode matrix, resistors, and a power supply. For our present discussion, a diode is an electronic device which allows electric current to flow in one direction only. A resistor is an electrical device in which when an electric current flows through, it produces a voltage drop (potential difference) across its terminals. The power supply, denoted as V CC , provides power to the ROM circuit. The input lines X 0 , X 1 , and X 2 , select one of the 8 outputs of the decoder which when active Low, selects the appropriate word appearing at the outputs Y 0 , Y 1 , Y 2 , and Y 3 . These outputs go Low if they are connected to the decoder output lines via a diode and that the decoder output line is Low. This is illustrated with the simplified resistor-diode circuit shown in Figure 9.5.
V CC Y V CC
Y
Y (Low) (a) Y (High) (b)
Figure 9.5. Simplified resistor-diode circuit
The output Y is Low (logic 0) whenever the selected decoder output line which is active Low allows electric current to flow through the resistor and through the diode thus developing a volt Same reference as above.
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Read-Only Memory (ROM)
age drop (potential difference) equal to V CC as shown in Figure 9.5(a). The output Y is High (logic 1) whenever the selected decoder output line is not active Low, and in this case no current flows and thus resistor-diode forms an open circuit as shown in Figure 9.5(b). Table 9.1 shows the outputs Y of the ROM circuit of Figure 9.4 for each input combination.
TABLE 9.1 Outputs for the ROM circuit of Figure 9.4 Inputs Outputs X2 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 Y3 0 0 0 0 0 1 1 1 Y2 0 0 0 1 1 1 0 1 Y1 0 1 0 1 0 1 1 0 Y0 0 0 1 0 0 0 1 0
ROMs are used extensively as look up tables for different functions such as trigonometric functions, logarithms, square roots, etc. Table 9.2 is an example of a look up table where a 4-bit input and a 4-bit output is used to convert an angle between 0 and 90 degrees to its cosine. We recall that as 0 90 , the cosine assumes the range of values in the interval 0 90
TABLE 9.2 An example of a lookup table (deg) 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 Binary input 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 Output ( cos ) - Fractional values 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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The output values for cos are understood to be fractional values. For instance,
cos 30 = 0.0 2 + 1 2 + 1 2 + + 1 2
1 2 3 10
= 0.499 0.5
Programming instructions that are stored in a read-only memory unit rather than being implemented through software are known as firmware. ROMs are also used as character generators referred to as CGROMs. For instance, a CGROM device may be designed to produce 128 characters in a 7 by 9 matrix. To select one of the characters, the appropriate binary code is applied at the address inputs of the device. All CGROM devices are capable of shifting the descender characters g , j , p , q , and y , below the baseline. Figure 9.6 shows the non-shifted characters A and a and the shifted character j .
9.3 Programmable Read-Only Memory (PROM)

A programmable read-only memory (PROM) is simply a ROM that can be programmed by hardware procedures. When first bought, PROMs contain all zeros (or all ones) in every bit of the stored binary words. The buyer can then use a PROM programmer to break certain links thus changing zeros to ones (or ones to zeros) as desired, and thus an unbroken link represents one state and a broken link another state. Figure 9.7 shows a simplified method of programming a PROM where each closed switch represents an unbroken link and an open switch represents a broken link.
R0 R1 R2 R3 R4 R5 R6 R7 R8 R0 R1 R2 R3 R4 R5 R6 R7 R8 R3 R4 R5 R6 R7 R8 R9 R10 R11
C0 C2 C4 C6 C1 C3 C5
C0 C2 C4 C6 C1 C3 C5
C0 C2 C4 C6 C1 C3 C5
Figure 9.6. Characters in a typical CGROM
In commercially available PROMs, the open/close switches shown in Figure 9.7 are actually fuses. In a PROM, a charge sent through a column will pass through the fuse in a cell to a grounded row indicating a value of 1. Since all the cells have a fuse, the initial (blank) state of a PROM chip is all logic 0s assuming that the decoder outputs are active Low. To change the value of a cell to logic 1, we use a programmer to send a specific amount of current to the cell and this current burns the fuse. Accordingly, this process is known as burning the PROM. Obviously, PROMs can only be programmed once.
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JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Erasable Programmable Read-Only Memory (EPROM)

V CC
X2 X1 X0 3 to 8 decoder Outputs are active Low
ROM inputs
Y3
Y2 ROM outputs
Y1
Y0
Figure 9.7. A simplified illustration of a typical PROM
9.4 Erasable Programmable Read-Only Memory (EPROM)

Erasable programmable read-only memory (EPROM) can be erased and reprogrammed many times. To rewrite an EPROM, we must erase it first. To erase an EPROM, a special tool that emits an ultraviolate (UV) light at a certain frequency and specified duration. In commercially available EPROMs, the cell at each intersection of a row and a column is usually an enhancement type nchannel MOSFET* with two gates, one referred to as the floating gate, and the other as select (or control) gate. These two gates are separated from each other by a thin oxide layer. The floating gate is programmed by applying a relatively large voltage, typically 15 to 18 volts between the drain and the source of the MOSFET. This voltage causes the floating-gate to act like an electron gun. The excited electrons are pushed through and trapped on the other side of
* For a detailed discussion on MOSFETs, please refer to Electronic Devices and Amplifier Circuits, ISBN 09744239-4-7.
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the thin oxide layer, creating a negative charges and these charges act as a barrier between the select gate and the floating gate. A device called a cell sensor monitors the level of the electron charge passing through the floating gate. If the flow through the gate is greater than 50 percent of the charge, it has a value of 1. When the charge passing through drops below the 50-percent threshold, the value changes to 0. A blank EPROM has all of the gates fully open and this results in a logic 1 in each cell of the EPROM.
9.5 Electrically-Erasable Programmable Read-Only Memory (EEPROM)

The electrically-erasable PROM (EEPROM) is a variant of the EPROM that can be erased and reprogrammed without the use of ultraviolet light. EEPROMs remove the biggest drawbacks of EPROMs. EEPROMs need not be removed to be rewritten, and there is no need that the entire chip has to be completely erased. Moreover, changing the contents does not require additional dedicated equipment. Generally, the contents of EEPROMs change state 1 byte at a time. However, EEPROM devices are too slow to use in many products that require quick changes to the data stored on the device.
9.6 Flash Memory

Flash memory is rewritable memory chip that holds its contents without power. It is used for easy and fast information storage in cell phones, digital cameras, and video game consoles. Flash memory works much faster than traditional EEPROMs because it writes data in chunks, usually 512 bytes in size, instead of 1 byte at a time. One of the most common uses of flash memory is for the basic input/output system (BIOS) of a computer. The task of the BIOS it to make sure that all the other devices, i.e., hard drives, ports, microprocessor, etc., function together and properly.
9.7 Memory Sticks

A memory stick is a device that uses flash memory. It was first introduced in 1998. A memory stick records various types of digital content, allows sharing of content among a variety of digital products, and it can be used for a broad range of applications. The dimensions of a typical memory stick is 1.97 x 0.85 x 0.11 in. A smaller size, known as memory stick duo media, has dimensions 1.22 x 0.79 x 0.06 in, and it is extensively used in mobile applications. The maximum theoretical access speed of a modern technology memory stick is about 150 Mbps but the actual speed depends on the design of the host device. Generally, all memory stick media are pre-formatted by the manufacturer and they are readily available for immediate use. The manufacturer provides re-formatting instructions in the event that the user wishes to reformat the memory stick at a later date. It is also possible to transfer data from a memory stick to a PC through a memory stick USB reader/writer. The advantages of flash memory over a hard disk are that flash memory is noiseless, provides faster access, smaller size and weight, and has no moving parts. However, the big advantage of a hard disk is that the cost per megabyte for a hard disk is considerably cheaper, and the its capacity is substantially higher than that of flash memory device.
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Cache Memory
A very popular flash memory device it the SmartMedia developed by Toshiba. SmartMedia cards are available in capacities ranging from 2 MB to 128 MB. The card is very small, approximately 45 mm long, 37 mm wide and less than 1 mm thick. SmartMedia cards can be erased, written onto, and read from memory in small blocks (256- or 512-byte increments). Accordingly, they are fast, reliable, and allows the user to select the data he wishes to keep.
9.8 Cache Memory

Cache memory is essentially a fast storage buffer in the microprocessor of a computer. Caching refers to the arrangement of the memory subsystem in a typical computer that allows us to do our computer tasks more rapidly. Thus, the main purpose of a cache is to accelerate the computer while keeping the price of the computer low. Modern computers are bundled with both L1 and L2 caches and these terms are explained below. Let us consider the case where in a typical computer the main memory (RAM) access time is 20 nanoseconds and the cycle time of the microprocessor is 0.5 nanosecond. Without cache memory, the microprocessor is forced to operate at the RAMs access time of 20 nanoseconds. Now, let us assume that a microprocessor is build with a small amount of memory within in addition to the other components, and that memory has an access time of 05 nanosecond, the same as the microprocessors cycle time. This memory is referred to as Level 1 cache or L1 cache for short. Let us also suppose that, in addition to L1 cache, we install memory chips on the motherboard that have an access time of 10 nanoseconds. This memory is referred to as Level 2 cache or L2 cache for short. Some microprocessors have two levels of cache built right into the chip. In this case, the motherboard cache becomes Level 3 cache, or L3 cache for short. Cache can also be built directly on peripherals. Modern hard disks come with fast memory, hardwired to the hard disk. This memory is controlled by the hard disk controller. Thus, as far as the operating system is concerned, these memory chips are the disk itself. When the computer asks for data from the hard disk, the hard-disk controller checks into this memory before moving the mechanical parts of the hard disk (which is very slow compared to memory). If it finds the data that the computer asked for in the cache, it will return the data stored in the cache without actually accessing data on the disk itself, saving a lot of time.
9.9 Virtual Memory

Virtual memory refers to a scheme where the operating system frees up space in RAM to load a new application. Virtual memory can be thought of as an alternative form of memory caching. For instance, let us suppose that the RAM is full with several applications open at a particular time. Without virtual memory, we will get a message stating that the RAM is full and we cannot load another application unless we first close one or more already loaded applications. However, with virtual memory, the operating system looks at RAM for files that have not used recently, and copies them onto the hard disk. This creates space for another application to be loaded. The copying from RAM to the hard disk occurs automatically, and the user is unaware of this operation. Therefore, to the user it appears that the computer has unlimited RAM space. Virtual memory provides the benefit that hard disk space can be used in lieu of a large amount of RAM Digital Circuit Analysis and Design with an Introduction to CPLDs and FPGAs Orchard Publications
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since the hard disk costs less. The area of the hard disk that stores the RAM image is called a page file. It holds pages of RAM on the hard disk, and the operating system moves data back and forth between the page file and RAM. On Windows platforms, page files have the .SWP extension. Practically, all operating systems include a virtual memory manager to enable the user to configure virtual memory manually in the event that we work with applications that are speed-critical and our computer has two or more physical hard disks. Speed may be a serious concern since the read/write speed of a hard drive is much slower than RAM, and the technology of a hard drive is not designed for accessing small pieces of data at a time. If our system has to rely too heavily on virtual memory, we will notice a significant performance drop. Our computer must have sufficient RAM to handle everything we need to work with. Then, the only time we may sense the slowness of virtual memory would be when there is a slight pause when we are swapping tasks. In this case, the virtual memory allocation is set properly. Otherwise, the operating system is forced to constantly swap information back and forth between RAM and the hard disk, and this occurrence is known as thrashing, that is, thrashing can make our computer operate at very slow speed.
9.10 Scratch Pad Memory

A scratch-pad memory is a usually high-speed internal register used for temporary storage of preliminary data or notes. It is a region of reserved memory in which programs store status data. Scratch pad memory is fast SRAM memory that replaces the hardware-managed cache, and may be used to transfer variables from one task to another.
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Summary
9.11 Summary
Random access memory (RAM) is the type of memory where the access time is independent of the location of the data within the memory device, in other words, the time required to retrieve data from any location within the memory device is always the same and can be accessed in any order. RAM is volatile, that is, data are lost when power is removed. Serial access memory (SAM) is memory that stores data as a series of memory cells that can only be accessed sequentially. SAM is nonvolatile memory, that is, stored data are retained even though power is removed. The bits on a memory device can be either individually addressed, or can be addressed in groups of 4, 16, 64, and so on. RAMs are classified as static or dynamic. Static RAMs, referred to as SRAMs, use flip flops as the storage cells. Dynamic RAMs, referred to as DRAMs, use capacitors of the storage cells but the charge in the capacitors must be periodically refreshed. The main advantage of DRAMs over SRAMs is that for a given device area, DRAMs provide much higher storage capacity. Read-Only Memories (ROMs) are memories in which the binary information is prewritten by special methods and the contents cannot be changed by the programmer or by any software. ROMs are nonvolatile. ROMs are used extensively as look up tables for different functions such as trigonometric functions, logarithms, square roots, etc. Programming instructions that are stored in a read-only memory unit rather than being implemented through software are known as firmware. ROMs are also used as character generators referred to as CGROMs. A programmable read-only memory (PROM) is a ROM that can be programmed by hardware procedures. PROMs can only be programmed once. Erasable programmable read-only memory (EPROM) can be erased and reprogrammed many times. To rewrite an EPROM, we must erase it first. To erase an EPROM, a special tool that emits an ultraviolet (UV) light at a certain frequency and specified duration. Electrically-erasable PROM (EEPROM) is a variant of the EPROM that can be erased and reprogrammed without the use of ultraviolet light. Flash memory is rewritable memory chip that holds its contents without power. It is used for easy and fast information storage in cell phones, digital cameras, and video game consoles. Flash memory works much faster than traditional EEPROMs A memory stick is a device that uses flash memory. It records various types of digital content, allows sharing of content among a variety of digital products, and it can be used for a broad range of applications. Digital Circuit Analysis and Design with an Introduction to CPLDs and FPGAs Orchard Publications
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Memory sticks are pre-formatted by the manufacturer and they are readily available for immediate use. The manufacturer provides re-formatting instructions in the event that the user wishes to reformat the memory stick at a later date. It is also possible to transfer data from a memory stick to a PC through a memory stick USB reader/writer. Cache memory is a fast storage buffer in the microprocessor of a computer. Caching refers to the arrangement of the memory subsystem in a typical computer that allows us to do our computer tasks more rapidly. Modern computers are bundled with both L1 and L2 caches. Virtual memory is a scheme where the operating system frees up space in RAM to load a new application. A scratch-pad memory is a usually high-speed internal register used for temporary storage of preliminary data or notes. It is fast SRAM memory that replaces the hardware-managed cache, and may be used to transfer variables from one task to another.
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Exercises
9.12 Exercises
1. We can expand the word size of a a RAM by combining two or more RAM chips. For instance, we can use two 32 8 memory chips where the number 32 represents the number of words and 8 represents the number of bits per word, to obtain a 32 16 RAM. In this case the number of words remains the same but the length of each word will two bytes long. Draw a block diagram to show how we can use two 16 4 memory chips to obtain a 16 8 RAM. 2. We can also expand the address size of a RAM by combining two or more RAM chips. Draw a block diagram to show how we can use two 16 4 memory chips to obtain a 32 4 RAM. 3. The outputs of the decoder in the ROM circuit below are active Low. List the words stored in that circuit.
V CC
X2 X1 X0 3 to 8 decoder Outputs are active Low
ROM inputs
Y3
Y2 ROM outputs
Y1
Y0
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9.13 Solutions to End-of-Chapter Exercises

1.
Address bus A3 A2 A1 A0 RW ME
RW 16 4 RAM ME
RW 16 4 RAM ME
Word size
B7 B6 B5 B4 B3 B2 B1 B0
The address range is from 0000 to 1111 , the same as with the individual RAMs, that is, 16 words, but the word size is now 8 bits, B 0 through B 7 where the four higher order bits of the word are stored in the first 16 4 RAM and the four lower order bits of the word are stored in the second 16 4 RAM. The memory enable ( ME ) input enables or disables the memory chip so that it will or will not respond to other inputs. Thus, when ME is logic 1, the memory chip is disabled and when ME is logic 0, the memory is enabled. The read/write ( R W ) input determines which memory operation is to be performed, that is, when R W is logic 1, a read operation is performed, and when R W is logic 0, a write operation is performed. Similarly, we can use eight 1024 1 RAM chips to form a 1024 8 RAM.
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2.
Address bus A4 A3 A2 A1 A0 RW
Solutions to End-of-Chapter Exercises
RW 16 4 RAM ME
RW 16 4 RAM ME
Word size
B3 B2 B1 B0
We need five address lines and since each memory chip has only four, we use the ME input as a fifth address shown as line A4 which is connected such that only one of the two RAM chips is enabled at any time. Thus, when A4 = 0 , the ME of the left RAM is enabled, the ME input of the right RAM is disabled, memory locations from 00000 to 01111 are accessed. Likewise, when A4 = 1 , the ME input of the left RAM is disabled, the ME input of the right RAM is enabled, and memory locations from 10000 to 11111 are accessed. Similarly, we can use eight 1024 1 RAM chips to form an 8192 1 RAM. 3.
Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 1000 0111 0011 1100 0000 1111 1000 0101
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JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL

9.1 Random-Access Memory (RAM)

ta Figure 9.1. Access time defined

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Chapter 9 Memory Devices

Data inputs outputs

Figure 9.2. Block diagram of a typical RAM device

8192 8192 cell matrix

D1 Data flow D 2 controller DN Enable R W

Data inputs outputs

Figure 9.3. A 64M words by 1 bit RAM device

Read-Only Memory (ROM)

9.2 Read-Only Memory (ROM)

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Chapter 9 Memory Devices

X0 Outputs are active Low Y3 Y2 Y1 Y0

Figure 9.4. Simplified ROM circuit

Figure 9.5. Simplified resistor-diode circuit

Read-Only Memory (ROM)

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Chapter 9 Memory Devices

9.3 Programmable Read-Only Memory (PROM)

Figure 9.6. Characters in a typical CGROM

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Erasable Programmable Read-Only Memory (EPROM)

X2 X1 X0 3 to 8 decoder Outputs are active Low

Figure 9.7. A simplified illustration of a typical PROM

9.4 Erasable Programmable Read-Only Memory (EPROM)

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Chapter 9 Memory Devices

9.5 Electrically-Erasable Programmable Read-Only Memory (EEPROM)

9.6 Flash Memory

9.7 Memory Sticks

9.8 Cache Memory

9.9 Virtual Memory

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Chapter 9 Memory Devices

9.10 Scratch Pad Memory

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Chapter 9 Memory Devices

X2 X1 X0 3 to 8 decoder Outputs are active Low

JJM/IT/IT-Portal/2011/DIL JJM/IT/IT-Portal/2011/DIL Chapter 9 Memory Devices

9.13 Solutions to End-of-Chapter Exercises

Solutions to End-of-Chapter Exercises

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