In this lecture:

Lecture 12: Finite State Machines

Dr Pete Sedcole
Department of Electrical & Electronic Engineering • Finite State Machines (FSMs)
Imperial College London
http://cas.ee.ic.ac.uk/~nps/
• FSM design procedure

E1.2 Digital Electronics 1 12.1 21 November 2008 E1.2 Digital Electronics 1 12.2 21 November 2008

Design of a synchronous binary counter FSM design procedure 1

CLOCK C1
• Step 1: start with the transition table of the flip-flops to be used in
D2 A the FSM
From the last combinational 1D
circuit D1 B
lecture: D0 C
? Output D-type FF JK-type FF
transition inputs inputs D CLK Output
required D J K 0 ↑ 0
1 ↑ 1
0 to 0 0 0 X
• How do we design the combinational circuit? 0 to 1 1 1 X J K CLK Output
• This counter is an example of a Finite State Machine (FSM) 0 0 ↑ Q
1 to 0 0 X 1
• The following procedure can be used for any FSM 1 0 ↑ Q=1
1 to 1 1 X 0 0 1 ↑ Q=0
1 1 ↑ Q

E1.2 Digital Electronics 1 12.3 21 November 2008 E1.2 Digital Electronics 1 12.4 21 November 2008
 FSM design procedure 2 FSM design procedure 3
A\BC 00 01 11 10
• Step 2: for each state variable in the state transition table, construct For this example, D2 0 0 0 1 0
Karnaugh maps for each input in the flip-flop transition table we will use 1 1 1 0 1
D flip-flops
Current state Next state D2, D1, and D0
For the 3-bit binary counter A\BC 00 01 11 10
A B C A+ B+ C+ implement the
example, there are 3 state bits. 0 0 1 0 1
0 0 0 0 0 1 next values of D1 1 0 1 0 1
0 0 1 0 1 0 If we use D flip-flops, there will be A, B, and C
0 1 0 0 1 1 3 “next-state” functions to respectively
0 1 1 1 0 0 implement.
A\BC 00 01 11 10
1 0 0 1 0 1 If we use JK flip-flops, we need K- D0 0 1 0 0 1
1 0 1 1 1 0 maps for both inputs of each flip- 1 1 0 0 1
1 1 0 1 1 1 flop, which would be 6 Boolean
1 1 1 0 0 0
functions.
E1.2 Digital Electronics 1 12.5 21 November 2008 E1.2 Digital Electronics 1 12.6 21 November 2008

FSM design procedure 4 FSM design procedure 5

• Step 3: extract the Boolean expressions from the K-maps • Step 4: implement using combinational logic

A\BC 00 01 11 10
0 0 0 1 0
1 1 1 0 1 D 2 = A BC + AB + AC
CLOCK
A\BC 00 01 11 10 C1
0 0 1 0 1 D1 = B C + BC = B ⊕ C D2 A
1 0 1 0 1 1D
D1 B
D0 C
A\BC 00 01 11 10
0 1 0 0 1 D0 = C
1 1 0 0 1

E1.2 Digital Electronics 1 12.7 21 November 2008 E1.2 Digital Electronics 1 12.8 21 November 2008
 Design of arbitrary code counters Example
• Design a 3-bit counter to count the decimal sequence:
0, 2, 5, 6, 0, 2, 5, …
• It may be necessary to design counters that count sequences other
than binary numbers
Decimal Q2 Q1 Q0
• Examples: Counting 0 0 0 0
– counters which never reach their maximum value, such as sequence: 2 0 1 0
a zero-to-nine counter (which uses 4 bits) 5 1 0 1
– counters which follow a specific code, such as a Gray Code 6 1 1 0
• The design procedure presented for binary counters can be
extended to arbitrary code counters
State diagram: 000 010 101 110

E1.2 Digital Electronics 1 12.9 21 November 2008 E1.2 Digital Electronics 1 12.10 21 November 2008

Current state Next state

State transition Q2 Q1 Q0 Q2+ Q1+ Q0+ Undefined states as “don’t care”

table: 0 0 0 0 1 0
0 1 0 1 0 1
• What about states 001, 011, 1 0 1 1 1 0 Circuit diagram: RESET R
100, 111? 1 1 0 0 0 0 CLOCK C1

• These we call undefined states D0 Q0

combinational 1D
– what happens if the circuit gets into an undefined state, for circuit D1 Q1
example at power-up? ? D2 Q2
• Two approaches:
1. Use a reset signal to ensure the FSM enters the “zero” state at
power-up, treat undefined states as “don’t care”
2. Design the FSM to explicitly enter the “zero” state from
undefined states

E1.2 Digital Electronics 1 12.11 21 November 2008 E1.2 Digital Electronics 1 12.12 21 November 2008
 Undefined states as “don’t care” Undefined states to “zero” state
Current state Next state
Q2\Q1Q0 00 01 11 10
0 0 X X 1 Q2 Q1 Q0 Q2+ Q1+ Q0+
Current state Next state D2:
1 X 1 X 0 0 0 0 0 1 0
Q2 Q1 Q0 Q2+ Q1+ Q0+ 0 0 1 0 0 0 000
000
0 0 0 0 1 0 Q2\Q1Q0 00 01 11 10 0 1 0 1 0 1
0 1 0 1 0 1 0 1 X X 0 011
D1: 0 1 1 0 0 0
1 X 1 X 0
1 0 1 1 1 0 1 0 0 0 0 0 000 010 101 110
1 1 0 0 0 0 Q2\Q1Q0 00 01 11 10 1 0 1 1 1 0 001
D0: 0 0 X X 1 1 1 0 0 0 0
1 X 0 X 0 1 1 1 0 0 0

D 2 = Q0 + Q 2.Q1 Modified state diagram

Modified state transition table
D1 = Q1
D0 = Q 2.Q1
E1.2 Digital Electronics 1 12.13 21 November 2008 E1.2 Digital Electronics 1 12.14 21 November 2008

Undefined states to “zero” state Undefined states to “zero” state

Q2\Q1Q0 00 01 11 10 D 2 = Q 2.Q1.Q0 + Q 2.Q1.Q0 Q 2.Q1.Q0

D2: 0 0 0 0 1
1 0 1 0 0 D1 = Q 2.Q1.Q0 + Q 2.Q1.Q0
Q2\Q1Q0 00 01 11 10 D0 = Q 2.Q1.Q0 CLOCK
D1: 0 1 0 0 0 C1
1 0 1 0 0
D2 Q2
1D
Q2\Q1Q0 00 01 11 10 The terms D1 Q1
D0: 0 0 0 0 1 Q 2.Q1.Q0 Q 2.Q1.Q0 D0 Q0
1 0 0 0 0 can be reused to simplify
the circuitry

This approach produces more complicated

circuits, but they are more robust Q 2.Q1.Q0
E1.2 Digital Electronics 1 12.15 21 November 2008 E1.2 Digital Electronics 1 12.16 21 November 2008
 A +: A\BC 00 01 11 10
Current state Next state 0 0 0 1 0
Implementing an FSM with JK flip-flops A B C A+ B+ C+
J2
1 X X X X
A\BC 00 01 11 10
0 0 0 0 0 1 K2 0 X X X X
The full 3-bit binary counter from earlier: 0 0 1 0 1 0 1 0 0 1 0
Current state Next state
A B C A+ B+ C+ 0 1 0 0 1 1
0 1 1 1 0 0 B +: A\BC 00 01 11 10
0 0 0 0 0 1 0 0 1 X X
0 0 1 0 1 0 1 0 0 1 0 1 J1
CLOCK C1 1 0 1 X X
0 1 0 0 1 1 1 0 1 1 1 0
J2 1J A A\BC 00 01 11 10
0 1 1 1 0 0 K2 1 1 0 1 1 1 K1 0 X X 1 0
1K
combinational J1 1 1 1 0 0 0 1 X X 1 0
1 0 0 1 0 1 B
circuit K1
1 0 1 1 1 0 ? J0 Transition J K
C C +: A\BC 00 01 11 10
1 1 0 1 1 1 K0 0 1 X X 1
0 to 0 0 X J0
1 1 1 0 0 0 1 1 X X 1
0 to 1 1 X
1 to 0 X 1 A\BC 00 01 11 10
K0 0 X 1 1 X
1 to 1 X 0 1 X 1 1 X
E1.2 Digital Electronics 1 12.17 21 November 2008 E1.2 Digital Electronics 1 12.18 21 November 2008

Binary counter circuit using JK flip-flops D and JK flip-flop comparison

The Boolean equations for CLOCK CLOCK
all Js and Ks: D flip-flop circuits are
C1 usually easier to design C1

J 2 = K 2 = B.C J2
J2 1J A
A K2
J 1 = K1 = C K2
1J
1K J1
1K

B
J1 K1
J0 = K0 =1 K1
B
1 J0 C
1 K0
In this case, the J and K 1 J0 C CLOCK
C1
inputs to each FF happen to 1 K0
D2 A
be the same – this is not D1
1D
B
usually the case D0 C JK flip-flop circuits usually
use less combinational logic
• The Karnaugh maps using JK flip-flops have a lot of “don’t cares”
• The logic is usually simpler than circuits that use D flip-flops
In VLSI integrated circuits, D flip-flops are preferred because
• But have to work out twice as many Boolean equations they are smaller, faster, and require fewer wires
E1.2 Digital Electronics 1 12.19 21 November 2008 E1.2 Digital Electronics 1 12.20 21 November 2008
 Implementing an FSM with ROM Implementing an FSM with ROM
Address A[2:0] Data D[2:0]
A2 A1 A0 D2 D1 D0
ROM programming table
000 010 101 110 0 0 0 0 1 0
All other locations contain 000 0 1 0 1 0 1
1 0 1 1 1 0
RESET R 1 1 0 0 0 0
CLOCK C1
RESET R
D0 Q0 CLOCK C1
1D
ROM D1 Q1 Q0
A0 D0
D0 1D
D2 Q2
23x3 D1 Q1
A1 D1
ROM D2 Q2
A2 D2

E1.2 Digital Electronics 1 12.21 21 November 2008 E1.2 Digital Electronics 1 12.22 21 November 2008