In this lecture:

Lecture 11: Registers and counters

Dr Pete Sedcole
Department of Electrical & Electronic Engineering • Registers and shift registers
Imperial College London
• Counters: synchronous and asynchronous
http://cas.ee.ic.ac.uk/~nps/

(Floyd 7.4, 8.1, 9.1)

(Tocci 5.17 – 5.19, 7.1, 7.19 – 7.20)

E1.2 Digital Electronics 1 11.1 19 November 2008 E1.2 Digital Electronics 1 11.2 19 November 2008

Registers Example symbol and implementation

• A register is a digital electronic circuit capable of storing several bits

CLEAR
of data R
CLOCK C1
– normally made from D flip-flops
D0 Q0
– normally bits are moved in and out all at once (i.e., in parallel) 1D
D1 Q1
– must have a CLOCK input
D2 Q2
– can also have RESET (synchronous) or CLEAR (asynchronous)
inputs
D0 Q0 D1 Q1 D2 Q2
CLEAR 1D 1D 1D
R
The values on inputs CLOCK C1 C1 C1 C1
D0, D1, D2, are The stored values
stored in the register
D0 1D Q0 are present on the R R R

on the positive edge

D1 Q1 register outputs CLOCK
of the CLOCK
D2 Q2 Q0, Q1, Q2 CLEAR

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 Shift registers Shift register operation

• In a shift register, bits move along the register from one flip-flop to
the next flip-flop, like a queue • Bits are input serially into Din
• Many applications, for example: • On the positive edge of the clock, each bit moves right by one flip-
– Conversion of data between parallel format and bit-serial format flop
– Random number generators • The data can be read at any time from the outputs Q[2:0]
• Construction: • Therefore 3 bits can be entered in serial and read out in parallel
format after 3 clock cycles
Q0 Q1 Q2
Din 1D 1D 1D
C1 C1 C1 • Also note that all the flip-flops can be asynchronously reset
R R R • It is also possible to have versions where all flip-flops can be loaded
with data in parallel and read out in serial
CLOCK
CLEAR

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Q0 Q1 Q2 A pseudo-random number generator

Din 1D 1D 1D
C1 C1 C1

R R R Q0 Q1 Q2 Q3
Din OUT
1D 1D 1D 1D
CLOCK
C1 C1 C1 C1
CLEAR
S S S S
CLOCK
CLOCK PRESET

CLEAR • A shift register where the input is a function of the state

Din • The value of the OUT signal will be:

Q0 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, and then repeat

Q1
• A shift register of N-bits can be used to generate a pseudo-random
Q2 sequence of 2N-1 bits before repeating
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 Binary counters Recall: frequency divider
Decimal Q2 Q1 Q0
0 0 0 0
CLOCK
1 0 0 1 CLOCK1
1D Q
Q0 2 0 1 0
Q
3 0 1 1 Q CLOCK2
Q1 4 1 0 0 CLOCK1 C1 Q
5 1 0 1
Q2
6 1 1 0
• A 3-bit binary counter 7 1 1 1
Produces an output signal that is half the
• Note that in frequency: CTR3 frequency of the input clock signal
– Q0 is half CLOCK
Q[2:0]
– Q1 is half Q0
– Q2 is half Q1 CLOCK +
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Asynchronous binary counter Ripple counter operation

Q0 Q1 Q2 Q0 Q1 Q2
1D Q 1D Q 1D Q 1D Q 1D Q 1D Q

Q Q Q Q Q Q
CLOCK C1 C1 C1 CLOCK C1 C1 C1

• This counter is asynchronous: the flip-flops are not all clocked with
CLOCK
the same clock signal
• This counter is also known as a ripple counter since changes Q0
“ripple” from one end of the counter to the other
Q1
• Can also be implemented with JK flip-flops
Q2

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 Limitations of asynchronous ripple counters Synchronous binary counters

• It takes a small but non-zero amount of time for each flip-flop to
change state
– typically the “Clock-to-Q” time is about 10ns
• It takes time for the changes to ripple through the whole counter
– for an n-bit counter, it would take ~ n x 10ns
– for a 3-bit counter, this is 30ns
– so the maximum clock frequency is 1/30ns = 33.3MHz
• All flip-flops are clocked with the same signal
– therefore all outputs change simultaneously
• The sequence of the count is controlled by combinational logic
– this is sometimes called the state sequence
– note that synchronous binary counters use both
sequential and combinational elements

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Example: 3-bit up-counter Implementation

Use a register of flip-flops and logical combinations of state variables
000 001 010 011 100 101 110 111
CLOCK C1

A+ A
State diagram Current state Next state combinational 1D
circuit B+ B
Example using
A B C A+ B+ C+ ? C+ C
D flip-flops:
0 0 0 0 0 1

From the state diagram, we can 0 0 1 0 1 0

construct the state transition table. 0 1 0 0 1 1
0 1 1 1 0 0 The design task is to create the combinational circuit
Here, label the state variables ABC,
1 0 0 1 0 1
where A is the MSB and C is the LSB • it needs to supply the next input A+, B+, C+, so that on the
1 0 1 1 1 0
next clock the correct sequence is followed
1 1 0 1 1 1
1 1 1 0 0 0 • other flip-flops could be used, such as JK flip-flops
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