In this lecture:

Lecture 10: State diagrams

Dr Pete Sedcole
Department of Electrical & Electronic Engineering • Introduction to Moore and Mealy state diagrams
Imperial College London
• State tables
http://cas.ee.ic.ac.uk/~nps/

E1.2 Digital Electronics 1 10.1 13 November 2008 E1.2 Digital Electronics 1 10.2 13 November 2008

State diagrams Moore state diagram of an S-R flip-flop

• A state diagram is used for a synchronous circuit. It shows: Transition from
– the circuit state S Q state a to state b
Inputs: SR when inputs SR = 10
– the possible transitions between states
CLK Outputs: Q
– the values of the circuit outputs
R SR Transitions
• There are two possible models
between states
– Moore and Mealy SR+SR SR+SR occur at the
a/0 b/1
• We will look at the Moore model first: positive edge
of the clock
– a circle is drawn for each state SR
– the value of the state and the outputs are written inside each
circle State a:
Output Q is 0
– arrows are drawn to show possible transitions between states State b:
Transition from Output Q is 1
– the arrows are labelled with the required input conditions for the state b to state a
transition to occur when inputs SR = 01

E1.2 Digital Electronics 1 10.3 13 November 2008 E1.2 Digital Electronics 1 10.4 13 November 2008
 Example: 2-bit Gray Code “counter” State Tables
E
GCC
• A state table is a tabular form of the state diagram
E D0
D1 a/00 • There is one row for each possible state
E E • It shows the next state that will be entered (on the next clock edge)
CLK for all possible combinations of inputs
• Example:
E d/10 b/01 E

SR Present Next state

E state inputs: SR
• When enabled (E=1) cycles a/0 b/1 00 01 10 11
E
through the 2-bit Gray Code c/11 a a a b X
• Pauses when disabled (E=0) SR+SR SR SR+SR b b a b X

E1.2 Digital Electronics 1 10.5 13 November 2008 E1.2 Digital Electronics 1 10.6 13 November 2008

Assigned state table (S-R flip-flop) Boolean expression from assigned state table
• The assigned state table differs from the state table by showing the
flip-flop outputs assigned to each state instead of the state label
• Ordering the state table inputs like a Karnaugh map enables it to be
• Example for SR flip-flop used directly as a K-map
Present Next output Q+ • It is used to find the Boolean equations that describe the
output inputs: SR next state Q+ from the values of the present state Q and the inputs
Q 00 01 11 10
0 0 0 X 1 Q\SR 00 01 11 10
1 1 0 X 1 0 0 0 X 1
1 1 0 X 1
The input values here have been ordered just like a Karnaugh Map

If the output of the circuit is 1, and the inputs are S=1, R=0: • For the example of the SR flip-flop:
what will be the output of the circuit after the next +ve clock edge? – the next state Q+ is a function of Q, S, R

Answer: 1
E1.2 Digital Electronics 1 10.7 13 November 2008 E1.2 Digital Electronics 1 10.8 13 November 2008
The Karnaugh Map for the S-R flip-flop JK flip-flop states
S Q
Q\SR 00 01 11 10
0 0 0 X 1 J Q JK+JK
CLK
1 1 0 X 1
CLK 1/0 2/1
R Q
Boolean expressions are found by grouping 1s as usual: K Q JK+JK JK+JK JK+JK

Moore state diagram

Q + = S + QR
Present Next output Q+
output inputs: JK
Q 00 01 11 10
0 0 0 1 1
Such equations are called characteristic equations 1 1 0 0 1

Assigned state table

E1.2 Digital Electronics 1 10.9 13 November 2008 E1.2 Digital Electronics 1 10.10 13 November 2008

JK characteristic equation D flip-flop

D
D Q
Q + = JQ + K Q D 1/0 2/1 D
CLK Q
D
• when J=1, K=0 then Q+ = Q + Q = 1
• when J=0, K=1 then Q+ =0 Symbol Moore state diagram
• when J=1, K=1 then Q+ = Q (= toggle)
Present Next output Q+
output
• The characteristic equation clearly and simply describes the circuit Q 0 1 Q+ = D
operation 0 0 1
1 0 1
• Note that JK flip-flops are usually built from master-slave latches
and not D flip-flops Assigned state table Characteristic equation

E1.2 Digital Electronics 1 10.11 13 November 2008 E1.2 Digital Electronics 1 10.12 13 November 2008
 Mealy state diagrams Mealy state diagram of a JK flip-flop

• Very similar to Moore state diagrams: Inputs: J K inputs (JK)

Outputs: Q output (Q)
– circles for states, arrows for transitions
– circles are labelled with states J Q 10/0, 11/0
– arrows are labelled with conditions for transition to occur 00/0 00/1
CLK a b
• However: 01/0 10/1
– the circuit outputs are labelled on the transitions K Q 01/1, 11/1
– this means that the value of the outputs depend on the values of
the inputs as well as the present circuit state
Note that here the input values are shown in State label
binary rather than Boolean expressions. This
can be done for Moore state diagrams as well.

E1.2 Digital Electronics 1 10.13 13 November 2008 E1.2 Digital Electronics 1 10.14 13 November 2008

Summary: latches, flip-flops

• A latch is level-sensitive: the outputs change in response to a
change in the input voltage level
• A flip-flop is edge-sensitive: the output only changes in response to
a clock edge (either negative or positive)
• Flip-flop characteristic equations:

SR JK D
+ + +
Q = S + QR Q = JQ + K Q Q =D

• SR flip-flops are not generally used because of the invalid input

combination SR=11
• Circuits implemented using JK flip-flops usually have fewer gates
• D flip-flops use less wiring as they only have one input

E1.2 Digital Electronics 1 10.15 13 November 2008