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E1.2 Digital Electronics 1 9.1 13 November 2008 E1.2 Digital Electronics 1 9.2 13 November 2008
E1.2 Digital Electronics 1 9.3 13 November 2008 E1.2 Digital Electronics 1 9.4 13 November 2008
Example Synchronous and asynchronous
E1.2 Digital Electronics 1 9.5 13 November 2008 E1.2 Digital Electronics 1 9.6 13 November 2008
E1.2 Digital Electronics 1 9.7 13 November 2008 E1.2 Digital Electronics 1 9.8 13 November 2008
A S-R latch built from NAND gates S-R latch: SET operation
1 1
1 1
SET 0 Q SET 1 Q 0 0
1 t0 t1 1 t0 t1
0 SET Q 0 SET Q
t0 t1 t0 t1
Q Q
1 1
RESET 1 RESET 0
Q Q
RESET RESET
1 1 1 1
0 0
This NAND gate latch has two possible stable states when t0 t1 t0 t1
SET = RESET = 1
A negative pulse on SET puts the latch in HIGH (SET) state
E1.2 Digital Electronics 1 9.9 13 November 2008 E1.2 Digital Electronics 1 9.10 13 November 2008
S-R latch: RESET operation Set-Reset latch symbol and truth table
1 1
0 0 SET Q S R Output
S Q 1 1 No change
1 t0 t1 1 t0 t1
SET Q SET Q 0 1 Q=1
1 0 Q=0
Q R Q 0 0 Invalid
RESET
1 Q 1 Q
0 RESET 0 RESET
1 1 SET
t0 t1 t0 t1
0 0
t0 t1 RESET
t0 t1
E1.2 Digital Electronics 1 9.11 13 November 2008 E1.2 Digital Electronics 1 9.12 13 November 2008
S-R latch to debounce a switch A NOR gate S-R latch
SET Q S R Output
S Q 0 0 No change
1 0 Q=1
0 1 Q=0
Q R Q 1 1 Invalid
RESET
SET
RESET
E1.2 Digital Electronics 1 9.13 13 November 2008 E1.2 Digital Electronics 1 9.14 13 November 2008
E1.2 Digital Electronics 1 9.15 13 November 2008 E1.2 Digital Electronics 1 9.16 13 November 2008
Clock signals and flip-flops Set-Reset (S-R) flip-flop
Synchronous digital systems: “positive edge” or
“positive-going transition” (PGT) S R CLK Output
S Q
• the state bits of the circuit all Clocked flip-flop: 0 0 ↑ No change
change simultaneously 1
the output only CLOCK CLK 1 0 ↑ Q=1
• the changes occur at fixed 0 changes at the 0 1 ↑ Q=0
points in time “negative edge” or positive edges of R Q 1 1 ↑ Invalid
• the control signal which “negative-going transition” (NGT) the clock
indicates it is time to change is
called the clock Flip-flops are CLOCK
sometimes called
Q Q
data and edge-triggered S
Flip-flop control inputs
symbols:
R
CLK CLK
Q Q
CLK is activated by Q
a positive edge CLK is activated by
E1.2 Digital Electronics 1 9.17 a negative edge 13 November 2008 E1.2 Digital Electronics 1 9.18 13 November 2008
R
RESET
X CLK X
CLK
CLK* CLK*
Edge detector
circuits for both
positive-edge CLK CLK
and negative-
edge flip-flops X X
CLK* CLK*
E1.2 Digital Electronics 1 9.19 13 November 2008 E1.2 Digital Electronics 1 9.20 13 November 2008
Internal circuitry of a J-K flip-flop D flip-flop
E1.2 Digital Electronics 1 9.21 13 November 2008 E1.2 Digital Electronics 1 9.22 13 November 2008
CLOCK
DATA
time
tS tH
The data/control inputs to
the flip-flop must be stable: DATA D Q
D Q CLOCK1
Q
CLOCK1 CLK CLOCK2
Q Q
E1.2 Digital Electronics 1 9.25 13 November 2008 E1.2 Digital Electronics 1 9.26 13 November 2008