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E1.2 Digital Electronics 1 8.1 7 November 2008 E1.2 Digital Electronics 1 8.2 7 November 2008
Memory terminology
E1.2 Digital Electronics 1 8.3 7 November 2008 E1.2 Digital Electronics 1 8.4 7 November 2008
A ROM device example
Read-only Memory (ROM)
64x1 bit ROM +5 Volts
– the data is kept even when the power supply to the circuit is A1
3 11 19 27 35 43 51 59
turned off A2
4 12 20 28 36 44 52 60
– the data can be read again after the power is turned back on 5 13 21 29 37 45 53 61
• Applications: 7 15 23 31 39 47 55 63
MUX
– permanent storage of programmes for microprocessors A3 7
OUT
.
.
– look-up tables of data A4 .
0
E1.2 Digital Electronics 1 8.5 7 November 2008 E1.2 Digital Electronics 1 8.6 7 November 2008
A ROM cell
Row
e
• 64 x 1 bit ROM example: rag
Sto
– 6 address inputs: half are used for selecting the row, and half for 0 or 1 Column
selecting the column
– the row-select decoder energises all 8 cells in one row
– the column-select MUX chooses just one column signal to pass
through to the output • A voltage level is stored to represent a 0 or 1
– column lines are normally “pulled high” by resistors • If the “row-line” is addressed, the switch closes and the stored
– a ROM cell programmed with a 0 pulls the line low voltage appears on the “column-line”
• The switch is implemented with a transistor (typically a MOSFET)
E1.2 Digital Electronics 1 8.7 7 November 2008 E1.2 Digital Electronics 1 8.8 7 November 2008
Programmable ROMs
Mask Programmed ROM • MROM are inflexible – the data are fixed when the chips are
fabricated
• In a Mask Programmed ROM (MROM): • Programmable ROMs (PROMs) can be programmed after
– The data to be stored in the ROM is fixed at the time of manufacture
manufacture – A fuse is used instead of a wire link
– The presence or absence of a wire determines whether a cell is – Certain types of fuses can be reset under UV light
programmed with a 0 or a 1 • Electrical Erasable PROMs (EEPROMs) use another transistor
instead of a fuse
5V data stored in a
PROM cell EEPROM cell gate capacitance
row line row line
stores column
0 0 stores 0 line 0 column 0
1 line
E1.2 Digital Electronics 1 8.9 7 November 2008 E1.2 Digital Electronics 1 8.10 7 November 2008
Different ROM technologies • A 2n x m ROM has n inputs (the address) and m outputs
• E.g.: 24 x 6
Addr[3:0] 16x6 Data[5:0]
ROM
E1.2 Digital Electronics 1 8.13 7 November 2008 E1.2 Digital Electronics 1 8.14 7 November 2008
PAL architecture
A0 A1 A2 A3 A4 A5 A6 A7
Detail of AND gates in PALs
&
f = A 0. A1. A 3 + "
All inputs and their &
complements are
&
provided >1 &
&
To simplify the f
diagram, only one &
input line is drawn ≥1 f
&
for each AND gate
A dot indicates an & 1 1 1 1
active connection &
E1.2 Digital Electronics 1 8.17 7 November 2008 E1.2 Digital Electronics 1 8.18 7 November 2008