MIDDLE EAST TECHNICAL UNIVERSITY NORTHERN CYPRUS CAMPUS

ELECTRICAL AND ELECTRONICS ENGINEERING PROGRAM

EEE-445 (3-0)3 Fall-2009

COMPUTER ARCHITECTURE I

Instructor’s Name Office Phone e-mail

ALİ MUHTAROĞLU R-216 661 2933 amuhtar@metu.edu.tr

Course Schedule: T. 13:40–15:30 (S-105); Th. 9:40–10:30 (S-106)

Office Hours : W. 9:00–10:30 or by appointment (R-216)
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Main Text: Patterson&Hennessy, “Computer Organization and Design” (4 Ed.), Kaufmann, 2008.
Will use plenty of lecture notes since no single text has the full coverage.
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Auxiliary Text: Stallings, “Computer Organization & Architecture” (7 Ed.), Pearson, 2006.
Mano & Kime, “Logic and Computer Design Fundamentals”, 4th Ed., Prentice Hall, 2008.
Brown & Vranesic, “Fund. Of Dig. Logic with VHDL Design” (2nd Ed.), McGraw Hill, 2005.

Catalog Description: Asynchronous logic system. Algorithmic state machines. CPU organization.
Construction of arithmetic logic unit. Process control architectures. Instruction modalities.
Microprogramming. Bit slicing. Prerequisite: EEE 248 or consent of the department.

Course Objectives: We will learn about the components of a computer system organization, and
instruction set architectures. We will build on the knowledge of microcontroller macro-coding from EEE
347, and study hardware and micro-programmed control for single- and multi-cycle datapath design. I/O
organizations, asynchronous logic design concepts will be covered as time allows this term. EEE-446
(next term) will follow from where we left off. Those without EEE 347 background can take the course, but
let the instructor know in advance.

Course Outline (Tentative):

Week Week HW HW
LECTURE
# Starts Out Due
1 28-Sep Intro. to Computer System Architecture and Organization
2 5-Oct Computer Components and Program Concept; Instructions 1
3 12-Oct Instruction Set Architecture Design 2 1
4 19-Oct Instruction Sets and Addressing Modes 3 2
5 26-Oct Addressing Modes; Program Control; Data Types
6 2-Nov Midterm #1; Sequential Design Review
7 9-Nov Fetch-Decode-Execute cycle 4 3
8 16-Nov Single-Cycle Datapath for Fetch-Decode-Execute 5 4
9 23-Nov Single-Cycle Datapath & Control for Fetch-Decode-Execute 6 5
10 30-Nov Multi-Cycle Datapath & Control Design
11 7-Dec Microprogrammed Control 7 6
12 14-Dec Microprogrammed Control Examples 8 7
13 21-Dec Midterm #2; Input/Output
14 28-Dec Interrupts, Traps 9 8
15 4-Jan Buses; PCI example 9
16 11-Jan Final’s week
17 18-Jan Final's week
Note: No class on 29-10-09.
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Grading: Midterm 1 : 20% Tentatively on November 3 in class
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Midterm 2 : 25% Tentatively on December 22 in class
Final : 35% Date/Time/Place To Be Determined
H.W. + Attendance : 20% Late assignments penalized 20% per week day

 Brush up on C programming language and VHDL for homeworks/projects.

 Those who fail to follow the rules of academic honesty will fail the class. ALL course work
should be completed independently.
 Attendance is higly recommended to do well in the class.
 Will use METU-Online to post HWs, Labs, solutions, lecture notes, announcements, etc.