CSC506 Cache Coherence HW due Wednesday, June 16, 1999

Question 1: Describe the difference between strong consistency and weak consistency in multiprocessor systems. Strong consistency requires that ALL instructions must have globally consistent ordering. Weak consistency requires that only designated SYNCHRONIZING instructions must have globally consistent ordering with all instructions.

Question 2: A 4-way SMP configuration implements write-back cache using the MESI (Modified Exclusive Shared Invalid) algorithm for cache coherency. Assume that location 1E0 is not in any cache at the start of the following sequence. Show the state (M, E, S or I) for the line containing location 1E0 in each processor cache and the state in main memory after each operation. Also note any transfers to/from memory if any occur. For example, if Px has a snoop hit of Py reading a line while it is holding a dirty copy of the line, indicate Px writes line back, Py reads line under the Memory Transfers column. a) b) c) d) e) f) Processor 0 reads from location 1E0. Processor 0 writes to location 1E0. Processor 1 reads from location 1E0. Processor 2 reads from location 1E0. Processor 1 writes to location 1E0. Processor 3 writes to location 1E0.

Action P0 reads P0 writes P1 reads P2 reads P1 writes P3 writes

P0 E M S S I I

P1 I I S S M I

P2 I I I S I I

P3 I I I I I M

Mem V I V V I I

Memory Transfers P0 reads line.

P0 writes line back, P1 reads line. P2 reads line.

P1 writes line back, P3 reads line.

Question 3: A 2-way SMP configuration implements write-back cache using the MESI (Modified Exclusive Shared Invalid) algorithm for cache coherency. Each processor has 16 megabytes of addressable memory and a 2-way set-associative write-back cache with 256 sets and 16 bytes per line. The LRU replacement policy is used. Assume that each cache is empty when we start executing programs on the two processors, and they make the following sequence of references. Use the tables provided to give the tag, set, line number, MESI state, and data for non-empty cache lines, and the contents of memory after each step of the sequence. Be sure to fill in the complete contents of occupied cache lines and memory at each step. Use hexadecimal notation for all numbers.

Initial Memory Loc 7C3x 8C3x 9C3x 0 0000 0000 0000 Memory Data 4 8 0000 0000 0000 0000 0000 0000 C 0000 0000 0000

1. Processor 0 writes 1111 to location 8C34 Processor 0 cache Tag RAM Tag Set Line MESI 8 C3 0 M

0 0000

Data RAM 4 8 1111 0000

C 0000 Memory Loc 0 0000 0000 0000 Memory Data 4 8 0000 0000 0000 0000 0000 0000 C 0000 0000 0000

Processor 1 cache Tag RAM Tag Set Line MESI

Data RAM 4 8

7C3x 8C3x 9C3x

2. Processor 0 reads from location 7C34 Processor 0 cache Tag RAM Tag Set Line MESI 8 7 C3 C3 0 1 M E

0 0000 0000

Data RAM 4 8 1111 0000 0000 0000

C 0000 0000 Memory Loc 7C3x 8C3x 9C3x C 0 0000 0000 0000 Memory Data 4 8 0000 0000 0000 0000 0000 0000 C 0000 0000 0000

Processor 1 cache Tag RAM Tag Set Line MESI

Data RAM 4 8

3. Processor 1 writes 2222 to location 8C30 Processor 0 cache Tag RAM Tag Set Line MESI 8 7 C3 C3 0 1 I E

0 ---0000

Data RAM 4 8 ---0000 ---0000

C ---0000 Memory Loc 7C3x 8C3x 9C3x C 0000 0 0000 0000 0000 Memory Data 4 8 0000 1111 0000 0000 0000 0000 C 0000 0000 0000

Processor 1 cache Tag RAM Tag Set Line MESI 8 C3 0 M

0 2222

Data RAM 4 8 1111 0000

4. Processor 1 reads from location 7C34 Processor 0 cache Tag RAM Tag Set Line MESI 8 7 C3 C3 0 1 I S

0 ---0000

Data RAM 4 8 ---0000 ---0000

C ---0000 Memory Loc 7C3x 8C3x 9C3x C 0000 0000 0 0000 0000 0000 Memory Data 4 8 0000 1111 0000 0000 0000 0000 C 0000 0000 0000

Processor 1 cache Tag RAM Tag Set Line MESI 8 7 C3 C3 0 1 M S

0 2222 0000

Data RAM 4 8 1111 0000 0000 0000

5. Processor 1 reads from location 9C38 Processor 0 cache Tag RAM Tag Set Line MESI 8 7 C3 C3 0 1 I S

0 ---0000

Data RAM 4 8 ---0000 ---0000

C ---0000 Memory Loc 7C3x 8C3x 9C3x C 0000 0000 0 0000 2222 0000 Memory Data 4 8 0000 1111 0000 0000 0000 0000 C 0000 0000 0000

Processor 1 cache Tag RAM Tag Set Line MESI 9 7 C3 C3 0 1 E S

0 0000 0000

Data RAM 4 8 0000 0000 0000 0000

6. Processor 0 reads from location 8C3C Processor 0 cache Tag RAM Tag Set Line MESI 8 7 C3 C3 0 1 E S

0 2222 0000

Data RAM 4 8 1111 0000 0000 0000

C 0000 0000 Memory Loc 7C3x 8C3x 9C3x C 0000 0000 0 0000 2222 0000 Memory Data 4 8 0000 1111 0000 0000 0000 0000 C 0000 0000 0000

Processor 1 cache Tag RAM Tag Set Line MESI 9 7 C3 C3 0 1 E S

0 0000 0000

Data RAM 4 8 0000 0000 0000 0000

7. Processor 0 writes 3333 to location 8C3C Processor 0 cache Tag RAM Tag Set Line MESI 8 7 C3 C3 0 1 M S

0 2222 0000

Data RAM 4 8 1111 0000 0000 0000

C 3333 0000 Memory Loc 7C3x 8C3x 9C3x C 0000 0000 0 0000 2222 0000 Memory Data 4 8 0000 1111 0000 0000 0000 0000 C 0000 0000 0000

Processor 1 cache Tag RAM Tag Set Line MESI 9 7 C3 C3 0 1 E S

0 0000 0000

Data RAM 4 8 0000 0000 0000 0000