Overview of the Inter-Integrated Circuit (I2C) Bus

ECPE 4536

Microprocessor System Design II

Virginia Tech

The Inter-Integrated Circuit (I2C) Bus, developed and patented by Philips, is a simple, low-cost serial interface for connecting one or more microcontrollers and peripherals in an embedded system. Components available with an I2C Bus interface include microcontrollers, LCD drivers, I/O expanders, memory, analog-to-digital and digital-to-analog converters, clock/calendars, and application-specific ICs such as voice synthesizers, transcoders for infrared remote controls, picture-in-picture controllers, and frequency synthesizers for mobile telephones. The I2C Bus defines the signals, data formats, and protocols necessary for devices to communicate. This document provides information about the I2C Bus that will be needed for a project. It is not intended as a comprehensive description of the bus. Specifically, only basic addressing modes and the low-speed mode of operation are discussed in detail. +VDD +VDD C A C B Device a Device b Device c

Rp

Rp

SCL SDA Figure 1. Example I2C Bus system.

1. Basic Operation
A typical I2C Bus configuration is shown in Figure 1. The I2C Bus defines two signals (wires), SDA for serial data and SCL for serial clock, to carry information between devices. Each device is identified by a unique address. Each device can either transmit data or receive data. A device operates as either a master or as a slave. A master initiates data transfer, either to or from one or more slaves, and generates clock signals. The device addressed by the master is considered, at that time, to be a slave. For example, if microcontroller A (C A) in the figure addresses and sends data to Device a, perhaps an LCD driver, then C A is the master and Device a is the slave. In this case, C A generates the clock signal on SCL, sends the address, and sends the data. Suppose C A wanted to receive data from Device b, say a memory device. Then, as master, C A generates the clock signal on SCL and sends the address, but Device b sends data back to the microcontroller. The I2C Bus supports multiple masters, i.e. more than one device is capable of controlling the bus. In the example shown in the figure, both C A and C B can act as masters. The I2C Bus includes an arbitration scheme so that correct operation will occur if more than one master wants to use the bus at the same time. Note that the master and slave relationships are dynamic. For example, C B can address C A and send it data. In this case, C B acts as a transmitting master and C A acts as a receiving slave. Later, C A might address and send data to C B, in which case the master and slave roles are reversed. Clock generation is the responsibility of the master. However, slave devices can stretch clock cycles by holding the clock low. This allows devices of different speeds to be connected to the bus.

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2. SCL and SDA Characteristics

SCL and SDA are bidirectional lines. Any device acting as a master must be able to both drive and sense SCL and SDA. Any device acting as a slave must be able to sense SCL and drive and sense SDA. A slave may also drive SCL to stretch a clock cycle. SCL and SDA are connected to a positive supply voltage (VDD = +5 V for TTL logic) through pull-up resistors (RP = 2.7 K for our purposes) and are driven by open-collector devices (7407 TTL non-inverting open-collector drivers for our project). If any device outputs a low (0), then the signal is low. The signal is high (1) if and only if all devices are driving the signal high. Thus, SCL and SDA each implement a wired-AND function.

3. Data Transfer 3.1. Format

Figure 2 shows a data format for an I2C Bus transaction. The unit of information including start condition, address, data, acknowledgment, and stop condition is sometimes referred to as a frame and constitutes an atomic transfer as defined for the I2C Bus. A higher level protocol may use the I2C Bus to transfer multiple frames, but the I2C Bus itself defines no relationship between different frames.
8 S Sr A P = start condition = restart = acknowledge = stop condition S start byte 1 7 1 1 8 data 1 A 8 1 A P

A Sr address

R/ A W

...

data

Figure 2. Data transfer format for low-speed mode. As shown in the figure, a master generates a start condition (S) to change the bus from an idle state to a busy state and begin the transaction. A master cannot begin a frame unless the bus is idle. If two or more masters attempt to use the bus at approximately the same time, an arbitration procedure determines which master may use the bus. Section 5 describes arbitration. For a low-speed mode transfer (as used in the project), the start condition is followed by a special start byte (00000001B) and dummy acknowledgment. Another start condition, called a repeated start or restart (Sr), is generated immediately after the dummy acknowledgment (A). The start byte permits a slow device, such as a microprocessor implementing the I2C Bus interface in software, to poll for bus activity less often. The slow device can detect bus activity at any point during the start byte and then detect the restart. Following the restart, the master sends a byte that consists of a seven-bit address and a read/write (R / W ) command bit. Each device can compare the transmitted address to its own address. If they are equal, then the device is being addressed as a slave. If they are not equal, then the device ignores the rest of the transaction. The R / W bit indicates if the master wishes to receive data (R / W =1) or transmit data (R / W =0). The selected slave device follows the address and read/write byte with an acknowledgment (A). A=0 is a positive acknowledgment that indicates to the master that the slave is responding. If A=1, then the master must assume that the addressed slave is not responding. The I2C Bus does not define error recovery procedures. Zero or more data bytes follow. The I2C Bus does not define a maximum number of bytes that can be transferred in one frame. The master drives the data on SDA for a write operation and the slave drives data on SDA for a read operation. Each data byte is followed by an acknowledgment. The acknowledgment is always generated by the device receiving data, i.e. the slave for a write and the master for a read.

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When the master is finished sending or receiving data, it generates a stop condition (P) and the bus returns to an idle state. The master will also generate a stop condition in the event of an error. For example, if the slave does not respond to the address sent by the master, then the master generates a stop condition.

3.2. Start Condition

Normally the SDA line must be held stable during a high clock (SCL) pulse. The start condition (S) and stop condition (P) are two exceptions. A high-to-low transition on SDA while SCL is high indicates a start. The start condition is always generated by a master. Figure 3 shows a low-speed mode data transfer. The start condition (S) occurs at the beginning of the transfer. A repeated start condition (Sr) occurs after the start byte.

SDA

R/W

SCL S

2-7 start byte

9 A Sr

1-7

9 A

1-7

9 A P

address

data byte(s)

Figure 3. Low-speed mode data transfer.

3.3. Bit Transfer

Figure 4 shows a bit transfer on the I2C Bus. Data on SDA remains valid while the clock, SCL, is high. Certain timing constraints must be met, as described in Section 8. If the master is transferring data on a write operation, it will pull the clock low, drive the next bit onto SDA, and then release the clock (set it high). The master will continue to drive SDA until it again pulls SCL low.

SDA SCL data cannot change data can change

Figure 4. Bit transfer. If the slave is transferring data on a read operation, it will wait until the master pulls the clock low and then drive the next bit onto SDA. It will hold this value on SDA until the master again pulls the clock low.

3.4. Byte Transfer

Every byte transferred must be eight bits in length. Each byte must be followed by an acknowledgment bit. The most significant bit (msb) is transmitted first and the least significant bit (lsb) is transmitted last.

3.5. Acknowledge
An acknowledgment bit (A) must be sent after each byte is received, as shown in Figures 2 and 3. The master generates the clock pulse on SCL for the acknowledge bit, while the data receiver generates the

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acknowledge bit on SDA. The transmitter must release SDA (high output) during the acknowledge clock pulse. When a slave does not acknowledge the slave address transmitted by the master, the data line is left high. The master should then generate a stop condition to terminate the transfer. When a slave acknowledges its address, but cannot receive any more data bytes, it does not generate an acknowledge on the following byte. The master then generates a stop condition. When a master is receiving data from a slave, it does not acknowledge the last byte that it wishes to receive. The slave then releases the data line, allowing the master to generate a stop condition.

3.6. Stop Condition

A low-to-high transition on SDA while SCL is high indicates a stop condition (P), as shown in Figure 3-3. The stop condition is always generated by the master.

4. Clock Generation
The wired-AND function of the SCL lines supports clock synchronization. The master normally pulls SCL low at the end of a high clock period. At the end of the low period, it releases SCL by setting its clock output to high. However, SCL will not go high until all devices have released the clock. The master waits until SCL actually goes high before it begins timing the high clock pulse. Thus, a slave may pull SCL low if it needs additional time before the next high clock pulse.

5. Arbitration
A master cannot attempt to transfer data unless the bus is idle, i.e. SDA and SCL are both high following a stop condition. However, it may be that two or more masters sense an idle bus and attempt to use the bus (drive SDA) at nearly the same time. An arbitration procedure ensures a valid transfer by one of the masters in this situation. The arbitration scheme used on the I2C Bus grants the bus to the first master that generates a low (0) on SDA while the other master generates a high (1). If during a high clock pulse a master that outputs a high on SDA detects that SDA is low, then it knows that another master must be transmitting. The master generating the high loses arbitration and releases SDA (sets its data output high). The losing master may continue to generate clock pulses until the end of the byte in which it loses arbitration. The winning master continues with its data transfer. Arbitration can continue through many bits. If the masters are transmitting to different slaves, then arbitration will terminate with the first difference in address bits. If the masters are transmitting to the same slave, then arbitration will continue into the data. Because the winning master's data is transmitted properly, no data is lost. The losing master must recognize that it has lost arbitration and attempt its transfer later, if appropriate. A tricky situation occurs when a master loses arbitration during the address byte. It is possible that the winning master is trying to address the losing master as a slave. Therefore, the losing master must immediately switch to slave receiver mode. This implies that a master must collect the address byte being transmitted over the I2C Bus and, if it loses arbitration during the address byte, check the address to see if it matches its own address.

6. Addresses
Device addresses are seven bits long are unique for every device. The seven-bit device address and the R / W bit together form an eight-bit address byte. Certain addresses are reserved. For example, the start byte (00000001B) is a reserved address byte so that no slave device will respond to the start byte as an address.

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7. Interface for the 486 Target System and CEL I2C Bus
As shown in Figure 5, an I2C Bus interface requires four signals: SCL, SDA, VDD (+5V), and GND (ground). Four port pins are needed. Two pins are used to directly sense the actual value on SCL and SDA. The other two pins are used as the locally generated clock and data signals and are input to 7407 TTL open-collector non-inverting drivers. These two signals are referred to as USERCL (to drive SCL) and USERDA (to drive DA). The parallel port on the 80486 target system is used to input SCL and SDA and to drive USERCL and USERDA. Signal assignments are shown in Table 1 and illustrated in Figure 5. Note that the SLCT and PE parallel port signals may also be used to read the DIP switch. Verify that the proper connections are made on the breadboard in a drawer. Refer to the breadboard in a drawer schematic for details. Table 1. I2C Signal Assignments for Target Parallel Port

I C Signal
SCL SDA USERSCL USERSDA

Printer Pin
SELECT (SLCT) PAPER OUT (PE) AUTOFDXT* STROBE*

Pin Number
13 12 14 1 SCL

Port Location
Status (379H) D4 Status (379H) D5 Control (37AH) D1 Control (37AH) D0

SDA GND VDD

Parallel Port SCL SLCT SDA PE USERCL AUTOFDXT* USERDA STROBE* 07

Note: Bus must have exactly one pull-up resistor Rp for each of SCL and SDA signals.

07 Figure 5. I2C Bus interface.

A target systems breadboard in a drawer can be plugged into any of the three I2C Busses that are prewired in the EE 4536 section of the Computer Engineering Laboratory. Each pre-wired bus contains eight jacks allowing the connection of up to seven I2C devices plus one pull-up device that provides pull-up resistors from SCL and SDA to VDD. Additional pull-ups for SCL and SDA should not be included on project boards attached to the pre-wired bus. By disconnecting the pull-up device on one bus, two pre-wired busses can be connected with a jumper cable to form a larger bus that can accommodate up to 13 devices.

8. Timing for Low-Speed Mode

Figure 6 and Table 2 provide timing constraints for the low speed mode.

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Sr

SDA

tBUF

tR

tF

tHD;STA

SCL

tHD;STA

tLOW

tHIGH

tSU;DAT tHD;DAT

tSU;STO tSU;STA

Figure 6. Timing for low-speed mode. Table 2. I2C Low-Speed Mode Timing Parameter Values
Symbol
TBUF tHD;STA tHD;STA TLOW THIGH tSU;STA tHD;DAT tSU;DAT TR TF tSU;STO

Parameter
Time the bus must be idle before a new transmission can start. Hold time start condition. After this period the first clock pulse is generated. Hold time (repeated start condition only). Low period of clock. High period of clock. Setup time for start condition (repeated start condition only). Hold time for data. Setup time for data. Rise time for both SDA and SCL lines. Fall time for both SDA and SCL lines. Setup time for stop condition.

Limits MIN
105 365 210 105 365 105 0 250 1 300 105 155 155 415 155

Unit
s s s s s s s ns s ns s

MAX

9. Clock Skew
Clock skew is defined to be the uncontrolled and random deviation from the nominal timing of the leading edge of a given clock signal at a given clock input.1 Clock skew results from physical factors such as

S. H. Unger and C.-J. Ten, Optimal Clocking Schemes for High Speed Digital Systems, Proc. Intl. Conf. on Computer Design, 1983, pp. 366-369.

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variations in capacitances, differences in wire lengths, and other effects. While good design practices can minimize clock skew, it cannot be eliminated. Systems must be designed to tolerate some maximum clock skew S. Since a specified clock edge can be as much as S time units early at one point in a circuit and as much as S time units behind at another point, the maximum deviation between the receipt of the same clock edge at two different points in a circuit is 2S. Figure 6 shows an example of how clock skew can cause incorrect operation of an I2C Bus. The clock signal, SCL, is pulled low by the transmitting node tHD;DAT time units before SDA is pulled low (as shown in the light line) to end the transmission of a logic 1 data bit. However, if clock skew S is such that SCL is received (as shown by the heavy line) after SDA goes low, then the receiver may incorrectly interpret the signaling as a stop condition. This clearly leads to incorrect operation! A solution is for the bus master to account for the clock skew in controlling the clock signal, SCL. If SCL is pulled low 2S + tHD;DAT time units before SDA is pulled low, then all nodes will receive the high-to-low transition on SCL at least tHD;DAT time units before the high-to-low transition of SDA, even if SCL and SDA are skewed such that SCL is S time units late and SDA is S time units early, and correct operation is ensured. Similar considerations can be made for other setup and hold timings. For the purposes of the project, a clock skew value of S 2 s should be adequate. Note that if particularly long wires are used for SCL and SDA, or if the length of the SCL and SDA signal paths differ significantly, designs may need to tolerate a higher value of S. tHD;DAT SDA

SCL 2S Figure 6. Example of incorrect behavior resulting from clock skew.

10. References
Philips Components, Inter-Integrated (I2C) Circuit Bus, 80C51 and Derivative Microcontrollers (Book IC20), Section 2, 1991. Philips Semiconductors, I2C Peripherals for Microcontrollers, 1992. S. D. Quarles, How to Implement I2C Serial Communication Using Intel MCS-51 Microcontrollers, Application Note AP-475, April 1993 (Intel, Embedded Microcontrollers, pp. 2.147-2.173, 1994).

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