1

FPGA/CPLD Based Designing

Vinay Sharma
vinay@ni2designs.com
ni logic Pvt. Ltd., Pune
2
Agenda
World of Electronics
Introduction to Programmable Logic
CPLD
Working principle, Architecture, I/O Block, Macrocell, programming, features, examples.
FPGA
Working principle, Architecture, I/O Block, CLB, embedded memory, clock management,
DSP capability, programming, features, examples.
Comparison of CPLD / FPGA Architecture.
VHDL and its examples
PLD Design flow
Timing Aspects & analysis of PLDs
Latest trends in PLD Market
Design Consideration for PLDs
Advantages of PLDs
Prototyping Solutions
Conclusion
Q & A
3
World of Electronics
Master
Microprocessor/Microcontroller
Communication Interface
Serial, parallel, high speed, USB, irDA, PCI
Digital Logic
FPGAs/CPLDs
Memory
SRAM, FLASH, DRAM
Analog Circuitry
Sensors, Buffers,
amplifiers, ADC, DAC
Power Electronics
SCRs, optical isolators,
relays, IGBT
Displays
LCDs,LEDs
An Electronic System
4
World of Integrated Circuits
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLD
FPGA PAL PLA CPLD
Controllers
5
Programmable Logic
Since the invent of PLD from 1980s with few gate count, they have grown into
million gates, so as there usage in different applications.
Advantages like programmability and reconfiguration of PLDs has given ideas and
shape to many applications.
Todays PLDs like FPGAs can compete with ASICs in terms of performance and
gate counts.
From the time their use has increased in all sectors, like defense, consumer, multi
media, communications, DSP, etc.
6
What is Available?
CPLD (Complex Programmable Logic Device)
consists of multiple PLA blocks that are
interconnected to realize larger digital systems.
FPGA (Field Programmable Gate Array) has
narrower logic choices and more memory
elements. LUT (Lookup Table) may replace actual
logic gates.
7
CPLD Working Principle (SOP)
A B C
C B A C B A f + =
1
C B A B A f + =
2
AND plane
Programmable AND array followed by fixed fan-in OR gates
Programmable switch or fuse
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What is an CPLD ?
Integration of several PLD blocks with a programmable interconnect on
a single chip
PLD
Block
PLD
Block
PLD
Block
PLD
Block
Interconnection Matrix
Interconnection Matrix
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PLD
Block
PLD
Block
PLD
Block
PLD
Block
I
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Interconnection Matrix
Interconnection Matrix

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FPGA - Working Principle (LUT)
Look-up table with N-inputs can be used to implement any combinatorial function of
N inputs
LUT is programmed with the truth-table
A B C D Z
0 0 0 0
0
0 0 0 1
1
0 0 1 0
1
0 0 1 1
1
0 1 0 0
0
0 1 0 1
1
0 1 1 0
1
0 1 1 1
1
1 0 0 0
0
1 0 0 1
1
1 0 1 0
1
1 0 1 1
1
1 1 0 0
0
1 1 0 1
0
1 1 1 0
0
LUT
LUT
A
B
C
D
Z
Truth-table
A
B
C
D
Z
Gate implementation
LUT implementation
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What is an FPGA ?
FPGA building blocks:
Programmable logic blocks
Implement combinatorial and
sequential logic
Programmable interconnect
Wires to connect inputs and
outputs to logic blocks
Programmable I/O blocks
Special logic blocks at the
periphery of device for
external connections
I
/
O
I/O
Logic block Interconnection switches
I/O
I
/
O
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CPLD
Architecture and Examples
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CPLD Working Principle(SOP)
A B C
C B A C B A f + =
1
C B A B A f + =
2
AND plane
Programmable AND array followed by fixed fan-in OR gates
Programmable switch or fuse
13
CPLD Structure
Integration of several PLD blocks with a programmable interconnect on
a single chip
PLD
Block
PLD
Block
PLD
Block
PLD
Block
Interconnection Matrix
Interconnection Matrix
I
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PLD
Block
PLD
Block
PLD
Block
PLD
Block
I
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B
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Interconnection Matrix
Interconnection Matrix

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CPLD Example- Xilinx XC 9500
JTAG
controller
In system Programming Controller
JTAG
port
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Architecture Description
Each XC9500 device is a subsystem consisting of multiple
Function Blocks (FBs)
Provides programmable logic capability with 36 inputs and 18 outputs.
I/O Blocks(IOBs)
The IOBs provide buffering for device inputs and outputs.
FastConnect switch matrix.
Connects all FB outputs and inputs signals to the FB inputs.
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Function Block
Global
Set/Reset
Global
Clocks
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PLD - Macrocell
A B C
Flip-flop
Select
Enable
D Q
Clock
AND plane
MUX
1
f
18
Set control
Programmable
inversion or XOR
product term
Up to 5 product terms
Global clock or product-term
clock
Reset control
OE control
Macrocell
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I/O Block
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I/O Block
Interfaces between internal Logic and I/O Pins.
IOB consists of an
Input Buffer
Compatible with standard 5V volt CMOS, 5VTTL and 3.3 V signal
levels.
Output Driver
Capable of supplying 24 mA output drive.
Output enable selection multiplexer
Can be generated from, A product term signal, Any of the global OE
signals
User programmable ground control
To reduce system noise generated from large number of
simultaneous switching outputs.
21
CPLD Example - Altera MAX7000
EPM7000 Series Device Macrocell
22
Technology Used
CPLDs are non-volatile devices, I.e retain the program after Power-off.
The EPROM, EEPROM, FastFlash are the non-volatile type of memory.
The FastFlash technology is used because of its advantage over the EEPROM.
High Performance Logic Device.
High Memory cell density
Electrical erasable
High reliability and endurance
Fast device programming times
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Xilinx CPLD Product Portfolio
1.8V core
1.5V - 3.3V I/O
SSTL, HSTL, LVCMOS,
LVTTL
Lower power
DataGATE
Clocking features
Clock Divide
CoolCLOCK
DualEDGE
2.5V core
1.8V - 3.3V I/O
LVCMOS, LVTTL
I/O Banking
3.3V core
2.7V - 5V I/O
LVCMOS, LVTTL
Low power
Fast Zero Power
3.3V core
2.5V - 5.0V I/O
LVCMOS, LVTTL
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Altera CPLD Products
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FPGA
Architecture and Examples
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B
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R
A
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s
B
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R
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M
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Configurable
Logic
Blocks
I/O
Blocks
Block
RAMs
What is an FPGA?
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FPGA Block Diagram
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Other FPGA Building Blocks
Clock distribution
Embedded memory blocks
Special purpose blocks:
DSP blocks:
Hardware multipliers, adders and registers
Embedded microprocessors/microcontrollers
High-speed serial transceivers
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FPGA Basic Logic Element
LUT to implement combinatorial logic
Register for sequential circuits
Additional logic (not shown):
Carry logic for arithmetic functions
Expansion logic for functions requiring more than 4 inputs
LUT
LUT
Out
Select
D Q
A
B
C
D
Clock
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FPGA - Working Principle (LUT)
Look-up table with N-inputs can be used to implement any combinatorial function of
N inputs
LUT is programmed with the truth-table
A B C D Z
0 0 0 0
0
0 0 0 1
1
0 0 1 0
1
0 0 1 1
1
0 1 0 0
0
0 1 0 1
1
0 1 1 0
1
0 1 1 1
1
1 0 0 0
0
1 0 0 1
1
1 0 1 0
1
1 0 1 1
1
1 1 0 0
0
1 1 0 1
0
1 1 1 0
0
LUT
LUT
A
B
C
D
Z
Truth-table
A
B
C
D
Z
Gate implementation
LUT implementation
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LUT Implementation
Example: 3-input LUT
Based on multiplexers (pass
transistors)
LUT entries stored in configuration
memory cells
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
X1
X2
X3
F
Configuration memory
cells
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CLB Contains Four LUTs (Slices)
Each CLB is connected to one switch matrix
Providing access to general routing resources
CIN
Switch
Matrix
TBUF
TBUF
COUT COUT
Slice S0
X0Y0
Slice S1
X0Y1
Fast Connects
Slice S2
X1Y0
Slice S3
X1Y1
CIN
SHIFT
High level of logic integration
Wide-input functions
16:1 multiplexer in 1 CLB or
any function
32:1 multiplixer in 2 CLBs
Fast arithmetic functions
2 look-ahead carry chains per
CLB column
Addressable shift registers in LUT
16-b shift register in 1 LUT
128-b shift register in 1 CLB
(dedicated shift chain)
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Block RAM
Spartan-III
True Dual-Port
Block RAM
P
o
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t

A
P
o
r
t


B
Block RAM
Most efficient memory implementation
Dedicated blocks of memory
Ideal for most memory requirements
4 to 104 memory blocks
18 kbits = 18,432 bits per block
Use multiple blocks for larger
memories
Builds both single and true dual-port
RAMs
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Digital Clock Manager (DCM)
Up to 12 DCMs per device
Located on top and bottom edges of the die
Driven by clock input pads
DCMs provide:
Delay-Locked Loop
Digital Frequency Synthesizer
Digital Phase Shifter
Digital Spread Spectrum
Multiple outputs of each DCM can drive onto global clock buffers
All DCM outputs can drive general routing
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Xilinx - 18 x 18 Embedded Multiplier
Embedded 18-bit x 18-bit multiplier
2s complement signed operation
Multipliers are organized in columns
18 x 18 signed multiplier
Fully combinatorial
Optional registers with CE & RST (pipeline)
Independent from adjacent block RAM
18 x 18
Multiplier
Output
(36 bits)
Data_A
(18 bits)
Data_B
(18 bits)
4x4 signed ~255 MHz
8x8 signed ~210 MHz
12x12 signed ~170 MHz
18x18 signed ~140 MHz
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Altera: Embedded DSP Blocks
Two DSP Block columns per device
Number varies by height of column
Can implement:
Eight 9x9 multipliers
Four 18x18 multipliers
One 36x36 multiplier
Contains adder/subtractor/accumulator
Registered inputs can become shift register
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Altera: Embedded DSP Block
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Input/Output Blocks (IOBs)
IOB provides interface between the package pins and CLBs
Each IOB can work as uni- or bi-directional I/O
Outputs can be forced into High Impedance
Inputs and outputs can be registered
Advised for high-performance I/O
Inputs can be delayed
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Basic I/O Block Structure
D
EC
Q
SR
D
EC
Q
SR
D
EC
Q
SR
Three-State
Control
Output Path
Input Path
Three-State
Output
Clock
Set/Reset
Direct Input
Registered
Input
FF Enable
FF Enable
FF Enable
What more?
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Spartan-3 I/O Pin
Storage Element Functions
Double-Data-Rate
Transmission
Slew Rate Control and
Drive Strength
Pull-Up and Pull-Down
Resistors
Digitally Controlled
Impedance (DCI)
Keeper Circuit
ESD Protection
SelectIO Signal Standards
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Spartan-3 I/O Pin
Output Path
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Spartan-3 I/O Pin
Input Path
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Programmable Interconnect
Interconnect hierarchy
Fast local interconnect
Horizontal and vertical lines of various lengths
L
E
L
E
L
E
L
E
L
E
L
E
L
E
L
E
L
E
L
E
L
E
L
E
Switch
Matrix
Switch
Matrix
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Switch Matrix Operation
6 pass transistors per switch matrix
interconnect point
Pass transistors act as
programmable switches
Pass transistor gates are driven by
configuration memory cells
After Programming
Before Programming
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Configuration Storage Elements
Static Random Access Memory (SRAM)
each switch is a pass transistor controlled by the state of an SRAM bit
FPGA needs to be configured at power-on
Flash Erasable Programmable ROM (Flash)
each switch is a floating-gate transistor that can be turned off by injecting
charge onto its gate. FPGA itself holds the program
reprogrammable, even in-circuit
Fusible Links (Antifuse)
Forms a forms a low resistance path when electrically programmed
one-time programmable in special programming machine
radiation tolerant
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FPGA Programming/Configuration
Configuration is process of loading design and device specific bit-stream into one
or more FPGAs.
Volatile nature of FPGA makes the configuration considerations important because
the configuration is required on each power-on.
FPGAs can be programmed from PC via programming cable or the programming
file(BIT file) can be stored in a PROM.
Take care of other system modules during FPGA configuration.
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FPGA Programming/Configuration
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Major FPGA Vendors
SRAM-based FPGAs
Xilinx, Inc.
Altera Corp.
Atmel
Lattice Semiconductor
Flash & antifuse FPGAs
Actel Corp.
Quick Logic Corp.
Share over 80% of the market
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FPGA Vendors & Device Families
Xilinx
Virtex-II/Virtex-4: Feature-packed
high-performance SRAM-based
FPGA
Spartan 3: low-cost feature reduced
version
CoolRunner: CPLDs
Altera
Stratix/Stratix-II
High-performance SRAM-based
FPGAs
Cyclone/Cyclone-II
Low-cost feature reduced
version for cost-critical
applications
MAX3000/7000 CPLDs
MAX-II: Flash-based CPLDs
Actel
Anti-fuse based FPGAs
Radiation tolerant
Flash-based FPGAs
Lattice
Flash-based FPGAs
CPLDs (EEPROM)
QuickLogic
ViaLink-based FPGAs
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Xilinx FPGA Families
Old families
XC3000, XC4000, XC5200
Old 0.5m, 0.35m and 0.25m
technology. Not recommended for
modern designs.
High-performance families
Virtex (0.22m)
Virtex-E, Virtex-EM (0.18m)
Virtex-II, Virtex-II PRO (0.13m)
Virtex-4 (0.09m)
Low Cost Family
Spartan/XL derived from XC4000
Spartan-II derived from Virtex
Spartan-IIE derived from Virtex-E
Spartan-3 derived from Virtex-II
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Altera FPGA Families
Old Families
FLEX 10K, FLEX 6000, FLEX
8000
High-performance Families
Mercury
Stratix, Stratix GX, Stratix II
APEX 20K , APEX II
Excalibur
Low Cost Family
Cyclone, Cyclone II
52
Comparison of CPLD / FPGA Architecture
53
CPLD Vs FPGA
Interconnect structure.
In-system performance.
Logic Utilization.
Applications.
54
Interconnect Structure
CPLD uses a Continuous interconnect structure :
Consists of metal lines of uniform length traverse the entire length and width of
the device.
Since the resistances and capacitances of all interconnect paths is fixed,
delays between any two logic cells can be predictable.
This minimizes the logic skew.
FPGA uses a segmented interconnect structure.
Consists of matrix of metal interconnects that run throughout the device.
Switch matrices or Antifuses join the ends of these segments allowing signals
to travel between logic cells.
Number of segments required to interconnect signals is neither constant nor
predictable, so delays are not fixed or specified until place and route is
completed.
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Logic Utilization
Logic cells in most FPGA architecture have fine granularity, therefore more logic
cells are required to implement a function in FPGA than in a CPLD.
Logic cells in FPGA can contain only small portion of a design, so a heavy burden
is placed on its segmented interconnect structure.
As design complexity increases, the probability of routing conflicts also increases
leading to lower FPGA device utilization.
Logic density in FPGA is less due to only 9 variables, where as CPLD has 36
variables available.
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Applications - FPGAs
FPGAs
Basically register intensive applications.
Data paths.
Hardware Emulation.
Image controller.
Battery powered applications.
Field-test equipments.
Gate-array prototyping.
57
Applications - CPLDs
CPLDs
Basically combinatorial functions.
Bus interfacings.
Comparators.
High-speed wide decoders.
Large fast state micro controllers.
High speed GLUE Logic.
System video controller.
PAL integration.
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VHDL and its examples.
59
VHDL Language
Hardware Description Language (HDL)
High-level language for to model, simulate, and synthesize digital circuits
and systems.
History
1980: US Department of Defense Very High Speed Integrated Circuit program
(VHSIC)
1987: Institute of Electrical and Electronics Engineers ratifies IEEE Standard
1076 (VHDL87)
1993: VHDL language was revised and updated
Verilog is the other major HDL
Syntax similar to C language
Many tools accept both Verilog and VHDL
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Terminology
Behavioral modeling
Describes the functionality of a component/system
For the purpose of simulation and synthesis
Structural modeling
A component is described by the interconnection of lower level
components/primitives
For the purpose of synthesis and simulation
Synthesis:
Translating the HDL code into a circuit, which is then optimized
Register Transfer Level (RTL):
Type of behavioral model used for instance for synthesis
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Digital Circuits and VHDL Primitives
Most digital systems can be described based on a few basic circuit elements:
Combinational Logic Gates:
NOT, OR, AND
Flip Flop
Latch
Tri-state Buffer
Each circuit primitive can be described in VHDL and used as the basis for
describing more complex circuits.
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Digital Circuit Primitives
Combinational Logic Gates: NOT, OR, AND
Flip Flop/Latch
Tri-state Buffer
Logic gates can be modeled using concurrent signal assignments:
Z <= not A;
Y <= A or B;
X <= C and D;
W <= E nor F;
U <= B nand D;
V <= C xor F;
It is possible to design circuits from logic gates in this way
X
C
D
AND
E
F
NOR
W
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4-to-1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
port (
a, b, c, d: in std_logic;
s: in std_logic_vector(1 downto 0);
y: out std_logic);
end entity mux;
architecture mux1 of mux is
begin
process (a, b, c, d, s)
begin
case s is
when "00 => y <= a;
when "01" => y <= b;
when "10" => y <= c;
when "11" => y <= d;
end case;
end process;
end architecture mux1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
port (
a, b, c, d: in std_logic;
s: in std_logic_vector(1 downto 0);
y: out std_logic);
end entity mux;
architecture mux1 of mux is
begin
process (a, b, c, d, s)
begin
case s is
when "00 => y <= a;
when "01" => y <= b;
when "10" => y <= c;
when "11" => y <= d;
end case;
end process;
end architecture mux1;
S(1) S(0)
d
c
b
a
y
External world interface
Internal logic design
Libraries
64
Sequential Logic: D-Flip Flop
architecture rtl of D_FF is
begin
process (Clock, Reset) is
begin
if Reset = 1 then
Q <= 0;
if rising_edge(Clock) then
Q <= D;
end if;
end process;
end architecture rtl;
architecture rtl of D_FF is
begin
process (Clock, Reset) is
begin
if Reset = 1 then
Q <= 0;
if rising_edge(Clock) then
Q <= D;
end if;
end process;
end architecture rtl;
Flip-flop
D Q
Clock
D Q
Reset
R
65
Binary Counter
This example is not explicit on
the primitives that are to be used
to construct the circuit.
The + operator is used to
indicate the increment operation.
entity counter is
generic (n : integer := 4);
port (
clk : in std_logic;
reset: in std_logic;
count: out std_logic_vector(n-1
downto 0)
);
end entity counter;
entity counter is
generic (n : integer := 4);
port (
clk : in std_logic;
reset: in std_logic;
count: out std_logic_vector(n-1
downto 0)
);
end entity counter;
use ieee.numeric_std.all;
architecture binary of counter is
Signal cnt : std_logic_vector(n-1 downto 0);
begin
process (clk, reset)
begin
if reset = '1' then -- async
reset
cnt <= (others => '0');
elsif rising_edge(clk) then
cnt <= cnt + 1;
end if;
end process;
Count <= cnt;
end architecture binary;
use ieee.numeric_std.all;
architecture binary of counter is
Signal cnt : std_logic_vector(n-1 downto 0);
begin
process (clk, reset)
begin
if reset = '1' then -- async
reset
cnt <= (others => '0');
elsif rising_edge(clk) then
cnt <= cnt + 1;
end if;
end process;
Count <= cnt;
end architecture binary;
66
State Machine
If a trigger signal is received, will stretch it to 2 cycles and wait for accept signal
entity trigger is
port (
clk, reset: in
std_logic;
trigger, accept : in
std_logic;
active: out
std_logic);
end entity trigger;
architecture rtl of trigger is
type state_type is (s0, s1, s2);
signal cur_state,
next_state: state_type;
begin
registers: process (clk, reset)
begin
if (reset='1') then
cur_state <= s0;
elsif rising_edge(clk) then
cur_state <= next_state;
end if;
end process;
entity trigger is
port (
clk, reset: in
std_logic;
trigger, accept : in
std_logic;
active: out
std_logic);
end entity trigger;
architecture rtl of trigger is
type state_type is (s0, s1, s2);
signal cur_state,
next_state: state_type;
begin
registers: process (clk, reset)
begin
if (reset='1') then
cur_state <= s0;
elsif rising_edge(clk) then
cur_state <= next_state;
end if;
end process;
reset
State
Transition
Logic
State
Transition
Logic
Output
Logic
Output
Logic
R
clk
curr_state
trigger accept
67
State Machine (cont.)
process (cur_state, trigger,
accept) is
begin
case cur_state is
when s0 =>
active <= '0';
if (trigger = '1') then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
active <= '1';
next_state <= s2;
when s2 =>
active <= '1';
if (accept = '1') then
next_state <= s0;
else
next_state <= s2;
end if;
end case;
end process;
process (cur_state, trigger,
accept) is
begin
case cur_state is
when s0 =>
active <= '0';
if (trigger = '1') then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
active <= '1';
next_state <= s2;
when s2 =>
active <= '1';
if (accept = '1') then
next_state <= s0;
else
next_state <= s2;
end if;
end case;
end process;
State
Transition
Logic
State
Transition
Logic
Output
Logic
Output
Logic
R
clk
curr_state
S0 S1
S2
trigger
accept
68
PLD Design flow
69
FPGA Design Flow
Synthesis
Translate Design into Device Specific Primitives
Optimization to Meet Required Area & Performance
Constraints
Design Specification
Place & Route
Map Primitives to Specific Locations inside
Target Technology with Reference to Area &
Performance Constraints
Specify Routing Resources to Be Used
Design Entry/RTL Coding
Behavioral or Structural Description of Design
LE
MEM
I/O
RTL Simulation
Functional Simulation
Verify Logic Model & Data Flow
(No Timing Delays)
70
FPGA Design Flow
Timing Analysis
- Verify Performance Specifications Were Met
- Static Timing Analysis
Gate Level Simulation
- Timing Simulation
- Verify Design Will Work in Target Technology
Program & Test
- Program & Test Device on Board
t
clk
71
Specifications
Functional
Simulation
Logic Synthesis
Design Entry
Static Timing Analysis
System partitioning
and Floor-planning
Placement and Routing
Post-Layout
Simulation
Programming
Production
Pre-Layout
Simulation
Synth. Lib
Constraints
Timing Lib.
Design Flow
Static Timing Analysis
T
e
s
t

B
e
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h
Sch, VHDL, Verilog
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EDA Tools : Altera Quartus II
Fully integrated design tool
Multiple design entry methods
Text-based: VHDL, Verilog,
AHDL
Built-in schematics editor
Logic synthesis
Place & route
Simulation
Timing & power analysis
Create netlist for timing
simulation
Device programming
Xilinx ISE has similar kind of features
73
Timing Aspects & Analysis of PLDs
74
Timing Issues
Basic Questions
Does my design meet a given timing requirement, or
How fast I can run the design?
Are there any chances of failures?
We know about nominal delay simulation; why not use it..?
Requires too many patterns.
Increases exponentially with the number of design inputs.
Even worse if we consider sequences needed to initialize latches.
So what we do instead..??
Separate function from time,
Determine when transitions occur without worrying about how.
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Timing Issues
The basic idea of Static Timing Analysis is,
To find that the data is transferred through the system safely.
Instead of considering an infinitely long simulation sequence, fold all possible
transitions back into a single clock cycle.
If the design is working extremes, we can guarantee it always will.
Static part just means we arent doing simulation (dynamic).
A
B
C
D
Clock rate?
Data rate?
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FPGAs - Fmax
All in MHz
77
Synchronous or Asynchronous
Synchronous designs have a clock that determines when signals should be
sampled. The signals are either sampled at the rising edge or at the falling edge of
the clock.
Unit of Time is Fixed
Asynchronous designs do not operate with a clock. Relies on handshaking
between logic. Sensitive to glitches and ordering of signals.
Unit of Time is NOT Fixed
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Why Synchronous?
Signals are sampled at well- defined time intervals.
Interfacing two synchronous blocks is simple. Interfacing asynchronous blocks is
not simple.
Synthesis and other tools does not handle asynchronous logic very well.
FPGAs are NOT good for Asynchronous designs.
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What is the MAXIMUM frequency of operation for above system?
Maximum Frequency = 1/ (longest delay path I.e. Critical Path)
Timing Issues
Combinational
Logic
Circuit
n
m
K k
k-bit
Present State
Value
k-bit
Next State
Value
clk
DFF
D Q
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How To Improve Speed?
The register-to-register delay is usually the delay path that sets the maximum
clock rate.
From a design point of view,one can only affect the combinational logic between
the registers
Need to shorten the maximum combinational delay path
Setup/Hold time of registers are fixed
Can shorten the delay by placing a register in the combinational logic to break
longest delay path
This technique is called pipelining
Adds latency to the output (the number of clocks between an input value and
its corresponding output result)
81
Latest trends in PLD Market
82
Fight of Titans
83
State of the Art in FPGAs
90 nm process on 300 mm wafers
Lower cost per function (LUT + register)
Smaller and faster transistors: Higher speed
System speed up to 500 MHz
Mainly through smart interconnects, clock management, dedicated circuits,
flexible I/O.
Integrated transceivers running at 10 Gigabits/sec
More Logic and Better Features:
>100,000 LUTs & flip-flops
>200 embedded RAMs, and same number 18 x 18 multipliers
1156 pins (balls) with >800 GP I/O
50 I/O standards, incl. LVDS with internal termination
16 low-skew global clock lines
Multiple clock management circuits
On-chip microprocessor(s) and multi-Gbps transceivers
84
Latest Devices: Capacity & Features
Xilinx Virtex-4
90nm process
Up to 960 I/Os
>2,00,000 logic cells
Up to 552 18kb block RAMs (~10Mb
RAM)
192 DSP slices (18x18 multiplier-
accumulator)
20 digital clock managers (DCM)
24 high-speed serial transceivers
(622Mb/s to 11.1Gb/s)
Up to four PowerPC 405 cores
Altera Stratix-II
90nm process
Up to 1170 I/Os
1,79,000 logic elements
9.6Mb embedded RAM
96 DSP blocks: 380 18x18 multipliers
12 PLLs
Serial I/O up to 1Gb/s
No hard processor cores
85
Design Consideration for PLDs
86
Designing with FPGA
A complete flat land (logic elements,
memory, gates).
No predefined architecture or
controllers.
Generation of timings and timing
match.
Control of bus.
Handshaking of signals.
Protocol development.
Verification of logic.
User to describe complete logic with
HDLs.
Logic dependant on
..HDL..HDL..HDL
87
Designing with FPGA
FPGA
Memories
Microcontroller
Analog Circuits
Communication
Peripherals
Handshaking
Timing
Voltage Levels
Protocols, Speed
Bus Control, triggering
88
Advantages of PLDs
89
Why to go for PLDs ?
Flexibility.
In system programmability.
Less project development time.
Best prototyping solution.
Cost effective solutions.
Involves less risk.
Design security.
Consumes less board area.
Reconfigurable computing.
Best suits hardware verification for design.
90
Prototyping Solutions
91
Prototyping Solutions
A system model to test and develop the
product before its final implementation.
Prototyping is like headache to designers
Ease of prototyping is necessity
Flexibility is must
Individual eval boards or kits available
Need for universal platform integration
Modular approach
Up gradation and addition of modules at regular interval.
92
Prototyping Boards
Multi-vendor
device support for
Xilinx and Altera
PLDs.
All FPGA I/Os
accessible
through headers.
93
Prototyping Boards
A universal platform for various
technologies
An excellent prototyping and
system development platform
Modular approach
Modules can be integrated
according to needs
Flexible and easy up gradation
94
Prog. Port
FPGA
FPGA
Modules
Configuable I/Os
7 Seg Disp,
LCD interface
Box Osc.
One Platform
Keypad Interface
SRAM
89c51
PIC uC
ADC/DAC
..more
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Embedded System Development.
High-Resolution Image Processing.
High speed Digital Signal Processing.
NIOS-II/ Microblaze Soft Processor Development.
USB / LAN based application development.
Process Control, automation and Industrial Systems
Universal Prototyping Platform.
96
Conclusion
PLDs are
Cheaper
Faster
Bigger
More versatile
and easier to use
And obviously best choice for the system designer.
97
Thank You..!
ni logic Pvt. Ltd.,
Email: info@ni2designs.com
URL: www.ni2designs.com