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Chapter 6 : Design With CPLDS AND FPGAS Q. 1. What are Programmable Logic devices? Ans.

A programmable logic device is an IC that is user configurable and is capable of implementing logic functions. Memory cells control and define the function that the logic performs and how the various logic functions are interconnected. PLD is composed of two types of gate arrays, the AND array and the OR array. Q. 2. What are the advantages of ROM as a programmable logic device? Ans. The advantages of using ROM as a programmable logic device are: 1, Ease of design since no simplification or minimization of logic function is required. 2. Designs can be changed, modified rapidly. 3. ROM is faster than discrete SSP/MSI circuit. 4. Cost is reduced. Q. 3. What are the advantages of PLDs over fixed function ICs? Ans. Advantages of PLDs over fixed function iCs: 1. Reduction in board space requirements. 2. Reduction in power requirements. 3. Design security. 4. Compact circuitry 5. Higher switching speed. Q. 4. What are the steps in design process using PLDs? Ans. The design process using PLDs require the following steps: 1. Function specification 2. Generation of Booleart equations. 3. Minimizatjcn of Boolean equations. 4. Generation of fuse maps. 5. Logic simulation. 6. Programming the selected device. 7. Testing. Q. 5. What do you mean by ROM? Ans. Read only Memory (ROM): A Read only memory (ROM) is a ombinafionaI circuit with n-inputs and b-outputs he inputs are called address inputs and outputs are called data outputs. Some of the Features of ROM are as follows: 1. Densest memory. 2. ROM is programmed with transistors to supply the designed value. 3. Static memory. 4. ROM core is organised or NOR gates-pull-down transistors or NOR determine programming.

Q. 6. Draw the structure of ROM.

The ROM has n address lines and since there are 2n combinations of n-binary digits the device contains 2n registers, each addressed by one of the 2n output lines of the address decoder. Q. 7. What are different types of ROMs? Ans. Types of RUMs: 1. Mask Programmed : Their contents are programmed according to the desired specification and no change is permitted by the user. Mask Programmability may be achieved using: contact programming. Presence or absence of a transistor. Implant to turn transistors permanently OFF or ON. 2. PROMs (Programmable ROMs) : A programmable read only memory (PROM) is similar to a mask ROM except that the customer may store data values. It is user programmable with the aid of a device known as PROM programmer. The PROM programmer can be used to set desired bits to the opposite value. 3. EPROMs (Erasable PROMs) : User programmable like PROM but can also be erased to all-is state by exposing it to ultraviolet light. 4. EAROMs (Electrically alterable ROMs) : They are erased electrically and also employ MOS floating gate technology such ROMs have quite small packing densities. 5. Flash Memory : Flash memories are often packaged into a single credit-card- size module for applications these offer fast read access and rapid contents erasure. Their packing densities are similar to EPROMs.

Q. 8. Explain ROM implementation using bipolar technologies. Ans. Circuit details of a bipolar 4 x 4-bit ROM.

In bipolar ROM, bipolar junction transistors are considered to be data-storing elements. In the figure, BL is the bit line and WL is the word line. No physical contact is there between WL and BL line. When BL line is grounded irrespective of the value on WL line 0 is stored. When a high voltage is applied on WL line the BIT is forward biased and I is considered to be stored and if there is no BJT 0 is stored.

Q. 9. Implement a 2-bit adder using ROM.

We see that there are five input variables and a three output variables. So a 5 to 32 line decoder is to be used and the ROM matrix used is of 32 locations each storing three bits of output. The partial ROM program table is given by

How would you construct it? Ans. ROM : A read only memory (ROM) is a semiconductor memory device used to store information which is permanent in nature, and has become an important part of many digital systems because of its low cost, high speed, system design flexibility and data non-volatility. The read-only memory has a variety of applications in digital systems, such as implementation of combinational logic and sequential logic, character generation, look-up table microprocessor programme storage etc. RAM: Many digital systems require memories in which it should be possible to write into or read from any memory location with the same speed. In such memories, the data stored at any location can be changed during the operation of the system. This types of memory is known as read/write memory and is usually referred to as RAM :random access memory).

Q. 11. What are the advantages and disadvantages of ROM? Ans. Advantages of ROM: 1. Ease and high speed of design. 2. Faster than circuit using SSI/ MSJ devies. 3. Design can be easily changed and modified 4. Reduced cost. Disadvantages of ROM: 1. More power consumption. 2. Increase in size with increase in number of input variables.

Q. 12. Explain and draw the internal structure of PLA. Ans. PLA (Programmable Logic Array) : PLA basically consists of AND matrix and OR matrix depending on the users requirement; connections in the matrix are fused. In this, both AND or gate arrays are programmable.

PLA uses two levels of logic, one implementing ANDs (product terms) and another OR terms. AND gate provide the product terms and OR array gate logically sum the product terms and thus generat the SOP expression. Input supplies both true and complement form of the variable by using pair of inverters on the true form as buffers. Input to AND plane flows vertically while outputs of AND flow horizontally and emerges at right side. OR plane is simply 90 rotation of AND plane.

Q. 13. List few of the commercially available PLA ICs. Ans. 825200 and 825201 are the commercial PLA ICs which are pin-for-pin mask programmable replacements for the 825100 and 825101. The DM 7575 PLA has taken pole output, whereas DM7576 and 1M5200 have passive pull up. The devices with passive pull up are useful for expanding functions by wire-ANDING the outputs of similar other devices.

Q. 15. Enumerate advantages and disadvantages of PL4 Ans. Advantages of PLAs: PLA like ROMs have many advantages over random logic gate networks. Some of the advantages of PLAs are described as below 1. Logic designing is less time consuming. 2. Design checking is easy and can also be changed or modified easily. 3. Layout is very simple. 4. With the advancement of new IC technology the previous design information can be used but without changes, making adoption of the new technology quick and easy. Disadvantages of PLAs: 1. PLAs have lesser speed than random logic gate network. 2. PLAs occupy larger chip-area as that of random logic gate networks. 3. With large production volumes, PLAs became costlier as compared to random - logic gate networks. 4. PLAs cannot store complex functions i.e. functions whose disjunctive forms consists of many product terms.

Q. 16. What are the applicaticms of PLAs? Ans. Applications of PLAs: 1. PLAs can be used to implement combinational and sequential logic circuits. 2. PLAs are used in many microprocessor chips because of ease of design change and check.

3. PLAs are particularly suited for implementation of ASICs. 4. PLAs are used in control logic, thereby repairing full custom design approach because it is very time consuming. A number of different custom-design chips with high performance can be made quickly by changing only one connection mark for PLAs.

Q. 17. How does a PLA differ from a ROM? Ans. Difference between PLA and ROM: 1. For storing the same functions or tasks, PLAs can be smaller than ROMs generally, the size difference sharply increases asthe number of input variables increases. 2. The small size advantages of PLAs diminishes as the number of terms in disjunction increases. PLAs can not store complex functions. 3. In ROM, only OR plane lines are programmable whereas in case of PLAs both AND and OR plane lines are programmable.

Q. 18. What is a PAL (Programmable Array Logic)? Ans. PAL is a programmable logic device that consists of a programmable and matrix whose outputs drive fixed or gates. PALs can typically implement small functions easily and run very fast, but they are inefficient for large functions. The input and gate connections are programmable in PAL and the gate count in PAL as compared to PROM is very much reduced. Since, only the AND array is programmable the PAL is less expensive than general PLA. Typical combinational PALs have from 10 to 20 inputs and from 2 to 20 outputs with 2 to 8 AND gates divising each or gate. Computer aided design programs for PALs are widely available such programs accept logic equations, truth tables, state graphs or state tablesas inputs and automatically, generate the required fuse patterns.

These patterns can then be downloaded into a PLD programmer, which will blow tht required fuses and verify the operation of the PAL. Q. 19. What are the advantages of PALs as compared to PI.As? Ans. Advantages of PALs over PLAs: 1. PALs are less expensive than general PLAs since in this only AND array is programme.

2. Since, PALS eliminates fuses in OR array. This results in reducing very larg area which otherwise requires large area. 3. PAL is an alternative to PROMs. 4. PAL is easier to program and used to replace individual gates when severa logic-function must be realized. 5. PALS containing D flip-flops with inputs driven from the programmable arraj logic provide a convenient way of realizing sequential networks.

Q. 20. Draw the block diagram of Programmable Gate Array.

The arrays if XOR and AND gates are programmable.

Q. 21. Implement 4-input 4-output PGA. Ans. A 4-input 4-output PGA is shown in fig. It is capable of generating the AND NAND, OR and NOR functions. Since, a PGA only provides a single level of logic, it have very limited applications.

Q. 22. Write short note on GAL. Ans. Generic Array Logic (GAL): 1. Generic array logic family consists of electrically erasable programmable devices designed by lattice semiconductor.

2. The GAL is very useful in phototyping stage of a design. When any bugs in the logic can be corrected by reprogramming. 3. GAL devices are intended as pin-for-pin replacements for a wide variety of PAL devices. It is designed to be compatible, all the way to the fuse level, for any simpler PAL which can be implemented in the GAL device. 4. It has a fixed OR array and a programmable And array the reprogrammable array is essentially a grid of conductors forming rows and columns with an electrically erasable CMOS (E2CMOS) cell at each cross point. 5. The GAL has the programmable logic and the OLMC (Output Logic Macro cell) Logic that excludes OR gates and flip-flops.

Q. 23. Draw the functional block diagram of GAL 16V8 and enlist important features of GAL 16V8. Ans. Functional block diagram of GAL 16V8: The GAL 16V8 is the fastest available combinational PLJ at 3.5ns maximum propagation delay the generic architecture provides maximum design flexibility by allowing the output logic macro cell to be configured by the user.

Features of GAL 16V8: 1. Maximum operating frequency is 250MHz. 2. Reconfigurable logic and reprogrammable cells. 3. High speed Electrical Erasure. 4. Maximum flexibility for logic designs. 5. Programmable output Polarity. 6. High performance E CMOS Technology.

Q. 24. Draw the structure of Output Logic Macro Cell (OLMC) different operating modes.and explain its?

Each OLMC has four cells SYN, ACo, AC1(n) and EX-OR(n) which can be programmed to select one of the five operating modes of OLMC. 1. SYN bit: It determines whether the output of the OLMC will be registered or purely combinational. It replaces the ACO bit in .OLMC (2) and OLMC (19) of GAL structure. 2. ACO bit: It along with 8ACI (n) selects any one of the following output enable configuration. I/O pin in an OLMC is a dedicated output. I/O pin in an OLMC is a dedicated input The tristate inverters at the outputs of all OLMCs are enabled by the common output enable OE. The tristate inverters can be individually enable by a product term. 3. ACI (n) bit: It determines the source of feedback term. This term is feedback to the AND array via the multiplexer MUX.

Q. 25. Enlist important applications of GAL. Ans. Applications of GAL: 1. DMA control 2. State Machine control 3. High Speed Graphics processing. 4. Standard Logic speed Upgrade. Q. 26. Explain complex PLDs (CPLDs) in short.

Ans. Complex PLDs : Complex Programmable logic device (CPLD) is an programmable logic device that can be programmed by integrating numerous SPLDs on a single chip and a ding programmable interconnect between them results in a complex PDL or CPLD. The architecture of CPLD offers high speed, predictable timing and simple software.

The basic CPLD cell is called a macro cell, which is the CPLD implementation of. a CLB. It comprises of AND gate arrays and is surrounded by the interconnect area. The logic blocks have programmable AND, fixed or with fewer product terms as that of PAL devices. Some CPLDs are programmed using a PAL programmer, but this method become inconvenient for the devices with hundreds of pins. The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform to specified logic function.

Q. 27. List out various important features of XC9500 CPLD family. Ans. Features of .XC950 () CPLD: 1. High performance device. 2. Capacity to base 10,000 program/erase cycles. 3. Large density range having 35 to 280 macro cells with about 800-6,200 usable gates.

4. Slow rate control on industrial outputs. 5. User programmable ground pin capability. 6. Advanced CMOS 5V Fast Flash technology. 7. Flexible 36V18 Functional Block. 8. Programmable power reduction mode in each macro cell. 9. Enhanced pin-locking architecture. 10. Extended pattern security features for design protection.

Q. 28. Explain with block schematic, the architecture of Xilinx 9500 CPLD. Ans. XILINX 9500 CPLD Architecture: i/O Blocks : It comprises of input, buffer, output buffer and multiplexer for the output control and grounding control Multiplexer for the output control any delay. Function block (FB) : It is composed .of programmable AND array, product term allocator (PTA) and Macro cell. The function block also receives global clock, output enable and their corresponding output enable signals also drive tjie lOB. There are 18 independent macro cells in one FB. There are 18 pieces of output in the FB and they are connected with fast connect switch matrix and I/O Blocks (OEMUX) controls an output enable or stop. It is controlled by the macro cell or the signal of GTS (global three state control) pin. It can always make output 0 or 1. A slow rate control is to make the rising and the falling of the output pulse smooth. It is used to suppress the occurrence of noise.

A ground control is used when making input/output pin and, earth terminal. Fast CONNECT Switch Matrix: It controls the input signals to the function block. The output signals from the functional block are applied through the wired and buffer. This provides additional logic capability and increases the effective logic fan in of the destination FB without any delay.

Q. 29. What is the function of fast .connection matrix? Ans. Function of fast CONNECT Matrix: It connects the input signals to the function block. The diagram of fast CONNECT switch matrix is shown in fig below:

All the signals from the i/O port and all FB outputs are connected with fast CONNECT switch matrix The output signals from the FB are applied through the wired and buffer This provides additional logic capability and increases the effective logic fanin of functional block without any dela9

Q. 30. What are the applications of ClDs? Ans. Applications of CPLDs: 1. Implementing random glue logic and prototyping small gate arrays. 2. Conversion of designs including converting multiple SPLDs into a smaller number of CPLDs. 3. Realization of complex designs such as graphics controller, LAN controllers, VARTs cache control and many others. 4. Simple design changes through reprogramming (all commercial CPLD products are reprogrammable). 5. Possibility to configure hardware (e.g. to change a protocol for a communication) without power-down. 6. Predictability of circuit implementation and speed performance is one of the strongest advantages of CPLD architectures. Q. 31. Write short notes on: 1. PEEL 2. FPGA.

Ans 1. PEEL (Programmable Electrically Erasable Logic) Device : PEEL devices are another family of devices that are intended as PAL replacements the PEEL is available in 20 pin different packages with speeds ranging from 5ns to 25ns. The PEEL architecture allows it to replace over 20 standard 20 pin PLDs (PAL, GAL, etc.) Features of PEEL: 1. Speed ranging from 5ns to 25ns 2. Low Power consumption. 3. CMOS Electrically Erasable Technology. 4. Reduces development Cost 5. Flexible architecture. 2. FPGA field Programmable Array: A field Programmable gate array usually refers to a VLSI module that can be programmed to implement large digital systems containing thousands of gates. FPGAs have different architecture (design) than CPLD but very much similar to CPLD in their applications. FPGA are field programmable devices having logic structures, which can configured by end user. The basic FPGA structure shown in fig. below is built from logic blocks and interconnections between logic blocks arid input and output blocks (lOBs).

FPGAs mainly comprises of three types of resources-logic blocks, Input and output blocks (JOBs) and Interconnections and Switches. Logic cells are arranged in 2-D array. Interconnection wires are organized as horizontal and vertical routing channels between rows and columns of blocks. Individual cells are connected by matrix of wires and programmable switches. FPGA contains many identical logic cells that can be viewed as standard component. Each logic cell can independently can take any of the limited responsibilities. The logic cells may be either sequential or combinational or both. The functionality of logic cells is set at programming time by fixing a number of control inputs.

Q. 32. Explain different FPGA programming types. Ans. There are three ways in which FPGAs can be programmed. 1. SRAM Programming (Volatile) The SRAM FPGAs consists of a large array of programmable logic cells known as configurable logic blocks (CLBs). In this, interconnected routes are set up by using transistors, transmission gates and multiplexers. It is volatile because if power supply is interrupted, the contents of FPGA chip will be lost, so the program must be loaded from the processor at the start up time.

To program the component at start up time, programming data is shifted serially into the part over a single line. In SRAM based approach, the internals of the chip are modified without changing the hardware. 2. EPROM-FPGA (Non-volatile) : EPROM-FPGAs consists of erasable/electrically erasable floating gate transistors. By electrically modifying the threshold voltage of the transistor it is possible to program a memory cell to store either 0 or 1. The EPROM-FPGAs do not require external memory to preserve cell- configuration. The drawback is that chip fabrication process is complex and integration density is low. 3. Fuse-based FPGAs: Antifuse programmed devices (antifuse represents an open circuit in the unprogrammed mode, can be turned into a short circuit during programming phase) are programmed electrically to provide