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A Compact Low-Power VLSI Transceiver for Wireless Communication

Sa H. Bang, Member, IEEE, Joongho Choi, Member, IEEE, Bing J. Sheu, Senior Member, IEEE, and Robert C. Chang, Student Member, LEEE

Abstract-A 3 V CMOS VLSI for dual-mode wireless com- important role in transmitting, receiving signals and correcting munication systems has been designed and fabricated using the data errors occurred during the transmission via multi-path MOSIS scaleable CMOS technology. By using mixed analog channels. and digital circuit design techniques, a single chip solution to A 3 V CMOS data transceiver chip for dual-mode wireless baseband processing of data and supervisory audio tone signals in the analog transmission mode is possible. Key analog circuits mobile communication systems is designed and fabricated include an anti-alias filter, two fifth-order low-pass filters, one using the mixed analog and digital CMOS design techniques. sixth-order band-pass filter, an interpolator for sampling rate It provides a single chip solution to the processing of transmit conversion, and two comparators. The digital modules perform and receive wideband data in both the analog mode and standdata transmission and reception, error coding and decoding, as well as tone detection and regeneration. When implemented in by operation of the digital transmission mode. As an integrated the 2 pm CMOS technology from the MOSLS Service for low-cost data transceiver chip, it is especially designed to consume low-power applications, the transceiver chip consumes less than minimum power while achieving high performance operation 6 mW at receive-only mode. It is also quite suitable for battery- at a 3 V supply voltage. To this end, circuit architectures and powered devices, such as portable terminals. Design technologies design are carefully optimized. Low-power consumption in can be applied to future high-speed Wireless transceiver design. The architecture and circuits described in this chip can be used the stand-by operation is an extremely important feature in i n aggressively scaled technologies even with the supply voltage personal communication systems [ 5 ] , [6] because the system reduced toward 1 V if the threshold voltage is proportionally must be ready to receive the incoming calls for a long period decreased. of time. On the other hand, the power consumption in the active operation is typically dominated by that of the RF power


OR ESTABLISHING high-capacity land mobile telephone and data transmission systems, economical and high-performance mobile radio units have been developed and 11. HARDWARE ARCHITECTURE used in many cities over the world. New digital technologies have been employed to accommodate higher capacity The block diagram of a data transceiver and its function by increasing the efficiency of frequency resources and the in wireless communications are shown in Figs. 1 and 2. rapid trends in integrated data communication networks for The modulation technique employed is a noncoherent binary computer and multimedia applications. In Europe, the pan- frequency-shift keying (BFSK) in which the frequency of European Groupe Special Mobile (GSM) [ 13 system has been modulated carrier switches between two frequencies. Binary established for voice and data communications. The dual- data is Manchester-encoded [2] for the purpose of embedding mode, time-division multiple access (TDMA) [2]-[4] scheme timing information into the data signal. The transceiver rehas been adopted in the North America for the second- ceives data streams from an FM discriminator, detects data generation personal communication systems. By assigning using recovered data clock, and performs error detection multiple time slots in a single frequency channel, the channel and correction if it occurs. In transmit unit, the transceiver capacity has increased manyfold and the compatibility with generates predefined streams of data by adding the parity conventional analog system is maintained. Both systems em- bits of message and synchronization sequences. In addition, ploy complex speech compression and sophisticated digital received supervisory audio tone (SAT) is regenerated by a modulation methods to accommodate high-quality voice and phase-locked loop and re-transmitted. In the stand-by mode, data communication with the minimal frequency bandwidth. In only circuits for data reception are enabled to minimize power such systems, low-power and high-performance VLSI play an consumption.
Manuscript received April 8, 1995: revised July 12, 1995. This work was supported in part by the NSF under Grant ECS-9322279 and Samsung Electronic Co. This paper was recommended by Guest Editors A. RodriguezVhzquez and E. SAnchez-Sinencio. The authors are with the Department of Electrical Engineering and Integrated Media Systems Center, University of Southern California, Los Angeles, CA 90089 USA. IEEE Log Number 9415057.

amplifier. This transceiver chip dissipates less than 6 mW in the stand-by mode, making it suitable for battery-powered devices.

A. Analog Fronl-End

The analog front-end for incoming signals contains an antialiasing filter, 20 kHz low-pass filter for data signal, and 6 kHz band-pass filter and interpolator for SAT signal. The ar aliasing filter is a continuous-time active filter. All other 9

1057-7122/95$04.00 @ 1995 IEEE






-I rtP-@20 kHz




Digital PU




6/20ktiz LPF







Fig. 1. Block diagram of Manchester-data transceiver


1 : w-qFrequency Synthesizer@)

i 1 I I RX

Down Conversion ,


t u


Receive Data

1I I

SAT Recovery


+ +






Data Transceiver Fig. 2. Data transceiver VLSI chip in wireless communication systems.

circuits are based on the switched-capacitor (SC) technologies. The low-pass filter is a fifth-order Butterworth filter and is intended to remove all unwanted signal components above 20 kJ3z. Note that when a 10 kbps non-return-to-zero (NRZ) data stream is encoded by the Manchester encoding rule, i.e., lowto-high transition for logic- 1 and high-to-low for logic-0, most of the signal energy is contained in the frequencies below 20 IcHz. The output of the low-pass filter is then converted to NRZ stream by a comparator following the low-pass filter. The band-pass filter for SAT signal has a 200 Hz pass-band centered around 6 Mz. It removes voice-band signals as well as noise. Typically the N-path band-pass filter [7] is preferred in narrow band filtering applications. But the clock frequency requirement does not provide the compatibility with other building blocks. In this design, the filter is realized by

a cascade of three biquads. To reduce the dynamic power dissipation in the filters, the clock frequency fc chosen to be 501) kHz for both filters. When the filtered signal is translated to logic levels, the minimum duration that can be resolved by digital circuits is 1/fc M 3.3 ,us, for which it may be difficult to discriminate the frequencies of SAT signal in high accuracy. To improve the resolution, a linear interpolator driven by a 1.2 MHz clock is used to increase the sampling frequency by a factor of om. Please note that the interpolator can be implemented with a single operational amplifier instead of five amplifiers in the low-pass filter. A significant saving in the static power dissipation and the dynamic power associated with many capacitors in the filter has been achieved. The same comparator or processing the data signal is also used to convert the received SAT signal, which is a single frequency



tone plus noise, to square wave. The comparator acts like a zero-crossing detector. Analog postprocessing circuits for transmit data and SAT signals are also included to minimize the number of external components. The Manchester-encodedtransmit data from digital circuits contains high frequency components above 20 kHz. The transmit filter which has the same specifications as one in the receive section, removes these components for bandlimited FSK modulation. In the conversation mode, however, the clock frequency of the transmit low-pass filter is switched to 100 kHz, for which the cutoff frequency becomes one third of 20 kHz ( ~ 6 . 6 7 kHz). In this mode, the filter can effectively remove all harmonic components from the transmit SAT and retain the fundamental component, which is one of the 5970, 6000, 6030 Hz tones. In the summing amplifier which precedes the filter, two signals are properly scaled such that the modulation requirements are satisfied by using a single external device for level adjustment. In the stand-by mode, both the analog and digital transmit circuits are activated only during the transmission, which occurs intermittently.
B. Digital Transceiver Units

When the receiver operates asynchronously with the transmitter, the time instances at which the data is transmitted must be recovered before making decisions on data bits. As the Manchester-encoded data signal also conveys the clock information through level transitions, it can be readily regenerated using a digital phase-locked loop (DPLL). After the Manchester encoding, signal transitions occur between two consecutive data bits even when they have the same logic level. Therefore, these transitions must be removed first from the input before it is sent to the DPLL. After the symbol timing is obtained from the clock recovery circuit, the Manchester decoding and data detection are performed. The data detection is based on the digital approximation of integrated-and-dump filter and may result in a sub-optimum performance over white Gaussian noise. Frame synchronization, an 11-b Barker sequence [8], and other control bits are extracted afterward for use in the error correction unit. To cope with the deep signal fading, which occurs often during transmission in an urban area, two-fold error protection schemes, the majority voting and BCH coding, are employed in the system. After five repetitions of a data block is received, a bit-wise three-out-offive majority voting is performed. Two consecutive repetitions are 8.8 ms apart. Therefore the information is not affected by a complete signal loss due to fading for a maximum period of 17.6 ms. In the BCH decoder stage, a single bit error can be corrected, based on a successive evaluation of the syndromes. If the error occurs in two or more bits, an uncorrectable error flag is sent outside the chip through the serial interface. In this design, the BCH decoder is capable of correcting many combinations of two-bit error patterns, thus improving the performance. A message to be transmitted is pushed into the TX data buffer which is driven by the external serial data and clock. Upon the receipt of the first bit, the clock signals for analog and digital transmit circuits are activated. Notice that analog

circuits must be stabilized well within the minimum duration of the transfer. When the transfer of the message is completed, the parity of the information is generated and concatenated to form a BCH-encoded message. While the message is being sent out for transmission, the information part is stored in a circular buffer as well to accommodate multiple transmissions for majority voting scheme. This arrangement frees up the TX data buffer for the next message. After the message is transmitted following two sequences for synchronization, it repeats ten more times. After all necessary transmissions, the clock signals for transmit circuits are deactivated. In the conversation mode the analog circuits are turned on all the time for SAT transmission, and are not affected by the intermittent data transmissions. The received noisy SAT signal is regenerated through a DPLL and transmitted back to the transmitting station for the channel monitoring purpose. Furthermore, at every 250 ms its frequency as well as the validity must be determined and compared with one contained in the received message. If two values do not match or it is not a valid SAT, the conversation shall be suspended temporariIy. The DPLL is very similar to that for data timing recovery. However a second-order structure is needed. In a first-order DPLL, the output frequency will be floating over the whole tracking range when no valid signal is present. Thus it is likely that wrong decisions can be made. On the other hand, a second-order loop always pulls its output to one of two extreme frequencies in this case. The regenerated SAT signal is sent to analog circuits for retransmission and to digital circuits for frequency discrimination.

Performance improvements in semiconductor technologies are dramatic in each year and near-gigahertz operation in CMOS technologies has been made possible. Multi-milliontransistor VLSI chips operating at hundreds of megahertz speed [9], [lo] are already in use as personal computing devices. Another rapid change in microelectronic systems is the needs for small-size, lightweight, and low-power integrated circuits as required by the product portability. For example, the current generation of digital cellular telephony employs complex speech compression algorithms and sophisticated digital modulation techniques in a pocket-sized device [ll]. Such a hand-held system can hold a nickel-cadmium battery having 1 A . h or less capacity, with which the system can be fully active for less than half an hour. So far, a high data throughput rate is one of the challenging issues in system design. In the future portable applications, low power techniques are especially important because it is projected that only a trifling (about 30%) improvement in battery capacity
will be obtained over the next five years [6].

Standard digital CMOS technologies have been developed to accommodate the logic circuits with $5 V supply voltage. In mixed analog and digital VLSI circuits, analog building blocks also have been successfully integrated with digital circuits in a single die. As the battq-lifeafpcxtabksystemsbecomes very important, and the transistor feature sizes in VLSI decreased



down to a small fraction of micrometer [12], [13], demands for low-voltage integrated circuits have increased dramatically over past few years. A +3.3 V supply voltage has become an industry standard for low power equipment. Future scaling down of the power supply voltage to the 2 V range can be expected in the year 2000. In the twenty-first Century, CMOS circuits can be efficiently operated with around a 1 V power supply.

2) Class-AB Gain Stage: In circuits with the class-AB

A. Power Consumption in Digital CMOS Circuits

where CL is the load capacitance at the inverter output, f p = l / t p is the clock frequency. In general, total dynamic power dissipation in digital CMOS circuits can be represented as

stage, the quiescent operating current is maintained at a low value. When compared to basic class-A circuits, the class-AB circuits generally achieve better output efficiency. When the bias current of a class-AB amplifier is made adaptive [20], it offers many advantages in micropower circuits. 3) Dynamic Biasing [21]: The bias current at the beginning of a clock cycle is increased to allow fast slewing in a class-A circuits and is decreased to a low quiescent value for the remainder of the clock cycle. 4) Filter Topology [22]: Power consumption in SC filters is dependent on types of feedback networks used in SC realizations. Given performance requirements, an appropriate filter type for low power consumption can be chosen.

C. Sampling Rate Conversion in Switched-Capacitor Filters

The sampling rate conversion is a technique that increases or decreases the sampling rate to achieve better performance with less accurate elements. In cases when high sampling rate is required and the signal frequency of interest is much less than the half of the sampling rate, the use of a cascade of an SC filter with sufficiently low clock frequency and an interpolator, which increases the sampling rate by an integer multiple of that of the preceding filter, is a useful technique for lowering the power consumption as well as the capacitance ratio of the largest and smallest capacitors in the switched-capacitor filters. By using low sampling frequency for the filter, it is appropriate to employ low-speed operational amplifiers too. To achieve good settling behavior, the unity-gain bandwidth W O of a two-stage CMOS operational amplifier should be at least five times as large as the clock frequency w,, where

where ptr is the switching activity factor. and VSW is the voltage swing. The logic swing VSW is the same as the supply voltage VDDin most cases. In single-gate, passtransistor implementation [14], the voltage swing VSW on some internal nodes may be less than VDD. As can be seen from (2), lowering the supply voltage is a straightforward and efficient way to reduce the dynamic power consumption of CMOS circuits. Power consumption can also be saved by minimizing switching activity factor [15], [16], or lowering pre-charge voltage level to VDD- &h instead of the full VDDvalue. To implement selected functions, static logic gates have lower switching activity factors than their dynamic counterparts. By precharging the data node to a value closer to v D D / 2 , it not only saves the amount of energy, but also facilitates fast switching response by biasing the circuit to the sensitive point. Power consumption by a whole circuit block can be significantly saved with aggressive use of the shutdown technique. Accurate prediction of the idle behavior of circuit modules can be achieved with heuristic estimation based on operation history as pioneered by Chandrakasan et al. [17] into the subsecond range.
B. Low-Power Analog CMOS Design

While minimum power-consumption design in analog circuits is very complicated due to the interrelationship of many performance parameters, there are several methods for minimizing power dissipation in SC filters: 1) Current Scaling with Capacitive Loads: Typically, different capacitive loadings occur at different stages of

Here, C, is the feedback capacitance, gmi is the differential transconductance, IO is the bias current, and p is the transconductance parameter of the input differential stage. Given the MOS transistors follow a square-law characteristic, their transconductance gm has a square-root dependence on the bias-current l o for a given device size. Since the clock frequency of the operational amplifier is proportional to the gm of the input-stage, reduction of clock frequency by fourfold implies a reduction in bias current of sixteenfold. Typically, the interpolator requires one operational amplifier. This scheme can save significantly over both static and dynamic power consumption associated with the original SC filter. Fig. 3 shows the I-to-4 sampling rate conversion technique used
in the design. The clock frequency of the band-pass filter is

the filter. If a common amplifier cell is used, it is often over-designed for use in the stages with small capacitive loadings. By optimizing the amplifiers for their corresponding capacitive loading, it can reduce power dissipation by up to 50% in filters with widely varying capacitances [18], [19].

f c / 4 (Hz) and the interpolator following the filter increases the sampling frequency from f c / 4 to fc. If IO is the minimum bias current of an operational amplifier in the sixth-orderbandpass filter operating at a clock frequency fc, then the bias current in the samplingrateamversion scheme can be reduced from 610 to [ 6 . (1/4)2 1110 = 1.87510.



6th-order BandDass Filter

+ I f


spa/ Si(0


To Digital Circuit



Clock Frequency fc





4 fc , 4
To Digital Circuit



so it g n a / BUF < w + A iLPF u




Fig. 4. Analog front-end.

Fig. 3. Sampling-rate conversion scheme.





Active Area' (mm2)

* 2-pm aoubbpoiy CMOS



2 . 0 4

vss Fig. 5. Two-stage CMOS operational amplifier with class-AB output stage.

In addition to reduction in power dissipation, the sampling rate conversion technique also provides a smaller value of Cmax/Cmin where, ,C , and Cmin are the maximum and minimum capacitance values, respectively, required to realize the filter. For example, Cmax/Cmin values are equal to 32 and 10 in the original scheme and the sampling-rate conversion scheme, respectively. Table I summarizes the comparison between the two techniques. Iv. ANALOG FRONT-END Fig. 4 shows the block diagram of the analog front-end for the data transceiver chip. It consists of the receive module which interfaces the digital signal processing block through the comparators and the transmitter module which receives the output signals from the digital function block to generate the output waveforms.
A. Operational Amplijiers



Vdd=+3V, CL=SpF

Fig. 5 shows the circuit schematic diagram of the operational amplifier used throughout the design of the switchedcapacitor circuits. By avoiding the cascode scheme of the transistors, a two-stage amplifier is chosen for achieving large inputloutput ranges with a single +3 V power supply voltage. In order to reduce the standby current of the output stage, the class-AB output stage is used. me simulated and measured results are summarized in Table 11. SPICE simulation [23]-[25] results show the greatly reduction of power dissipation. When the sampling frequency

is 300 kHz and the 2-phase clocking scheme is used, the operational amplifier has to be settled down with 0.1% error during the clock pulse width of 1.67 ps. The power dissipation of the operation,al amplifier is around 0.3 mW. Since the total load capacitance varies for each amplifier, the operational amplifiers are grouped into three types of different values of compensation capacitors (2.5, 5, and 10 pF) according to the load capacitance values to ensure operation stability.
B. Anti-Aliasing Filter and Sample-and-Hold Circuit

The anti-aliasing filter is implemented with the active-RC approach. By usiing the passive resistance element which has








f- 0 d 8 to DC

-20 --40

.......... Simulated Values



Measured Values

-60-F W W

a low sheet resistance value, a large resistor is made with a significant amount of distributed capacitance associated with it. This distributed capacitance is quite big to obtain she additional values and can achieve higher-order attenuation well above the passband frequency. Fig. 6 shows the simulated and measured frequency characteristics of the second-order Rauch filter [26]. Changes in the frequency characteristics due to process variations are also plotted in the figure. When the desired sheet resistance is denoted by Rpoly,it is assumed that the value varies from R,,i,/2 to ~ R , , I ~ It. is clear &at the imperfect characteristic of the passive component is not critical for anti-aliasing low-pass operation. For bilinear s-to-z transformation of the fiIters L271, the sample-and-hold circuit is employed. Two operational amplifiers are used in order to suppress their offset voltage, which appears as the output divided by the voltage gain of the operational amplifier. The sampling capacitance is chosen to be 5 pF with consideration of the speed and the noise performance requirement.
C. Switched-Capacitor Low-Pass and Band-Pass Filters

Fig. 7(a) shows the complete schematic diagram of the fifth-order Butterworth low-pass filter implemented with a switched-capacitor ladder circuit. Fig. 7(b) shows the fifthorder low-pass l U C filter prototype on which the design of the switched-capacitor is based. Since the passband ripple is not allowed, the Butterworth filter scheme is chosen. In order to achieve good sampled-data representation in z-domain, the bilinear s-to-z transformation is used. It requires four additional capacitors, which are calculated to be small values. The integrators are designed to be insensitive to parasitic capacitance. The sample-and-hold circuit is preceded by the filter. The sampling clock frequency is 300 kHz and the 3 dB cutoff frequency is 20 kHz.SWITCAP [28] simulation resuIts of the frequency characteristics and the transient behavior are shown in Fig. 7(c). The SAT signal from the anti-aliasing filter output passes through the band-pass filter in order to remove voice and unwanted noise signals. In our design, three biquad sections performing the band-pass filtering operation are cascaded to construct the sixth order filter. Each biquad section has the same circuit topology, but has its own center frequency and the Q value so that the combined filter achieves the flat pass-

Magnitode ( d e


-20 --


Simulated Values





* (H.4

Fig. 7. Fifth-order low-pass filter. (a) Schematx dlagram. (b) LCR prototype filter. (c) Smulated and measured frequency charactemtics.

band around the desired center frequency and the resultant Q factor. Fig. 8(a) shows the schematic diagram of a biquad SC section for the sixth order band-pass filter. The SWITCAP simulation and measured results are shown in Fig. 8(b). The 3 dB bandwidth is equal to 200 Hz (f100 Hz) centered at 6 kHz.





Magnitude (ds)




..........Simulated Values

Measured Values Frequency

I 1

two branches. One has a voltage gain of 1 and the other has a voltage gain of 1/4. When no input is activated, the analog ground voltage is applied to the circuit. The circuit is insensitive to the parasitic capacitance and the offset voltage of the operational amplifier is compensated. Chopper inverter comparator [29] is employed at the final stage of the receive analog front-end to interface with the digital signal proct:ssing blocks. The operation is guaranteed at the supply voltage down to V D D = &hn \&hp1 2Vnet where &hn,&hp ,are the threshold voltages of nMOS and PMOS transistors, respectively, and Vnet is the net control voltage on both nMOS and PMOS transistors. A typical choice of 2vnet can be around &hn. In the submicron low-power VLSI circuits, if the threshold voltage is aggressively scaled to be around 0.251 V then the required supply voltage can be just 1 V. As shown in Fig. 4, it should operate at both the frequencies of fc = 300 kHz and 4fc = 1.2 MHz. The output of the comparator is stored in the 0-flip flop which is edge-triggered by the delayed clock for obtaining the sufficient setup time.

3 k


1 2 k


A. Digital Phase-lacked Loop

Fig. 10 shows the digital data receiver with the clock recovery circuit using digital phase-locked loop (DPLL). The Manchester-encodled signal contains the 0-to- 1 or 1-to-0 transitions, which occur at the middle point of each symbol. When VIN this signal is applied to the DPLL circuit, the symbol clock -VINT can be recovered at the output. However, when two or more consecutive symbols have the same logic level, the signal also contains trarisitions between two symbols. The DPLL is preceded by the digital monostable circuit as shown in Fig. 10 for removing those transitions. The bit synchronization circuit is designed to detect the dotting sequence, which is contained in the d,ata signal. The dotting sequence is repetition of the 10 pattern and provides a pure 5 kHz clock signal Fig. 9. Circuit schematic of 1-to-4 linear SC interpolator. on a Manchester-encoded format. When it is detected, the DPLL is reset to the zero reference phase at the instance a D.Linear Interpolator, Summing Ampl$er, and Comparator signal transition occurs. This scheme can provide a fast initial The schematic diagram of the switched-capacitor 1:4 linear. operation of the DPLL without widening the bandwidth in the interpolator is shown in Fig. 9. The frequency of two-phase acquisition mode. The received signal is decoded to the nonsignal through the Manchester decoder. clock ($1 and 4 2 ) is 1.2 MHz. The output value of the return-to-zero (NU) interpolator VINT is sampled by $0. The frequency of $0 The sum-and-reset circuit following the decoder approximates is 300 kHz. The difference between the applied input VIN an analog integrate-and-dump filter, which has an optimum and the sampled output VINT appears at the capacitor C1. performance in white Gaussian noise environment. The block diagram of the first-order DPLL circuit is shown By choosing C2/C1 = 4, integration occurs during the next 4 cycles with each increment equal to one quarter of the provided in Fig. 11. Its tracking range is about 20 Hz at a center frequency of 10 W z . Once it is initialized upon the detecdifference. The voltage summing amplifier generates a step-type wave- tion of the dotting sequence, the reset line is disabled to form with the transmit data and SAT signals. Since the output prevent it from being re-initialized by successive pulses. A voltage is followed by the low-pass filter, its magnitude should programmable up/down counter acts as a digital integrator and be within the linear region of the operational amplifier. The its output is attenuated by 4 in the combinational logic circuit. Vss to VDD pulses of transmit data and SAT signals are Attenuation in the feedback loop corresponds to reduction in converted to (VDD - Vss)/3 to ~ ( V D D - Vss)/3 pulses by the tracking range by the same factor as well as the reduction the reference voltage divider and the controlled switches. Since in noise level. The output of the combinational circuit is two voltage gains are required, the signal path is divided into among - 1 , O , + I , which correspond to advance, normal,

Fig. 8. Sixth-order band-pass filter. (a) Biquad section of the filter. (b) Simulated and measured frequency response.




Manchester Decode

Integrate Dump

random noise signal (positive or negative phase error with the same probability) during severe fading, the above-mentioned OUf worst-case phenomenon is almost unlikely to occur and the DPLL can withstand the fading of much longer duration. The Glodctracking range, defined as the range of frequency changes of recovered clock around the center frequency ~ / T D (Hz), is given as


= 2 l A f l = 2 -[To TD+Tc/] = To 2 1 E___ - ___





Digital Phase-Locked Loop

For the values given above, ~ T ~ R 4 Hz, 0 which means that the DPLL is able to track the input frequencies in the range f =1 0 Hf ~ 20Hz.

Fig. 10. All digital receiver for Manchester-encoded data.

Recovered Clock

fixed Dinder

Divider Clock


Presettable Combinatronal UpDown Counter Lo&

Fig. 11. First-order digital phase-locked loop for timing recovery.

and retard in the diagram. If it is a nonzero value, then a single clock pulse is removed or added, to advance or retard lease note the phase Of recovered lock by a fixed that the updown counter is preset to the zero state any nonzero output (-1 or +I). The acquisition time can be calculated as follows: Let T D , Tc(= / . f C ) , and be the timing to be recovered, master clock period, and the attenuation factor, respectively. Assume that the initial phase error is +n or -n, i.e., +To12 or - T D / ~Since . it takes N.T seconds to retard C. Decoding o f BCH Code or advance the output by Tc seconds, the time for the DPLL n e Bose-Chaudhufi-Hocqghem codes are a class of to acquire a complete synchronization is simply cyclic codes whose generator polynomials are chosen to make the minimum distance guaranteed by the lower bound large N T - NTfc (seconds). [3P]. An (n,k)-BCH code has the following parameters TACQ = __ (4) 2 2TC -1 Block length: n = 2 When fc = l/Tc =1.2 MHz, TD = loops, and N = Number of parity digits: n - k <: mt ~ , T A C equals Q to 24 ms. If the input signal is noise-free, then the phase error lies in the range - n / 2 < BE < +n/2 and Minimum distance: d >_ 2t 1 it provides correct decisions on the received data. The average acquisition time is one half of the maximum value determined for any positive integers m and t. Clearly, this code is capable by (4). Similar statements may apply when the DPLL begins of correcting any combination of t or fewer errors in a block to lose the synchronism due to noise or deep signal fading. of n = 2m - 1 digits. Decoding of a BCH code consists of Therefore, the DPLL is able to maintain the phase coherency h e following steps: for up to 12 ms during a deep fading which can cause a , . . . , Szt]from Step 1) Calculate the syndrome S = [ S I52, complete signal loss at the input. However, the input is purely the received vector r ( X ) = T O r l X + . . . + T , - ~ X ~ - ~ ,

B. Majority Voting Circuit In order to reduce data loss during transmission, 40 b information is repeated five times, each being sandwiched between two repetitions of data. This scheme provides a good error protection for deep fading that spans up to 10 20 ms long, and for additive random noise. In the receiver, four 40 b buffers are required to hold received data temporarily. As the fifth repetition is received, a three-out-of-five majority voting is performed in bit-wise and the result is stored back to the first buffer. Each buffer consists of 40 static D-type flipflops and is driven by a separate clock signal. During the fifth O repetition interval, all buffers are clocked simultaneously. T reduce power consumption and required silicon area, chaintype D flip-flop is employed [30]. Slave (or master) latch shares its circuit between two adjacent master (or slave) latches in order to reduce the number of transistors almost by half. An &ansmission gate must be placed between two bvemrsso &at one of &em can switch its functions in each clock phase. Transistor sizes have to be carefully chosen to avoid the charge-sharing problem. The feedback switch is a single wIL ratlo, such that it with a ha-=, a lmge h e constant when passing logic-1 value.



ThresholdLogic CLKI

28-Bit (Double Buffered)





: A n D Flip-Flop
1 .


b Error

Fig. 12. Error-trapping decoder for (40, 28)-BCH code.

where S , = r(olz), i = 1 , 2 , . , 2 t , for a primitive element a of the Galois field GF(2m). Step 2) Find the error location polynomial o ( X ) from
s 1 , s 2 ,* . . S2t.

Step 3) Determine the error location numbers p,,j = 1 , 2 , . . . , t , by finding the roots of a ( X ) . Notice that Step 2 is the most difficult part of decoding a BCH code and Berlekamp [32] has developed an iterative algorithm for finding the error location polynomial. From an implementation point of view, a programmable processor is quite suitable for the decoding algorithm. Thus with some sacrifice in error correctability, an error-trapping scheme is X ) f ( X ) r ( X ) generate the same reused for the decoding of a specific BCH code. An error- Thus, X n - k + l ~ ~ [ and mainder when divided by g(X). The (40, 28)-BCH code is trapping decoder for cyclic codes is based on the following a shortened version of (63, 51)-BCH code with the following two theorems [31]. Theorem 1: If the syndrome of received vector r ( X ) is parameters: 1) with a minimum Hamming distance of 5 taken to be the remainder after dividing X n - k r ( X ) by the 2) can detect four or fewer errors, generator polynomial g ( X ) , and all errors lie in the highest3) can correct two or fewer random errors (t = 2), and . X ), then the nonzero portion of error order n - k symbols of ( 4) with a generator polynomial : g ( X ) = 1 X 3 X 4 pattern appears in the corresponding positions of the syndrome. x 5 x 8 XI0 + x 1 2 . Theorem 2: Let s ( X ) denote the syndrome of r ( X ) . The Then xn-k+Il x 3 5 = syndrome of a cyclic shift of T-( X ), that is, X , ( X ), is obtained d X ) q 2 ( X ) f ( x ) ,where by shifting the syndrome generator of g ( X ) once with initial q2(X) = 1 x4+ x7 X I 0 + X I 1 X I 2 XI4 contents s ( X ) . Once the syndrome of X n - k r ( X ) is obtained in the synX l 6 X l 7 xzl x23 drome register, any error patterns with t or fewer errors confined within n - k consecutive digits can be corrected and by shifting the content of the register successively until the number of nonzero elements is equal to or less than t. If this f ( X )= 1+ X + X ~ + X 4 + X ~ + X 1 0 + X ~ 1 . (7) situation does not happen until the kth shift, an uncorrectable error has been detected. In a shortened version of BCH code The syndrome register that multiplies the received polynomial by 1 digits, i.e., ( n - I, k - Z)-BCH code, it can be regarded r ( X ) by f ( X ) and divides it by g ( X ) is shown in Fig. 12. as the original (n,k)-BCH code with 1 leading zeros. The Received digits are shifted into both syndrome register which first I zeros are always error-free and thus does not affect was set to zero initially, and the data buffer. After 40 shifts, the syndrome calculations. In this case, the syndrome of the register holds s ( X ) , the syndrome of X 3 5 r ( X ) .If the

X"-'"+lr(X) is first calculated. The pre-multiplication by Xnek+' can be accomplished by multiplying r ( X ) by f ( X ) , which is the remainder after dividing Xn-lc+l by the generator polynomial g ( X ) ,If X n - k + l ~ ( X= ) s ( X )+ g ( X ) q l ( X )and Xn-k+l = s ( X k z ( X ) + f ( - n then

+ x+





Clock Recovery


and Dafa Dstecfion

Voting Decoding

Transmit Data

Supervisory Autio Tone isAV

Syndrome Register

..... QI r








Fig. 14. Floor-plan of data transceiver chip.



Fig. 13. Threshold logic circuits. (a) Propagation of partial s u m ( Q 3 = Q7 = Q5 = Q l O = 1). (b) Current comparison.

number of nonzero elements in s ( X ) is less than or equal to 2, the feedback connection for division (SW2) is opened and the content of the syndrome register is added to that of the data buffer as they are shifted out of the register. Otherwise (9) the content of the register with SW2 closed is shifted to the right by one bit to generate the syndrome of X 3 % ( X ) . At the Here S,k = 1. If S,3 = 1,i = 1 , 2 , . . . , t 1, for some same time, the first bit in the data buffer is shifted out as a j , then Sf = 1 , k = j l , . . . , n - k. Notice that if correct digit, because an error has not occurred at this position St+l = 1 for some k = t I , . . . , n - 5 , then Lth = 1. if it is correctable. The procedure repeats until &e number of nonzero elements in the register is less than or equal to 2, Thus Lth = SpGk and no additional decoding circuitry is which corresponds to correctable error patterns. If this situation required. The worst-case propagation delay is ( n - k)T, does not happen until the 28th repetition, an uncorrectable seconds, where T, is the propagation delay in the multiplexer. error has been detected. Notice that, when a correctable error If operating speed is the primary requirement in the circuit, is detected, the error correction operation (SW2 opened, SW3 the circuit shown in Fig. 13(b) may be used. This threshold closed) continues until the final digit because the SR is cleared circuit is based on the comparison of two currents set by the during at most n - k = 12 shifts and the tailing zeros have output of the syndrome register and reference. MOS transistors no effect. This error-trapping decoder is capable of correcting are sized such that current IO flows through each current all one-digit errors and, two-digit errors that are confined source controlled by Q z ,i = 1 , 2 , . . . , n - k and the reference within any 12 consecutive digits. The complete BCH-decoder current is set to f t 0.5)Io. Thus the output of the current 5 t , and 1 otherwise. Since all comparator is 0 if QSum is shown in Fig. 12. current sources are switched at the same time when Q2,i = 1,2, * . . ,n - k , is available, the propagation delay is now D. Threshold Logic T TC seconds, where T and TC are the propagation delays The threshold logic in the error-trapping decoder is a in the current switch and current comparator, respectively. combinational logic circuit that generates logic-0 if the number The complementary switches for current Idummy are provided of nonzero elements in the syndrome register is less than or to improve the switching characteristics of current switches. equal to t, and logic-] otherwise. In other words, if Qi is the For a large ( n - k ) circuit, any mismatch in currents due to ith output from the syndrome register, then device parameter variations and geometrical distribution, may result in erroneous operation. In standard CMOS technologies, n-k-I however, the accuracy of 8 b 10 b weighted-binary is readily achievable [33], [34]. This corresponds to n - k = 256 1024.

Unless t = 1, the threshold logic can be very complex in order to accommodate all combinations of the event QSum 5 t . Fig. 23(a) shows a serial architecture that propagates local sums to the next stage. If Qsum> t at any stage, the remaining stagesaredontcare,andLth= ~ . L e t S ? , i = 1,2,...,t+ 1,k = 1,2,. . . ,n - k , denote the ith local sum at the kth stage. Then

+ +




Poww Dissipation Isill active) Minimum Operating

2-pnlCMOS Double-Poly, Double-Metal


2.6 V

Fig. 15. Die photo of CMOS data transceiver chip.

Simulated Values

Measured Values 65 12

Unit dB MHz V

DC Gain
Unity-Gain Frequency Input Range Output Range Offset Slew Rate Settling Time

69 12


0.14-2.66 6.2



0.36 Vdd=+3V. CG5pF


analogdigital design techniques, it provides a single-chip solution for the processing of data and supervisory audio tone signals. Key analog circuits include an anti-alias filter, two fifth-order low-pass filters, sixth-order band-pass filter, interpolator for sampling rate conversion, and comparators. Digital circuits performs data transmission and reception, error coding and decoding as well as tone detection and regeneration. As !shown in Fig. 14, efficient floor-planning and layout of each block make it possible for the entire transceiver to be integrated into a compact silicon area of 4.6 x 6.8 mm'. The well-characterized blocks are judiciously placed and routed so that the critical signal paths are greatly minimized. In the SC filter blocks, the clocking switches are far separated from the analog signal components to avoid coupling from the digital switching noise. All capacitors are located above the ground-connected p-wells to absorb the undesired noise from the substrate. A unit capacitance size is 20 x 20X2, which corresponds to 240 f F for the given technology with 11X being 1 pm. Capacitor arrays are laid out to minimize the effect due to fabrication-induced area variations. Fig. 15 shows the die photo of the fabricated chip. Fig. 16 shows the measured input and output waveforms of the low-pass filter at 1 and 40 kHz test signals. Table 111 lists some measurement results of the fabricated data transceiver chip. For each functional block, test vector was generated. The test vectors include typical patterns of signals for the verification of the chip. All tests were conducted with a breadboard containing tlhe fabricated chip, EPROM which stores test vectors, and additional supporting logic gates from standard IC parts which generate the control timing. The designed chip has been successfully tested and it meets the specifications for the low-power wireless communication. VII. CONCLUSION The low-power transceiver chip for the dual-mode wireless communication systems was designed, fabricated, and successfully tested. The chip is fully functional at a f 3 V supply voltage. It consumes less than 6 mW when only the receive module is activated. The design knowledge can be applied to the developmemt of the wireless communication modules of future portable electronic systems such as multi-media terminals.

Fig. 16. Measured waveforms of fifth-order low-pass filter. (a) Frequency = 1 kHz,inputloutput scale: 0.2 V/div. (b) Frequency = 40 kHz,input scale: 0.2 V/div., output scale: 20 mV/div.


A low-power, 3 V CMOS data transceiver chip for the

dual-mode wireless mobile communication systems has been designed and fabricated using the 2 pm scaleable CMOS technology from the MOSIS Service of USClInformation Sciences Institute at Marina Del Rey [35]. By using mixed




Valuable comments and suggestions from reviewers are highly appreciated.
REFERENCES [l] B. J. T. Mallinder, An overview of the GSM system, in Proc. DCRC Con$, Hagen FRG, Oct. 1988, pp. l d l - l d l 3 . [2] G. A. Arredondo, J. C. Feggeler, and J. I. Smith, Advanced mobile phone service: Voice and data transmission, Bell Syst. Technol. J., vol. 58, no. 1, pp. 97-122, Jan. 1979. 131 The Electronic Industries Association, Cellular system dud-mode mobile station-base station compatibility standard, ELWTIALS-54-B, Jan. 1992. [4] T. Habuak et al., A single-chip FM modem baseband CMOS LSI for land mobile telephone radio units, IEEE J. Solid-State Circuits, vol. SC-20, pp. 617-622, Apr. 1985. [5] R. W. Brodersen, A. Chandrakasan, and S. Sheng, Design techniques for portable systems, in Proc. IEEE Int. Sotid-State Circuits Con$, San Francisco, CA, Feb. 1993, pp. 168-169. [6] A. P. Chandrakasan and R. W. Brodersen, Low-power CMOS digital design, IEEE J. Solid-state Circuits, vol. 27, pp. 473-484, Apr. 1992. [7] M. B. Ghaderi, J. A. Nossek, and G. C. Temes, Narrow-band switchedcapacitor band-pass filters, IEEE Trans. Circuits Syst., vol. CAS-29, pp. 557-572, Aug. 1982. [8] J. J. Spilker, Jr., Digital Communications by SateZZite. Englewmd Cliffs, NJ: Prentice-Hall, 1977. [9] W. J. Bowhill et al., A 300 MHz 64 b quad-issue CMOS RISC microprocessor, in Tech. Dig. IEEE Int. Solid-State Circuits Con&, San Francisco, CA, Feb. 1995, pp. 182-183. [lo] D. Bearden et al., A 133 M H i 64 b four-issue CMOS microprocessor, in Tech. Dig. IEEE Int. Solid-State Circuits Con$, San Francisco, CA, Feb. 1995, pp. 174-175. [I 11 K. Feher, Modems for US digital cellular and emerging digital mobile radio systems, in Proc. IEEE Int. Con$ Commun., 1991, pp. 19.1.1-7. [12] M. Kakumu and M. Kinugawa, Power-supply voltage impact on circuit performance for half and lower sub-micrometer CMOS LSI, IEEE Trans. Electron Devices, vol. 37, pp. 1902-1908, Aug. 1990. [13] C. G. Sodini, P. K. KO, and J. L. Moll, The effect of high fields on MOS device and circuit performance devices, IEEE Trans. EZecfron Devices, vol. ED-31, pp. 1386-1393, Oct. 1984. [14] K. Yano et al., A 3.8-ns CMOS 16 x 16 multiplier using complementary pass transistor logic, IEEE J. Solid-State Circuits, vol. SC-25, pp. 388-395, Apr. 1990. [15] A. P. Chandrakasan and R. W. Brodersen, Low Power DigitaZ CMOS Design. Boston, MA: Kluwer, 1995. [16] A. Bellaouar and M. I. Elmasry, Low-Power Digital VLSI Design. Boston, MA: Kluwer, 1995. [17] A. P. Chandrakasan and R. W. Brodersen, Minimizing power consumption in digital CMOS circuits, Proc. IEEE, vol. 83, pp. 498-523, Apr. 1995. [lS] W. C. Black, Jr., D. J. Allstot, and R. A. Reed, A high performance low power CMOS channel filter, IEEE J. Solid-state Circuits, vol. SC-15, pp. 929-938, Dec. 1980. [19] D. 5. Allstot and W. C. Black, Jr., Technological design considerations for monolithic MOS switched-capacitor filtering system, Proc. IEEE, vol. 71, pp. 967-986, Aug. 1983. [20] M. G. Degrauwe et al., Adaptive biasing CMOS amplifiers, IEEE J. Solid-state Circuits, vol. SC-17, pp. 522-528, June 1982. [21] B. J. Hosticka, Dynamic CMOS amplifiers, IEEE J. Solid-state Circuits, vol. SC-15, pp. 887-894, Oct. 1980. [22] P. M. Van Peteghem and W. M. C. Sansen, Power consumption versus filter topology in SC filters, IEEE J. Solid-state Circuits, vol. SC-21, pp. 40-47, Feb. 1986. [231 T. Quarks et al., SPICE3 version 3F3 users guide, Dept. Electrical Eng. and Comput. Sci., Univ. California, Berkeley, Apr. 1993. [241 B. J. Sheu, D. L. Scharfetter, P. K. KO,andM.-C. Jeng, BSIM: Berkeley short-channel IGFET model for MOS transistors, IEEE J. Solid-State Circuits, vol. SC-22, pp. 458-466, Aug. 1987. [25] S. M. Gowda, B. J. Sheu, and J. S. Cable, An accurate MOS transistor model for submicron VLSI circuits-BSIM-plus, in IEEE Custom Integrat. Circ. Con$, San Diego, CA, May 1991, pp. 23.2.1-4. [26] B. K. Ahuja, Implementation of active distributed RC antialiasinglsmoothing filters, IEEE J. Solid-state Circuits, vol. SC-17, pp. 1076-1080, Dec. 1982. [27] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. New York: Wiley, 1986.

1281 S. C. Fang, Y. P. Tsividis, and 0. Wing, SWITCAP: A switched capacitor tietwork analysis program, IEEE Circuits Syst. Mag., vol 5, pp. 4-10 and 4146, 1983. [29] A. Matsnzawa, Low voltage mixed analog/digital circuit design for portable equipment, m ZEEE Symp. VLSI Circuits, Kyoto, Japan, May 1993, pp. 49-54. [30] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective. Readmg, MA: Addison-Wiley, 1985. E 3 1 1 W.W. Peterson and E. J. Weldon, Jr., Error-Correcting Codes. Cambridge, MA: MIT Press, 1972. [32] E. R. Berlekamp, Algebraic Coding Theory. New York McGraw-Hill, 1968. [33] T. viiki et al., An 80-MHz 8-bit CMOS D/A converter, IEEE J. Solid-state Circuits, vol. SC-21, pp, 983-988, Dec. 1986. [34] H. J. Schouwenaars, D. W. J. Groeneveld, and H. A. H. Termer, A low-power stem 16-bit CMOS D/A converter for digital audio, IEEE J. Solid-State Circuits, vol. 23, pp. 1290-1297, Dec. 1988. [35] C. Tomovich, MOSIS-A gateway to silicon, IEEE Circ. Dev. Mag., vol. 4, pp. 22-23, Mar. 1988.

Sa H. Bang (S93-M95) was born in Kyungbook, Korea, in 1958. He received the B.S. and M.S. degrees in electrorucs engineering from Hankuk Aviation College (formerly National Aviatlon ColIege of Korea), Seoul, Korea in 1982 and 1984, respectively. From 1984 to 1989, he worked at Samsung Electronics Co., Ltd., where he was responsible for the development of telecomrnumcahon systems. From 1988 to 1989, he was a project manager workmg on handheld moblle phones. During 1989 and 1994, he pursued the graduate study in the Department of Elecmcal Engineenng, at University of Southern Caliornia,working in the area of system architecture and VLSI design for digital communication systems. HIS research interests include circuit and system design and VLSI implementations of communication modules. He has received five Korean patents and one U.S. patent on communication circuits and systems. He has published more than 20 technical papers.

Joongho Choi (M94) was bom in Korea in 1964 He received the B S and M S degrees in electronics engineenng from Seoul National University, Korea, in 1987 and 1989, respectively He received the Ph.D. degree in electncal engineering at the University of Southern California, Los Angeles, CA, in 1993. He is currently workmg at IBM Thomas J Watson Research Center in Yorktown Heights, NY In the master-degree project, he worked on a 32b RISC mcroprocessor and an oversampling AfD converter Dunng 1989 and 1993, he was a research assistant at the VLSI Signal Processing Laboratory at USC and partlcipated in several research orgamzahons at USC mcluding Center for Neural Engineering (CNE), Signal and Image Processing Inshtute (SIPI), and Center for Photonic Technology (CPT) He has been mvolved in various informahon processing VLSI design projects mcludmg art~ficialneural networks, analog and hgital VLSI neuroprocesors, med-signal data processors for mobile communication, oversamphng A/D converter for digital audio, and optoelectronic crcuits for photonic mterconnection and signal processing He has published more than 25 papers m techmcal journals and cohference proceedings He taught a graduate-level course on med-signal VLSI systems at USC in Fall 1993. He co-authored a chapter of the book Analog VLSI e&ted by M Ismad (McGrawHdl, 1994) He is a co-author of the book Neural Information Processing and VLSZ (Kluwer, 1995) HIS research areas include mxed-signal VLSI design for signal processing, neural networks, and mulhmedia communicatlon Dr Choi serves on the Editonal Board of Joumal of Analog ICs and Signal Processing from Kluwer Academc Pubhshers and served on the Technical Program Comnxttee of IEEE International Conference on Neural Networks, 1994 and 1996.



Bing J. Sheu (S81-M85SM91) was born in Taiwan in 1955. He received the B.S.E.E. degree (Honors) in 1978 from the National Taiwan University, the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1983 and 1985, respectively. At National Taiwan University, he was the recipient of the Distinguished Book-Coupon Award seven times. In 1981, he was involved in custom VLSI design for a speech recognition system at Threshold Technologv Inc., Cuuertino, CA. From 1981 to 1982, he was a Teaching Assistant % the EECk Department, UC Berkeley. From 1982 to 1985, he was a Research Assistant in the Electronics Research Laboratory, UC Berkeley, working on digital and analog VLSI circuits for signal processing. In 1985, he joined the faculty in Electrical Engineering Department at University of Southern California and is currently an Associate Professor with a joint appointment in Biomedical Engineering Department. He has been an active researcher in several research organizations at USC including Signal and Image Processing Institute (SIPI), Center for Neural Engineering (CNE), Institute for Robotics and Intelligent Systems (IRIS), and Center for Photonic Technology (CPT). He serves as the Director of VLSI and Signal Processing Laboratory. Since 1983, he has served as a consultant to the microelectronic and information processing industry. His research interests include VLSI chips and systems, massively paralleled neural networks and image processing, and high-speed interconnects and computing. He is an Honorary Consulting Professor in National Chiao Tung University, Hsin-chu, Taiwan. Dr. Sheu was a recipient of the 1987 NSF Engineering Initiation Award and, at UC Berkeley, the Tse-Wei Liu Memorial Fellowship and the Stanley M. Tasheira Scholarship Award. He was also a recipient of the Best Presenter Award at IEEE International Conference on Computer Design in both 1990 and 1991. He is a co-recipient of the Best Paper Award of IEEE Transactions on VLSI Systems in 1995. He has published more than 170 papers in international scientific and technical journals and conferences and is a coauthor of the book Hardware Annealing in Analog VLSI Neurocomputing in 1991, and the book Neural Information Processing and VLSI (Kluwer, 1995) and co-editor of Microsystems Technologyfor Multimedia Applications (IEEE, 1995). He served on the Technical Program Committee of IEEE Custom Integrated Circuits Conference. He served as a Guest Editor of IEEE JOURNAL OF SOLID-STATE CIRCUITS for March 1992 and 1993 Special Issues; a Guest Editor on computer technologies for IEEE TRANSACTIONSON VLSI SYSTEMS for June 1993 Special Issue; an Associate Editor of IEEE TRANSACTIONS ON NEURAL NETWORKS. He is on the Technical Program Committees of IEEE International Conference on Neural Networks, International Conference on Computer Design, and International Symposium on Circuits and Systems. At present, he serves as an Associate Editor of IEEE TRANSACTIONS ON VLSI SYSTEMS; an Associate Editor of IEEE TRANCTIONS ON CIRCUITS AND SYSTEMS, PARTI and PARTE ,and the CAS Editor of IEEE CIRCUITS AND DEVICES MAGAZINE. He also serves on the editorial board, and a guest editor for intelligent microsystems special issue of the Journal of Analog ICs and Signal Processing, Kluwer; and the editorial board of Neurocomputing Journal, Elsevier. He serves as the Tutorials Chair of 1995 IEEE International Symposium on Circuits and Systems; and as the Technical Program Chair of 1996 IEEE International Conference on Neural Networks. He is among the key contributors of the widely used BSIM mode1 in the SPICE circuit simulator. He is a member of International Neural Networks Society, Eta Kappa NU,and Phi Tau Phi Honorary Scholastic Society.

Robert C. Chang (S95) was born in Taiwan in 1965. He received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan in 1987 and 1989, respectively. In 1995, he received the Ph.D. degree in electrical engineering from University of Southern California, Los Angeles, CA. From 1987 to 1989, he was a Research Assistant at National Taiwan University working on signal and image processing. Since 1992, he has been a Research Assistant at USC. In spring 1993, he served as a Teaching Assistant on Mixed-Signal VLSI Systems Design in the Electrical Engineering Department. He worked as a Senior Instructor on the same course in Fall 1994. He served as a co-organizer of the Multimedia Systems Technology session for the IEEE ISCAS Tutorial Program in 1995. He is currently working at Eliectronics Research and Service Organization (ERSO) of Industrial Technology Research Institute (ITRI)in Hsinchu, Taiwan. He has published more than a dozen technical journal and conference papers. His research interests include advanced VLSI for signavimage processing, telecommunication, biological neural networks, intelligent machines, and high-performance computers. Dr. Chang received Outstanding Academic Achievement Award from USC Office for International Students and Scholars in 1995. He is a member of Tau Beta Pi.