Phase-Locked Loops

David Johns, Ken Martin University of Toronto

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D. Johns, K. Martin, 1997

Common PLL Applications

Clock multiplier - input is a fixed frequency clock - output is a higher frequency clock signal that is a multiple of input clock frequency Frequency synthesizer - input is a fixed frequency clock - output is a clock signal with arbitrary frequency Clock and data recovery - input is a data signal (from a serial link) - output is digital data as well as clock signal - phase detector is different than other applications FM demodulation - input is a radio signal - output is demodulated signal
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PLL Basic Architecture

Vin
Phase detector

Vpd

Low-pass filter

H lp(s)

V lp

Gain

K lp

Output voltage

Average voltage proportional to phase difference

Vosc

VCO (voltage controlled oscillator)

Vcntl

In general, output may be V cntl or V osc

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PLL Basics
Feedback causes V in to be phase locked to V osc We start with a simple phase detector of ...
V pd = K M V in V osc K M is a multiplication constant

(1)

Also assume filter is ...

1 + s z H lp ( s ) = ---------------1 + s p

(2)

which is a lead-lag filter. Usually z << p

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Example Waveforms
1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 0

Vin Vpd

Vosc

10

12

14

16

18

20

V in = E in sin ( t ) V osc = E osc sin ( t d + 90 ) = E osc cos ( t d )

(3) (4)

Above shows an example of d 90 (slightly less)

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PLL Basics
Can show
E in E osc V pd = K M ------------------ [ sin ( d ) + sin ( 2 t d ) ] 2

(5)

The lowpass filter removes second term and for small d ...
E in E osc V cntl K lp K M ------------------ d = K lp K pd d 2

(6)

where we define
E in E osc K pd = K M -----------------2

(7)

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PLL Basics
Oscillator frequency given by
osc = K osc V cntl + fr fr is the free running freq of oscillator K osc is the VCO gain constant

(8)

Feedback forces osc to equal in However, if in does not equal fr , and loop filter does NOT have infinite gain at dc, then phase difference when in lock given by:
V cntl in fr d = ----------------- = -----------------------------K lp K pd K lp K pd K osc

(9)

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PLL Linear Model

in ( s ) K pd K lp H lp ( s ) K osc V cntl

osc ( s )

1s

V cntl ( s ) = K pd K lp H lp( s ) [ in( s ) osc( s ) ] K osc V cntl ( s ) osc ( s ) = -----------------------------s

(10) (11)

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PLL Equations
Combining above 2 equations ...
V cntl ( s ) sK pd K lp H lp(s) ------------------ = ---------------------------------------------------- in ( s ) s + K pd K lp K osc H lp(s)

(12)

This is a highpass response from input phase to control voltage Can also be written as
K pd K lp K osc H lp(s) osc ( s ) ---------------- = ---------------------------------------------------s + K pd K lp K osc H lp(s) in ( s )

(13)

This is a lowpass response from input phase to output phase

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Charge Pump PLL

Ich S1 S2 Ich R C1 (de-glitching cap) C2 V lp

Vin Vosc

Sequential phase detector

Pu Pd

Charge-pump phase comparator

Low-pass filter

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Sequential Phase Detector

Vin

Vosc

in
Pu

2
Pd Time

If V in leads V osc , P u (pulse up) goes high for lead time If V osc leads V in , P d (pulse down) goes high for lead time.

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Charge Pump PLL Equations

Average current flowing into lowpass filter is ...
in I avg = ---------- I ch 2

(14)

Lowpass filter is (ignoring C 2 )...

V lp ( s ) 1 + sRC 1 1 H lp ( s ) = ---------------- = ---------------------- = R + -------I avg ( s ) sC 1 sC 1

(15)

which results in
osc ( s ) ( 1 + sRC 1 ) ---------------- = ------------------------------------------------2 in ( s ) s C1 1 + sRC 1 + -------------------K pd K osc

(16)

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Charge Pump PLL Equations

The phase transfer curve is second-order (ignores deglitching cap C 2 ) so 0 and Q can be found as
1 0 = ------- = pll I ch K osc ----------------2 C1

(17) (18)

1 1 2 Q = ----------------- = -- ------------------------RC 1 0 R C 1 I ch K osc

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Charge Pump Example

Let K osc = 2 50 M rad V and I ch = 10 A .
fr = 2 50 M rad s . Desired loop time constant of

100 cycles, or 2 s . Find loop filter components. SOLUTION

1 0 = ---------- = 500 krad s 2 s 1 I ch = 2 nF -K C 1 = ------ ----2 2 osc 0

(19) (20)

Let C 2 = C 1 10 = 2.5 pF and Q = 0.4

1 2 R = --- ------------------------- = 31.4 k Q C 1 I ch K osc
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Phase Frequency Detector

Pu FF1 Reset Set1 Pu-dsbl Set2 Pd-dsbl Pd FF2

Vin

Vosc

FF3

FF4

Set3

Set4

Can be used for sequential phase detector but also works when large frequency differences between osc freq and input freq

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Phase Frequency Detector

Vin Vosc Pu Pd Pu-dsbl Pd-dsbl

Above example is for osc freq much lower than input freq Note that P u is high much longer than P d

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Oscillators
Oscillators

Tuned oscillators

Nonlinear oscillators

RC osc.

SC osc.

LC osc.

Crystal osc.

Relaxation osc.

Ring osc.

Two main classes of oscillators Most common are LC osc and Ring osc (Crystal osc is good but difficult to tune away from center freq)

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Ring Oscillators

Vout

Vout (quadrature)

1 1 f osc = -- = --------------T 2 n inv

(22)

where inv is delay of each inverter

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Fully Differential Delay Stage

IB
Vcntl Vbiasl Vout Vin Vcntl Q3

IB
Q4 Vout

Q1

Q2 2IB

Vin

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V2I Conversion
Q9 Q8 Vbias Vcntl

I
Q6 Q4

Q7
cntl I = -----------

Q5 Q3

To other oscillators

Q1

Q2

2I
First inverter of ring oscillator

Control circuitry

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Alternative Biasing
Ib
Vcntl Q3 Q4 Vref Q2 Q1 From other stages To other stages R2

Ib

R3 Vref

R4

R1

Bias stage

Delay stage

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Computer Simulation of PLLs

Simulation times can be very long due to large variations in time-constants Make use of bilinear transform to simulate analog signals in discrete timesteps. Loop Filter example Impedance looking into loop filter is ... ( G = 1 R )
1 1 - + ------------------Z lp ( s ) = -------sC 1 sC 2 + G

(23)

So voltage to charge relationship is ...

V lp ( s ) G + s ( C1 + C2 ) --------------- = ------------------------------------GC 1 + sC 1 C 2 Q lp ( s )

(24)

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Discrete-time loop filter

Use bilinear transform
2 1 z 1 s -- --------------- 1 T1 + z

(25)

giving
V lp ( z ) 2 ( 1 z 1 ) ( C 1 + C 2 ) + GT ( 1 + z 1 ) M ( z ) = --------------- = ------------------------------------------------------------------------------------ 1 1 Q lp ( z ) 2 C 1 C 2 ( 1 z ) + C 1 GT ( 1 + z )

(26)

which can be written as

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V lp ( z ) m1 + m2 z 1 P ( z ) = ------------------ = --------------------------------------------------------------- 1 2 Q lp ( z ) 1 + z (k 2) + z (1 k)
1 m + m z 1 1 2 = --------------- --------------------------------- 1 z 1 1 z 1 + kz 1

(27)

where
2 GC 1 T k = ----------------D 2 ( C 1 + C 2 ) + GT m 1 = ----------------------------------------D 2 ( C 1 + C 2 ) + GT m 2 = ---------------------------------------------D D = 2 C 1 C 2 + GC 1 T
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(28) (29) (30) (31)

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Discrete-time Loop Filter

X2(z) X1(z) Q(z) z1 k z1 m1 m2 Vlp(z)

Can use Matlab, Simulink, C, etc to simulate

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A Fractional-N Frequency Synthesizer

Use oversampling within a PLL
f xt f xt ---M M
phase detect loop filter VCO

crystal osc

Nf xt --------PM

N N = { k-1, k, k+1 }

A digital controlled oscillator

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