Basic Opamp Design and Compensation

David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu)

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D.A. Johns, K. Martin, 1997

Transistor Model Summary

General Constants
Transistor charge

q = 1.602 10 k = 1.38 10

19

C JK
1 16

Boltzman constant

23

Intrinsic silicon carrier concentration (300 K)

n i = 1.1 10

carriers/m

K ox 3.9 Relative permittivity of silicon K s 11.8

Relative permittivity of oxide

MOS Transistor Parameters

Electron mobility (typical) Hole mobility (typical)

n = 0.05 m 2 V s

p = 0.02 m 2 V s Oxide thickness (typical) t ox = 0.02 m

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D.A. Johns, K. Martin, 1997

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Transistor Model Summary

Gate capacitance per unit area C ox Device parameters (typ)

K ox o 3 2 = ------------- 1.9 10 pF/ ( m ) t ox

2 2

n C ox = 90 A/V , p C ox = 30 A/V Threshold voltages (typical) V tn = 0.8 V , V tp = 0.9 V

Threshold voltage adjustment

V tn = V tn -0 + ( V SB + 2 F 2 F )
12

= 0.5 V Fermi potential difference (typical) F = 0.35 V

Body effect parameter (typical)

Effective Gate-Source Voltage, V eff

Effective gate-source voltage

V eff V GS V tn

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D.A. Johns, K. Martin, 1997

Triode and Active Regions

2 V DS W - ( V GS V tn ) V DS -------I D = n C ox ---L 2

ID

V GS constant n C ox W I D = ---------------- ( V GS V tn ) 2 2 L

W I D n C ox ---- ( V V tn ) V DS L GS

Triode Region
V DS,sat

Active Region

V DS
V DS,sat = V eff

Cutoff Region

Cutoff Region: V GS < V tn Triode Region: V GS > V tn , V DS V eff Active Region: V GS > V tn , V DS V eff
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D.A. Johns, K. Martin, 1997

MOS Triode Equations

Region of operation V GS > V tn , V DS V eff
Drain current

ID

W = n C ox --- L

V DS ( V GS V tn ) V DS 1.7 -------2

1.7 typical term is due to body effect along channel

Small-Signal Model in Triode Region ( for V DS << V eff )

Vg

Cgs Vs Csb

rds

Cgd Vd Cdb

1 r ds = ---------------------------------W n C ox ---- V L eff

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D.A. Johns, K. Martin, 1997

MOS Active (or Pinch-Off) Equations

Region of operation V GS > V tn , V DS V eff
Drain current

ID

n C ox W 2 - ---- ( V GS V tn ) [ 1 + ( V DS V eff ) ] = ------------- 2 L 1 --------------------------------------------L V DG + V tn + 0.9 V eff = V GS V tn = 2 ID ------------------------------ n C ox ( W L )

Output impedance constant

0.9 term is due to built-in junction potential Effective gate-source voltage (ignoring output impedance)

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D.A. Johns, K. Martin, 1997

MOS Active Equations

Small-Signal Model (Active Region)
Cgd vg Cgs vgs gmvgs gsvs rds Cdb vd

Csb

vs

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D.A. Johns, K. Martin, 1997

MOS Active Equations

Transconductance Transconductance Transconductance

W - V g m = n C ox --- L eff gm = gm 2 n C ox ( W L ) I D 2 ID = -------V eff

gm Body effect transconductance g s = ---------------------------------2 V SB + 2 F Body effect transconductance (typical) g s 0.2 g m 1 Output impedance r ds = ------- ID L6 V DG + V tn where = 5 10 Output impedance r ds ---ID
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Vm
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D.A. Johns, K. Martin, 1997

Two-Stage CMOS Opamp

Useful for describing many opamp design concepts Still used for low voltage applications

C cmp

V in

A1

A2

V out

Differential input stage

Second gain stage

Output buffer

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D.A. Johns, K. Martin, 1997

Two-Stage CMOS Opamp

Q10 25 Q11 25 Q5 300 Ibias VDD Q6 300 500 Q8 Q14 25 Q12 25 Vin Q1 300 300 Q2 Vin+ Vout

100 Q15 Rb Q13

25

Q16

CC

300 150 Q3 Bias circuitry Q4 150 VSS Q7 Common-source second stage

500 Q9 Output buffer

Differential-input first stage

all transistor lengths = 1.6 um

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D.A. Johns, K. Martin, 1997

Opamp Gain
3rd stage NOT included if driving capacitive loads Typical gains of 50-100 for each of stage 1 and 2 First Stage Differential to single-ended A v 1 = g m 1 ( r ds 2 || r ds 4 ) gm1 = Second Stage Common-source gain A v 2 = g m 7 ( r ds 6 || r ds 7 )
(3) (1)

W 2 p C ox ---- I = L 1 D1

W I bias 2 p C ox ---- -------- L1 2

(2)

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D.A. Johns, K. Martin, 1997

Opamp Gain
Third Stage Source follower Typical gain slightly less than 1 (say 0.9) Note g ds = 1 r ds and G L = 1 R L gm8 A v 3 -------------------------------------------------------------------G L + g m 8 + g s 8 + g ds 8 + g ds 9 g s is body-effect conductance and equals zero if source tied to substrate G L is the load conductance at output
(4)

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D.A. Johns, K. Martin, 1997

Frequency Response
Q5 Vbias vin+ Q1 300 Q2 300 v1 CC v2 300

vin

A3 1
150 150 Q3 Q4 i = gm1 vin A2 A3

vout

C eq = C C ( 1 + A 2 )

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D.A. Johns, K. Martin, 1997

Frequency Response
C C dominates at all freq except unity-gain freq Ignore Q 16 for now (used for lead compensation) Miller effect results in ( C eq = C C ( 1 + A 2 ) ) C C A 2 At midband freq A 1 = g m 1 Z out = g m 1 ( sC C A 2 ) Overall gain (assuming A 3 1 ) A v(s) = A 2 A 1 = g m 1 ( sC C ) resulting in a unity-gain frequency of ta = g m 1 C C
University of Toronto (8) (7) (6) (5)

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D.A. Johns, K. Martin, 1997

Freq Response
First-order model 20 log ( A 1 A 2 ) Gain (dB) 0 p1 p1 ta -20 dB/decade ta g m 1 C C ta Freq (log)

Phase (degrees) 90 180

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Freq (log)

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D.A. Johns, K. Martin, 1997

Slew Rate
Max rate output changes when input signal large All Q5 bias current goes into Q1 or Q2 d v out SR ----------dt IC ID5 2 ID1 C max = ---------------- = ------- = ---------CC CC CC
(9)

max

I D 1 is nominal bias current of input transistors Using C C = g m 1 ta and g m 1 = W 2 p C ox ---- I L 1 D1

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D.A. Johns, K. Martin, 1997

Slew Rate
2 ID1 SR = -------------------------------------------------- ta = V eff 1 ta 2 p C ox ( W L ) 1 I D 1 where V eff 1 = 2 ID1 --------------------------------- p C ox ( W L ) 1
(10)

Normally, little control over t a for a given power diss Increase slew-rate by increasing V eff 1 This is one of main reasons for using p-channel input stage higher slew-rate

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D.A. Johns, K. Martin, 1997

Systematic Offset Voltage

To ensure inherent offset voltage does not exist, design should satisfy ( W L )7 ( W L )6 ------------------ = 2 -----------------( W L )4 ( W L )5 Ensures nominal current through Q7 equals Q6 Found by noting ID5 = 2 ID3 = 2 ID4 and V GS 7 = V DS 3 = V GS 4 then setting I D 7 = I D 6
(13) (12) (11)

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D.A. Johns, K. Martin, 1997

N-Channel or P-Channel Input Stage

Can also build complement opamp with an n-channel input diff pair and second-stage p-channel stage P-channel Advantages Higher slew-rate For fixed bias current, V eff is larger (assuming similar widths used for max gain) Higher unity-gain freq higher transconductance of second stage which is proportional to unity-gain freq Lower 1/f noise holes less likely to be trapped pchannel transistors have lower 1/f noise N-channel Advantage Lower thermal noise thermal noise is lowered by high transconductance of first stage

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D.A. Johns, K. Martin, 1997

Opamp Compensation

V in(s)

A(s)

V out (s)

Feedback circuit assumed to be freq independent R1 = ----------------R1 + R2

V out A(s) C1 A(s)

R2 R1

C2 = -----------------C1 + C2
C2 V out

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D.A. Johns, K. Martin, 1997

General Opamp Compensation

Model A(s) by A0 A ( s ) = ---------------------------------------------------------( 1 + s p 1 ) ( 1 + s eq ) p1 first dominant-pole frequency eq pole frequency modelling higher-freq poles. eq found from simulation frequency with 135 phase shift (90 due to p1 and another 45 due to higherfrequency poles and zeros) Closed loop gain given by A(s) A CL ( s ) = ----------------------1 + A(s)
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D.A. Johns, K. Martin, 1997

General Opamp Compensation

A CL 0 A CL ( s ) = -----------------------------------------------------------------------------------------------------------s ( 1 p 1 + 1 eq ) s2 1 + --------------------------------------------- + ---------------------------------------------1 + A0 ( 1 + A 0 ) ( p 1 eq ) where A CL 0 = A 0 ( 1 + A 0 ) 1 Compare to a general second-order equation K 0 K H 2 ( s ) = --------------------------------------- = ----------------------------------2 2 0 2 s s s + ----- s + 0 1 + ---------+ ------- Q 2 0 Q
0 2 (17) (16)

% overshoot = 100 e
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---------------------2 4Q 1

(18)

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D.A. Johns, K. Martin, 1997

General Opamp Compensation

Equating 2 equations above results in 0 = ( 1 + A 0 ) ( p 1 eq ) A 0 p 1 eq
(19)

( 1 + A 0 ) p 1 eq A0 p1 Q = ------------------------------------------------- -----------------1 p 1 + 1 eq eq

(20)

To find relationship between Q and phase-margin we look at the loop gain, LG(s) A0 LG ( s ) = A ( s ) = ---------------------------------------------------------( 1 + s p 1 ) ( 1 + s eq ) To find a relationship for the loop-gain unity-gain freq LG(j t) = 1
(22) (21)

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D.A. Johns, K. Martin, 1997

General Opamp Compensation

And rearrange and use approx that t p 1
2 A0 p1 t t ------------------ = -------- 1 + -------- eq eq eq (23)

so that Q =
2 t t -------- 1 + -------- eq eq (24)

Would also like to relate phase-margin with t eq and Q factor

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D.A. Johns, K. Martin, 1997

Phase-Margin
Loop Gain (dB)
20 log ( LG(j ) )

-20 dB/decade

p1 p1

ta ta

Freq (log)

(gain margin)
Freq (log)

GM

Phase 0 Loop Gain (degrees) 90 180

(phase margin)

PM

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D.A. Johns, K. Martin, 1997

General Opamp Compensation

PM = L G ( j t ) ( 180 ) = 90 tan 1 ( t eq ) where p 1 adds 90 phase shift t eq = tan ( 90 PM )
(26)
(25)

If non-dominant poles remains unchanged, t independent of for optimally compensated circuit!

PM (Phase margin) 55 60 65 70 75

t eq
0.700 0.580 0.470 0.360 0.270

Q factor 0.925 0.817 0.717 0.622 0.527

Percentage overshoot for a step input 13.3% 8.7% 4.7% 1.4% 0.008%

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D.A. Johns, K. Martin, 1997

Compensating the 2-Stage Opamp

Q5 Vbias1 300 VDD Q6 300

Q1 Vin300 300

Q2 Vin+ Vbias2 Q16 Cc Vout2

150 Q3 Q4

150

300 Q7

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D.A. Johns, K. Martin, 1997

Compensating the 2-Stage Opamp

v1 RC CC v out g m7 v 1 R2 C2

g m1 v

in

R1

C1

Q 16 has V DS 16 = 0 and is hard in the triode region. 1 R C = r ds 16 = -------------------------------------------W n C ox ---- V L 16 eff 16 Small signal analysis without R C present, right-half plane zero occurs and worsens phase-margin
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D.A. Johns, K. Martin, 1997

(27)

Compensating the 2-Stage Opamp

Including R C (through Q16) places zero at 1 z = ---------------------------------------CC ( 1 gm7 RC ) Zero moved to left-half plane to aid compensation Good practical choice is z = 1.2 t satisfied by letting 1 R C ---------------1.2 g m 1 since t g m 1 C C and z 1 ( R C C C ) if R C 1 g m 7
(30) (29) (28)

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D.A. Johns, K. Martin, 1997

1) Find CC with Rc=0 for a 55o phase margin Arbitrarily choose C C 5 pF and set R C = 0 Using SPICE, find frequency t where a 125 phase shift exists, define gain as A Choose new C C so t becomes unity-gain frequency of the loop gain results in a 55 phase margin. Achieved by setting C C = C C A Might need to iterate on C C a couple of times using SPICE

Design Procedure

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D.A. Johns, K. Martin, 1997

Design Procedure
2) Choose RC according to 1 R C = -------------------1.2 t C C Increases t by about 20 percent, leaving zero near final t Check that gain continues to decrease at frequencies above the new t 3) If phase margin not adequate, increase CC while leaving RC constant
(31)

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D.A. Johns, K. Martin, 1997

Design Procedure
4) Replace RC by a transistor 1 R C = r ds 16 = -------------------------------------------W n C ox ---- V L 16 eff 16 SPICE can be used again to fine-tune the device dimensions to optimize phase margin
(32)

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D.A. Johns, K. Martin, 1997

Process and Temperature Independence

Can show non-dominant pole roughly given by g m7 p2 -----------------C1 + C2 Recall zero given by 1 z = ---------------------------------------CC ( 1 gm7 RC ) If R C tracks inverse of g m 7 then zero will track p2 1 R C = r ds 16 = ------------------------------------------------- n C ox ( W L ) 16 V eff 16 g m7 = n C ox ( W L ) 7 V eff 7
(35) (36) (34) (33)

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D.A. Johns, K. Martin, 1997

Process and Temperature Independence

Need to ensure V eff16 V eff7 independent of process and temperature variations
Vbias Q11 25 Q6 300

Q12

25 Va 25 CC 300 Vb Q7

Q16

Q13

First set V eff13 = V eff7 which makes V a = V b

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D.A. Johns, K. Martin, 1997

Process and Temperature Independence

2 ID7 ---------------------------------- = n C ox ( W L ) 7 2 I D 13 ----------------------------------- n C ox ( W L ) 13
(37)

( W L )7 ID7 --------- = --------------------I D 13 ( W L ) 13 Since V a = V b and gates of Q12 and Q16 same V eff12 = V eff16 2 I D 13 -----------------------------------V eff 7 V eff 13 n C ox ( W L ) 13 ------------ = ------------ = ---------------------------------------- = V eff 16 V eff 12 2 I D 12 ----------------------------------- n C ox ( W L ) 12
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(38)

(39)

( W L ) 12 --------------------( W L ) 13

(40)

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D.A. Johns, K. Martin, 1997

Stable Transconductance Biasing

Q10 25 Q11

Can bias on-chip gm to a resistor

25

V GS 13 = V GS 15 + I D 15 R B
2 I D 13 ---------------------------------- = n C ox ( W L ) 13 2 I D 15 ----------------------------------+I R n C ox ( W L ) 15 D 15 B

(41) (42)

Q14 25

Q12 25

But I D13 = I D15 and rearrange

W L 13 2 -------------------------------------------------- 1 --------------- = RB W L 15 2 n C ox ( W L ) 13 I D 13

(43)

100 Q15 RB Q13

Recall g m 13 =
25

2 n C ox ( W L ) 13 I D 13
(44)

g m 13

( W L ) 13 = 2 1 --------------------- R B ( W L ) 15

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D.A. Johns, K. Martin, 1997

Stable Transconductance Biasing

Transconductance of Q 13 determined by geometric ratios only Independent of power-supply voltages, process parameters, temperature, etc. For special case ( W L ) 15 = 4 ( W L ) 13 g m 13 1 = ----RB
(45)

Note that high-temp will decrease mobility and hence increase effective gate-source voltages Roughly 25% increase for 100 degree increase Requires a start-up circuit (might have all 0 currents)

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D.A. Johns, K. Martin, 1997