An Analysis of Full Adder Cells for Low-Power Data

Oriented Adders Design

Ireneusz Brzozowski
1, 2
, Damian Pays
1
, Andrzej Kos
1, 2
1
AGH University of Science and Technology
Department of electronics
Krakow, Poland
ireneusz.brzozowski@agh.edu.pl
2
The Bronisaw Markiewicz State Higher School of Technology and Economics,
Jarosaw, Poland


AbstractThis paper presents results of analyses of full
adders structures to build of low-power adders for specific data.
At first four 1-bit full adder cells were selected from literature,
designed in UMC 180nm technology and simulated for
assessment of theirs energetic and time parameters. Extended
power consumption model, taking into consideration input vector
changes, was used, giving more accurate values than traditional
model, based on switching activity only. Obtained results allow
analyzing what structure of full adder should be used for specific
data summation. So, such model and analyses can lead to
developing of data oriented low power design methods. Based on
energetic parameters assessed for 1-bit full adders, multi-bit
adders were considered. Theirs power consumption versus
summed data was analyzed.
Index TermsAdder; low-power design; power consumption;
energetic parameters; CMOS technology; layout design
I. INTRODUCTION
A summation is one of fundamental operations performed
in today computer systems. It is the most important in digital
signal processing, which is related to all kinds of digital
filtration and digital audio and video processing, ubiquitous in
today mobile devices. Taking into account execution of a
program by the processor, processing digital signal in real time,
adding operation is about 72% of all executed instructions in a
prototype DLX, RISC processor [1]. However, in popular and
widely used processors with ARM core, adding operation is
almost 80% of theirs execution time [2]. Therefore,
multidimensional optimization of adders used in today
processors design is very important. In this paper authors take
into account four popular structures of 1-bit full adders in
aspect of power consumption. The main purpose of the paper is
to propose a method of selecting the best design solution of the
adder to processing of strictly specified data. So, based on
examples of adders, designed in UMC 180nm CMOS
technology and extended power consumption modeling,
appropriate assessment of energy parameters is done. Next
some analyses and conclusions are presented.
Adder it is arithmetic circuit, which adds two N-bit
numbers. The result is N-bit number and one bit of carry.
Additionally carry input can be taken into consideration. The
basic circuit, which allows building adders of any size, is 1-bit
full adder. There are several strategies for basic cells
connection to build larger adders. The sum (s
i
) and carry (c
i+1
)
outputs of 1-bit full adder, summing a
i
, b
i
, and c
i
(carry input),
can be described by following equations:

i i i i
b a c s = (1)

i i i i i i i
c b c a b a c + + =
+1
(2)
It can be directly implemented in CMOS technology after
using of deMorgan laws. But another implementation can be
finding if (1) will be transform.
II. CELL STRUCTURES OF 1-BIT FULL ADDERS
A. Standard CMOS Adder
First considered structure of 1-bit full adder is conventional
CMOS circuit consists of 28 transistors [3]. Transforming (1)
to the following formula:

i i i i i i i i
c b a c b a c s + + + =
+
) (
1
(3)
and using complex gates, with appropriate transistors reducing,
the schematic diagram of the T28 full adder is shown in Fig. 1.
The work carried out was supported by the National Science Center
Poland project no. N N 515 500340

Figure 1. The standard 28-transistor CMOS full adder
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Twelve of transistors are used to produce carry output
function, and remaining sixteen ones for sum output.
Additionally, delay of carry output is added to delay of sum,
which is delay of whole circuit. Relatively large number of
transistors beside complexity of theirs interconnections can
cause high power consumption. But from other hand it is fully
complementary circuit. It has high robustness and can its
operation is independent of supply voltage.
B. Transmision Gate Adder
The adder is built using a set of appropriate connected
transmission gates in such a way that input signal is transmitted
to the output in order to implement of summation operation. It
can be perceived as extended pass transistor logic technique.
Full transmission gates require complementary signals for
theirs control and additional inverters are added to the circuit.
In consequence TGA considered in this paper consists of 12
transistors in transmission gates and remaining of total 20, are
used in inverters [3]. Fig. 2 shows schematic diagram of the
adder.
Usage of full transmission gates instead of single transistors
ensures full voltage swing at the circuit outputs. This adder has
lower number of transistors than previous, but from other hand
there are no isolations between inputs and outputs.
C. Bridge Style Adder
In bridge design style of circuits an additional transistor is
used and it is called bridge. The transistors create a conditional
conjunction between two circuit nodes. And in consequence
new path from supply to the output can be formed [4]. If the
full adder is described by functions represented in sums of
product as follows:

i i i i i i i i i i i i i
i i i i i i i i i i i i i
c b a c b a c b a c b a c
c b a c b a c b a c b a s
+ + + =
+ + + =
+1
(4)
then it can be implemented with bridge design style, as shown
in Fig. 3. Frames in the figure mark bridge transistors. That
implementation requires using of 26 transistors for sum and
carry function. But each input has to be negated, so three
inverters are needed. The total number of transistors is 32. It is
disadvantage, but this adder has bigger operating frequency
than standard one.
D. Dual Value Logic Adder
DVL technique is a kind of pass-transistor logic. Synthesis
method of such circuits consists in employing Karnaugh-Map
at transistor level. So, there are not cascading several logic
gates in order to implement a given function. Instead, the
function is built by directly using several transistor levels in
series. It is explained with example function in Fig. 4 [5]. It can
be observed, that for realization of a function instead of supply
and ground input variables are used. In consequence it reduces
number of transistors, but degrades a swing of output voltage.
Based on this technique 1-bit full adder was designed [6].
Its schematic diagram is shown in Fig. 5. The adder consists of
12 transistors for summation operation implementation and 11
for carry function. Additionally three inverters are needed.

Figure 2. TGA 20-transistor full adder


Figure 3. Bridge style 1-bit full adder
a) b)
BC
A
00 01 11 10

BC
A
00 01 11 10
0
0 1 0 0
0
0 1 0 0
1
0 1 0 1
1
0 1 0 1


Figure 4. Realization of example function in CMOS (a) and DVL (b)
C AB C B F + =
847
Thus, overall number of transistors is 29. But used inverters
have good advantage in performance, and they improve output
voltage swing. From other hand, it causes increasing power
consumption due to switching of the inverters.
III. PARAMETERS ASSESSMENT OF 1-BIT FULL ADDERS
A. Layouts of Adders
Four described above adders are designed in CMOS UMC
180nm technology using Cadence software. Dimensions of
transistors were set like in symmetrical inverter. Transistors
NMOS are as small as possible and PMOS appropriately wider.
Layouts of the designed circuits are shown in Fig. 6 to Fig. 9.
B. Model of Power Dissipation
Authors used extended model of power dissipation. This
model in comparison with traditional one is more accurate but
it needs little bit more calculation effort and allows detailed
analysis of power consumption taking into account specific set
of processed data. Generally the model is capacitive type and
based on equivalent capacitance and gate driving way as
activity factor [7]. This activity factor takes into account
probability of changes of input vectors. Inputs of a circuit are
driven together (vector of primary inputs), not separately.
Generally, this is a probability of a change of the gate input
vector between two values [8]. For considered gate it is needed
to take into account all possible changes of input vectors. Thus
for n-input gate it gives 2
2n
changes. Fig. 10 shows all driving
ways for 2-input gate.
The second parameter of the power model is equivalent
capacitance. It is value of capacitor, which causes the same
power consumption as considered circuit for one change of the
Figure 5. DVL full adder

Figure 6. Layout of the adder Sum1 conventional 28T Figure 7. Layout of the adder Sum2 designed with TGA technique

Figure 8. Layout of the adder Sum3 designed in bridge styl Figure 9. Layout of the adder Sum4 designed with DVL technique
84S
input vector. The capacitor represents current flowing through
the gate terminals. The currents are measured for each change
of the gate input vectors. Inputs and supply terminal are taken
into account. Values of currents and supply voltage are used for
calculation of the equivalent capacitances. Considering all
possible changes of input vectors, tables similar to that shown
in Fig. 10 are obtained for each terminal of the gate. Generally
the model of power consumption can be represented as shown
in Fig. 11, with set of tables containing energy parameters
equivalent capacitance for each terminal of the gate.
C. Simulation Results
Based on layouts of designed adders, netlists were extracted
with RC parasitic elements taken into account. Simulations
were done in conditions allowing obtaining equivalent
capacitance for above described extended power model. All
possible changes of input vectors were ensured in one
simulation thanks to proper definition of input signals
(specially prepared PWL). Input signals had such parameters
that only dynamic, capacitive power consumption occurred in
tested circuits. Proper time parameters of input signals assure
that there was no quasi-short. Moreover, authors assumed that
static lose in used technology (180nm) can be omitted.
Obtained results of equivalent capacitance are collected in
tables. Capacitance connected with supply terminal are called
internal load and denoted by C
Lint
. Input load are marked by
C
LinX
for input X. The sum of capacitances for all terminals
is denoted by C
Lall
. Tab. I and Tab. II contain equivalent
capacitance of internal load C
Lint
and all capacitance C
Lall
,
respectively, for standard 28T adder (sum1). Next tables
present only values of all capacitance for remaining adders.
Additionally for easy comparison of adders sum of all values of
equivalent capacitances are presented in Tab. VI.
Numbers collected in tables although precisely represent
properties of circuits, but they are difficult to fast comparison.
Therefore, obtained results of energy parameters assessment of
designed adders are presented in diagrams. Fig. 12 shows
collected values of internal load C
Lint
for all adders, and next
diagrams present input C
Lin
, and the total capacitance C
Lall
respectively (Fig. 13 and Fig. 14).
TABLE I. EQUIV. CAP. CLINT FOR ADDER SUM1 CONV. 28T [fF]
Next vector
000 001 010 011 100 101 110 111
P
r
e
s
e
n
t

v
e
c
t
o
r
000 0.00 3.50 2.82 7.43 3.04 6.84 7.80 3.58
001 11.00 0.00 0.66 9.84 0.68 9.52 9.24 0.59
010 12.15 3.40 0.00 11.14 0.58 10.26 9.52 1.58
011 14.96 17.73 16.53 0.00 15.77 0.45 0.38 2.94
100 12.64 3.87 1.75 11.86 0.00 10.88 10.35 2.43
101 15.20 18.01 17.29 2.01 16.41 0.00 1.36 3.64
110 16.57 20.22 18.37 3.99 17.74 2.31 0.00 4.65
111 26.22 21.88 20.53 12.15 17.23 11.04 10.07 0.00
TABLE II. ALL EQUIV. CAP. CLALL FOR ADDER SUM1 STAND. 28T [fF]
Next vector
000 001 010 011 100 101 110 111
P
r
e
s
e
n
t

v
e
c
t
o
r
000 0.00 11.72 13.39 26.21 14.09 26.04 29.68 34.11
001 11.00 0.00 11.15 20.46 11.72 20.47 31.13 22.96
010 12.15 10.82 0.00 18.80 11.64 28.82 21.09 21.13
011 14.96 17.75 16.05 0.00 26.75 11.45 11.68 14.83
100 12.64 11.26 11.55 29.49 0.00 18.50 20.97 21.05
101 15.20 18.02 26.67 11.62 16.30 0.00 11.38 14.43
110 16.57 27.62 17.92 10.96 17.67 9.65 0.00 12.94
111 26.22 21.32 20.15 11.19 17.29 10.53 10.09 0.00
TABLE III. ALL EQUIV. CAP. CLALL FOR ADDER SUM2 TGA20T[fF]
Next vector
000 001 010 011 100 101 110 111
P
r
e
s
e
n
t

v
e
c
t
o
r
000 0.00 9.04 19.97 30.39 23.17 26.23 17.74 26.19
001 6.61 0.00 26.87 22.10 29.40 19.18 23.95 17.43
010 16.32 28.93 0.00 10.76 12.56 23.50 21.12 28.58
011 22.87 19.15 9.16 0.00 21.57 12.56 28.14 18.39
100 15.70 27.62 12.64 23.46 0.00 10.76 19.38 26.51
101 20.44 18.48 21.78 12.69 9.16 0.00 25.36 16.68
110 10.76 19.73 20.80 31.22 19.26 22.69 0.00 9.02
111 17.45 10.75 28.12 22.98 26.33 14.81 6.62 0.00
TABLE IV. ALL EQUIV. CAP. CLALL FOR ADDER SUM3 BSA26T[fF]
Next vector
000 001 010 011 100 101 110 111
P
r
e
s
e
n
t

v
e
c
t
o
r
000 0.00 14.09 18.94 20.29 18.79 23.87 28.64 40.27
001 12.02 0.00 21.27 17.91 25.69 18.84 37.73 33.44
010 13.68 16.05 0.00 17.89 26.77 36.28 24.45 29.77
011 21.20 20.10 22.74 0.00 39.61 27.51 23.61 27.16
100 16.75 20.68 28.36 37.32 0.00 17.12 21.44 27.09
101 26.32 19.84 39.81 26.28 19.51 0.00 19.20 18.43
110 28.49 36.08 26.26 21.09 22.28 16.83 0.00 18.47
111 34.32 24.48 23.93 19.28 20.83 13.50 15.42 0.00
TABLE V. ALL EQUIV. CAP. CLALL FOR ADDER SUM4 DVL29T[fF]
Next vector
000 001 010 011 100 101 110 111
P
r
e
s
e
n
t

v
e
c
t
o
r
000 0.00 22.27 27.78 34.56 11.32 30.64 36.83 43.89
001 17.20 0.00 27.98 25.21 23.79 12.76 39.31 33.63
010 21.99 29.42 0.00 22.41 28.58 39.36 13.56 28.88
011 28.29 23.17 18.43 0.00 38.15 26.49 22.04 11.54
100 8.98 26.66 31.99 42.67 0.00 22.94 29.02 33.88
101 23.11 11.31 37.00 29.04 18.82 0.00 27.50 24.80
110 30.91 38.35 11.87 24.72 24.98 27.95 0.00 20.11
111 36.11 28.27 23.65 9.23 27.36 20.50 15.05 0.00
TABLE VI. SUM OF EQIV. CAP. FOR 1-BIT ADDERS
CLall [fF] Cin [fF]
sum1_1bit 991,248 466,625
sum2_1bit 1039,062 583,386
sum3_1bit 1338,023 324,649
sum4_1bit 1446,206 746,438
Figure 10. All possible changes of input vectors for 2-in. gate.
Figure 11. Power model with equivalent capacitance for 3-in. NAND gate
849
Based on tables or diagrams and analyzing values of
equivalent capacitance for single change of an input vector
differences among power consumption of adders can be
observed. Results of such analysis can be used for proper
choose of adder structure considering given set of data for
processing. But for precise characterization of adders
probability of input data changes are needed.
In this paper authors concentrate on power consumption
mainly, but time parameters are important too. So, proper
simulations were done for assessment of delay and maximum
operating frequency of designed 1-bit full adders. Circuits were
simulated with load of 15fF. It corresponds to about four inputs
of inverters. Results of time delay t
pHL
, t
pLH
, and average of
these values t
p
are presented in Tab.VI.
Maximum operating frequency was determined for critical
path in the circuit with load of one inverter. Rising and falling
time of input signals were set to 25ps. It was assumed, that
maximum frequency is as high as possible, such that, logic
levels at a circuit output were possible to distinguish yet.
Obtained approximate values are shown in Tab. VII.
TABLE VII. DELAY TIME FOR ALL INPUTS AND OUTPUTS IN
ADDERS [ps]
a
d
d
e
r
out.
in.
SUM Cout
a
d
d
e
r
out.
in.
SUM Cout
tpLH tpHL tp tpLH tpHL tp tpLH tpHL tp tpLH tpHL tp
s
u
m
1
A 334 585 460 375 635 505
s
u
m
3
A 719 810 765 500 621 561
B 535 730 633 436 578 507 B 519 920 720 556 720 638
Cin 254 776 515 382 674 528 Cin 762 721 742 704 680 692
s
u
m
2
A 410 696 553 521 618 570
s
u
m
4
A 432 551 492 320 541 431
B 407 622 515 401 510 456 B 253 740 497 454 632 543
Cin 110 125 118 109 127 118 Cin 253 298 276 249 267 258
TABLE VIII. MAXIMUM OPERATION FREQUENCY OF ADDERS [GHZ]
adder sum1 sum2 sum3 sum4
fmax 3.33 2.22 1.14 2.33
path B to SUM A to Cout A to SUM B to Cout
Figure 12. Equivalent internal capacitance CLint of all adders
Figure 13. Equivalent total input capacitance CLin of all adders
Figure 14. All equivalent capacitance CLall of all designed adders
0-1 0-2 0-3 0-4 0-5 0-6 0-7 1-0 1-2 1-3 1-4 1-5 1-6 1-7 2-0 2-1 2-3 2-4 2-5 2-6 2-7 3-0 3-1 3-2 3-4 3-5 3-6 3-7 4-0 4-1 4-2 4-3 4-5 4-6 4-7 5-0 5-1 5-2 5-3 5-4 5-6 5-7 6-0 6-1 6-2 6-3 6-4 6-5 6-7 7-0 7-1 7-2 7-3 7-4 7-5 7-6
-10
0
10
20
30
40
changes of input vectors (present - next)
e
q
u
i
v
.

c
a
p
c
i
t
a
n
c
e

[
f
F
]
Equivalent capacitance C
Lint


sum1 sum2 sum3 sum4
0-1 0-2 0-3 0-4 0-5 0-6 0-7 1-0 1-2 1-3 1-4 1-5 1-6 1-7 2-0 2-1 2-3 2-4 2-5 2-6 2-7 3-0 3-1 3-2 3-4 3-5 3-6 3-7 4-0 4-1 4-2 4-3 4-5 4-6 4-7 5-0 5-1 5-2 5-3 5-4 5-6 5-7 6-0 6-1 6-2 6-3 6-4 6-5 6-7 7-0 7-1 7-2 7-3 7-4 7-5 7-6
-5
0
5
10
15
20
25
30
35
40
changes of input vectors (present - next)
e
q
u
i
v
.

c
a
p
c
i
t
a
n
c
e

[
f
F
]
Equivalent capacitance C
Lin


sum1 sum2 sum3 sum4
0-1 0-2 0-3 0-4 0-5 0-6 0-7 1-0 1-2 1-3 1-4 1-5 1-6 1-7 2-0 2-1 2-3 2-4 2-5 2-6 2-7 3-0 3-1 3-2 3-4 3-5 3-6 3-7 4-0 4-1 4-2 4-3 4-5 4-6 4-7 5-0 5-1 5-2 5-3 5-4 5-6 5-7 6-0 6-1 6-2 6-3 6-4 6-5 6-7 7-0 7-1 7-2 7-3 7-4 7-5 7-6
0
5
10
15
20
25
30
35
40
45
changes of input vectors (present - next)
e
q
u
i
v
.

c
a
p
c
i
t
a
n
c
e

[
f
F
]
Equivalent capacitance C
Lall


sum1 sum2 sum3 sum4
80
IV. MULTI-BIT ADDESRS
One-bit full adders are usually used for building of large
adders. There are many structures in respect of carry
generation. Authors, for example, considered ripple carry
adders built with previously designed 1-bit full adders. Theirs
energy parameters were assessed too. But in this case
simulation technique was not needed. Authors developed a
method based on choosing and summing of appropriate data
from tables obtained for 1-bit adders. As previously the same
power dissipation model was used. Sum of equivalent
capacitance for multi-bit adders made of designed 1-bit full
adders are collected in Tab. IX. It can be observed, that
obtained values are smaller than appropriate values from Tab.
VI multiplied by number of adders. It is correct, because not all
driving ways of 1-bit adders occurred in multi-bit adders,
although for primary inputs of multi-bit adders all driving way
were applied. The one number of equivalent capacitance covers
subtle differences, which are seen when gate driving ways are
considered. So, for example, fragment of equivalent
capacitance versus driving way of 4-bit adders is shown in
Fig. 15. Below, in Fig 16 values sorted in descending order are
presented, but description of the vertical axe is different for
each adder, so it is general.
TABLE IX. SUM OF EQUIV. CAP. FOR MULTI-BIT ADDERS
2-bit 3-bit 4-bit 5-bit 2-bit 3-bit 4-bit 5-bit
CLall [fF] CLall [fF]
sum1 435,6 1531,8 3712,3 7348,9 171,7 595,8 1371,4 2677,2
sum2 467,2 1658,1 4037,7 8016,0 176,9 592,0 1394,8 2712,4
sum3 595,5 2085,7 5044,0 9971,9 121,7 410,2 971,6 1896,6
sum4 621,1 2203,9 5363,6 10642,5 132,4 448,3 1032,9 2083,1
V. CONCLUSION
The paper, based on results of adders power consumption,
presents an attempt to take into consideration detailed energy
parameters of building blocks during design of circuits, which
will process specific data. It is possible thanks to extended
power dissipation model. The model takes into consideration
subtle dependencies of a circuit operation during power
consumption analysis.
Four structures of 1-bit full adders were chosen from literature
and designed in 180nm CMOS technology. The assessment
procedure under extended power model was presented. Obtained
results can be next used for proper selection of 1-bit adder for
built of low-power multi-bit adder but information about
processed data is needed. And it needs further investigations.
REFERENCES
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[3] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design.
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CMOS Full-Adder Cell, Journal of Computers, Vol. 3, No. 2, February
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[7] I. Brzozowski, A. Kos, Two-Level Logic Synthesis for Low Power
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th
IEEE
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(DDECS), Krakw, Poland, April 11-13, 2007, pp. 139-144.
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Figure 15. Total equivalent capacitance CLall of all 4-bit adders (fragment)
Figure 16. Total equiv. capacitance CLall of all 4-bit adders sorted in descending order
2,7-4,0 2,7-4,1 2,7-4,2 2,7-4,3 2,7-4,4 2,7-4,5 2,7-4,6 2,7-4,7 2,7-4,8 2,7-4,9 2,7-4,102,7-4,112,7-4,122,7-4,132,7-4,142,7-4,15 2,7-5,0 2,7-5,1 2,7-5,2 2,7-5,3 2,7-5,4 2,7-5,5 2,7-5,6 2,7-5,7 2,7-5,8 2,7-5,9 2,7-5,102,7-5,112,7-5,122,7-5,132,7-5,142,7-5,15
0
0.5
1
1.5
2
Equivalent capacitance C
Lall
4-bit adders
changes of input numbers A,B (presaent - next)
e
q
u
i
v
.

c
a
p
c
i
t
a
n
c
e

[
a
F
]


8-bit sum1 8-bit sum2 8-bit sum3 8-bit sum4

0
0.5
1
1.5
2
2.5
changes of input numbers
e
q
u
i
v
.

c
a
p
c
i
t
a
n
c
e

[
a
F
]
Equivalent capacitance C
Lall
4-bit adders


8-bit sum1 8-bit sum2 8-bit sum3 8-bit sum4
81