Real-time fluorescence lifetime imaging system with a 32 32 0.

13m CMOS low dark-count single-photon avalanche diode array

Day-Uei Li1,*, Jochen Arlt2, Justin Richardson1,3, Richard Walker1,3, Alex Buts1, Stoppa4, Edoardo Charbon5, and Robert Henderson1
1

Institute for Integrated Micro and Nano Systems, Joint Research Institute for Signal & Image Processing/Integrated Systems/Energy/Civil and Environmental Engineering, School of Engineering, University of Edinburgh, Faraday Building, The Kings Buildings, Edinburgh EH9 3JL, Scotland, UK 2 School of Physics and Astronomy, University of Edinburgh, Joseph Black Building, The Kings Buildings, Edinburgh EH9 3JJ, Scotland, UK 3 Imaging Division, ST Microelectronics, Edinburgh EH12 7BF, Scotland, UK 4 Smart Optical Sensors and Interfaces, Fondazione Bruno Kessler, Trento, Italy 5 EEMCS Faculty, Delft University of Technology, Mekelweg 4, 2628CD Delft, Neitherlands

Abstract A fluorescence life time detector based on modified IEM algorithm on FPGA with SPAD pixel array. Modified IEM Algorithm:
When , Also, we know that for Integral, we have Rombergs coefficient. Multiply And or Then life time can be calculated only with With this algorithm, only addition, substraction and shifting is needed, precision is lifetime-independent, and a threshold value is available for futher requirements.
Fig. 1. Concept of IEM algorithm Fig. 3 Simulation Results: a: lifetime 200h b: lifetime 10h

HDL Simulation:

, the fluorescence decay function is the life time. , and use Rombergs Method , both side of the equation, then we have: , so is the
Fig. 2 (SPAD detection model and IEM implementation on FPGA for a single SPAD

For hardware implementation, we choose , and .

SPAD Detection Model: imitates SPAD+TDC output PRBS: imitates a SPAD pixel, produces 31 bits random photon count, CLK frequency equals to 1/h. LUT: with 1024 exponential set thresholds, 10 bits output, imitates TDC with jitter. IEM Implementation Count and , every time input suits, add 1. And calculate lifetime of FPGA.

Implementation:
Bin width h : 50ps or 160ps (Resolution of SPAD TDC) Laser pulse rate: 20MHz SPAD frame rate: 500kHz

Experiment:

Fig.4 IEM FPGA implementation and data path and Imager assembly on an EPFL LASP motherboard.

h=50ps: System reset and wait => One laser pluse => SPAD start sampling for at most 1024 50ps=51.2ns ~ 50ns, TDC start => first photon received => TDC, SPAD stops => 50ns all TDC stop => all pixel stop, TDCs output transmit => FIRST, LAST counter +1 or +0 => SPADs TDCs reset, wait => h=160ps: System reset and wait => One laser pluse => SPAD start sampling for at most 50ns (1024 160ps=163.84ns >> 50ns), TDC start => first photon received => TDC, SPAD stops => Stop signal arrives => all pixel stop, TDCs output transmit => FIRST, LAST counter +1 or +0 => SPADs TDCs reset,
Fig.5 Rhodamine B in water and ethanol mixing.

Possible future work: Fill factor of this design is 2%, which is very low. Since only photon counts of the first and last bin is needed for lifetime calculation, when , we may use SPAD with out TDCs and use the following timing for lifetime calculation. SPAD output 0 or 1 to counter FIRST Laser Pluse and LAST, two delay t circuits are needed. T1
T2 h
Fig. 6 Future work Timing