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Contents
Introduction Processing Steps
Wafer Formation Photolithography Well & Channel Formation Silicon Dioxide Isolation Gate Oxide Gate & Source/Drain Formation Contacts & Metallization Passivation Metrology
INTRODUCTION
PROCESSING STEPS
WAFER FORMATION
PHOTOLITHOGRAPHY
Wafer coated with Photoresist(PR). Subject to selective illumination through Photomask(PM). PM-constructed with Chromium covered Quartz glass. UV light source floods from backside. UV light passes clear sections of Mask to expose the PR coated on Wafer. PR changes property after being exposed on UV.
PHOTOLITHOGRAPHY continued
Developer Solvent used to dissolve soluble unexposed PR, leaving islands of insoluble exposed PR. PM aka Reticle is smaller than Wafer. Stepper/Scanner moves Reticle. Projection Printing-lenses between Reticle & Wafer focus the pattern on Wafer surface.
PHOTOLITHOGRAPHY continued
Resolution Enhancement Techniques
wavelength of UV influences feature size that can be printed. Can cause distortion in the patterns exposed on the PR.
Optical Proximity Correction(OPC) Phase Shift Masks(PSM) Off Axis Illumination(OAI) Most recent one: Immersion lithography technique
Ion Implantation
Thick PR(3.5-5.5 um) used to block ion implantation Si substrate subjected to highly energized donor or acceptor ions(injected) Hit the surface and travel below forming regions with varying doping concentrations Rapid Thermal Annealing(RTA) step-At T>800C, dopants redistribute uniformly
Advantage of Ion Implantation over Thermal Diffusion-No need to raise wafer Temp. -Improves throughput & reliability
ISOLATION
GATE OXIDE
Gate Oxide grown on top of planarized structure Oxide structure is called Stack Few atomic layers, each 3-4 Angstrom thick of SiO2 overlaid with oxynitrided oxide N increases k, which decreases EOT, thus performs like thin oxide
Gate Oxide grown where ever Transistor is required (A=S+D+G). Elsewhere there will be thick Oxide. Deposit Polysilicon. Pattern Polysilicon(both Gate & Interconnect). Etch Exposed Gate Oxide(area of gate oxide not covered by polysilicon). Implant pMOS & nMOS S/D regions through windows down to well & substrate. Lightly Doped Drain-exhibit low C, high R-reduces device performance
Metallization
Process of building wires to connect the devices. Al used. Al deposited either by Evaporation or Sputtering.
Sputtering
Ionize inert gas using RF or DC field. Gas Plasma produced. Ions are focused on Al target. Plasma dislodges metal atoms which are then deposited on wafer.
Metallization Scheme
Uniform layer thickness from 2nd to n-1 layer. Successively thicker & wider metal from lower to upper.
Metrology
SEM-Scanning Electron Microscope. Raster scans the structure and observes secondary electron emission to produce an image of the surface of the structure.
SOI Type-SiO2
Si substrate is used Buried Oxide(BOX) grown on top of it Thin Si layer grown on top of it Si layer selectively implanted to form nMOS & pMOS transistor regions Gate, Source & Drain defined
Cu Damascene Process
Barrier to prevent Cu atoms from diffusing into Si & dielectric. Barrier layer over prior metallization layer. Via dielectric laid down. A further barrier layer patterned. Line dielectric layered on top of structure.
Antireflective layer added to top(helps in litho) Two dielectrics etched away where lines & vias required. Barrier layer of Ta or TaN film (conductive) deposited to prevent Cu from diffusing into dielectric. Cu seed layer coated over barrier layer. Resulted structure electroplated full of Cu. CMP.
Metal-Insulator-Metal(MIM)
Common capacitor used in CMOS process Placed between layer n(top) and n-1 to minimise stray capacitance of bottom plate Insulator-Alumina(Al2O3), Tantalum Pentoxide C=1-4 fF/um2 Area efficient capacitors
Fringe Capacitor
Composed of interdigitated metal fingers Sucessive metal layers can be ganged to get more C
CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTS-TRANSMISSION LINES Used on a chip to provide known impedance wire Microstrip TL
Wire of width w placed over ground plane Dielectric of height h and dielectric constant k Wire can be top level of metallization and ground plane next metal down
Coplaner Waveguide
Wire of width w spaced s on each side from coplaner ground wires
Normal Operation
Floating gate determines if transistor is conducting To program- source is left floating & control gate is raised to appx. 20 V. e tunnel into floating gate thus conduction. To deprogram- drain & source are left floating & substrate(or well) connected to 20V. E stored on floating gate are attracted away leaving the gate unprogrammed.
CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTSBIPOLAR TRANSISTORS BiCMOS Process-npn & pnp transistors added to CMOS process Used for specialized analog or HV circuits Parasitic pnp Transistor in n well process
P-substrate collector N-well base P-diffusion emitter
Micro Electro Mechanical Systems CMOS Process used to make MEMS Air Bag Sensor
References
CMOS VLSI Design- Weste & Harris http://web.cecs.pdx.edu/~chiang/ECE_425_525_Winter_2011/
Questions?