Practical - 1. VHDL Introduction: Design Flow

PRACTICAL -1.
VHDL INTRODUCTION
There are basically two Hardware Description Language: VHDL and Verilog. VHDL (VHSIC hardware
description language) is a hardware description language used in electronic design automation to describe
digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
VHSIC is itself an abbreviation for Very High Speed Integrated Circuits. It is developed by United States
Department of Defense in the 1980s. Its firs version was VHDL 87, latter upgraded to the VHDL-93.
VHDL is the original and first hardware description language to be standardized by the Institute of
Electrical and Electronics Engineers, through IEEE 1076 standard. The IEEE 1164 standard was later
added to introduce a mutivalued logic system.
VHDL is used for circuit synthesis as well as circuit simulation. The main advantage of VHDL over
Verilog is that VHDL is a standard, technology/vendor independent language, portable and reusable. The
two main applications of VHDL are in the Logic Devices and FPGAs- Field Programmable Gate Arrays)
and in the field of ASICs (Application Specific Integrated Circuits). After the VHDL code has been
written, it can be used to implement the circuit in a programmable device (i.e. Altera, Xilinx, Atmel, etc.)
or can be submitted to a foundry for fabrication of an ASIC chip. Many complex commercial chip like
microcontrollers, USART etc. can be designed using such an approach.
Design Flow
As discussed in the introduction of VHDL, one of the major utilities of VHDL is that it allows the
synthesis of a circuit or system in a programmable device (PLD or FPGA) or in an ASIC. The steps
followed during a project are summarized in figure 1. We start the design by writing the VHDL code,
which is saved in a file with the extension .vhd and the same name as its entitys name. the first step in the
synthesis process is compilation. Compilation is the conversion of the high level VHDL language, which
describes the circuit at the Register Transfer Level (RTL), into a netlist at the gate level. The second step
is optimization, which is performed on the gate-level netlist for speed or for area. At this stage, the design
can be simulated. Finally, a place route software will generate the physical layout for a PLD/FPGA chip
or will generate the masks for an ASIC.
Figure 1: Design Flow
VHDL Code Structure
As shown in figure 2, any VHDL code is composed of at least three fundament sections:
Library declarations: Contains a list of all libraries to be used in the design. For example: ieee,
std, work, etc.
Entity: Specifies the I/O pins of the circuit.
Architecture : Contains the VHDL code proper, which describes how the circuit should behave
Figure 2 : Fundaments sections of a basic VHDL code
Library
A Library is a collection of commonly used pieces of code. Placing such pieces inside a library allows
them to be reused or shared by the other designs. The typical structure of a library is shown in figure 3.
The code is usually written in the form of Functions, Procedures, or Components which are placed inside
Packages, and then complied into the destination library. To declare a Library two lines of code are
needed, one containing the name of the library, and the other a use clause as shown in the syntax below.
Figure 3: Fundamental Parts of a Library
PRACTICAL -2. VHDL ENTITIES AND CODING STYLES

AIM:- TO STUDY VHDL ENTITIES AND CODING STYLES
Entity
An ENTITY is a list with specifications of all input and output pins (PORTS) of the circuit. Its syntax is shown
below.
The mode of the signal can be in, out, inout, or buffer. In and out are truly unidirectional pins, while Inout
is bidirectional. Buffer is used when the output signal must be used internally.
Architecture
The ARCHITECTURE is a description of how the circuit should behave. Its syntax is the following:
As shown above, an architecture has two parts: a declarative part (optional), where signals and
constants (among others) are declared, and the code part (from BEGIN down). Like in the case of an
entity, the name of an architecture can be basically any name (except VHDL reserved words),
including the same name as the entitys.
VHDL coding Styles

The internal details of an entity are specified by an architecture body using any of the following modeling
styles:
1. Data flow : As a set of concurrent assignment statements

2. Behavior : As a set of sequential assignment statements
3. Structure : As a set of interconnected components
4. As any combination of the above three.
Data flow
In this modeling style, the flow of data through the entity is expressed using concurrent (parallel) signal.
The concurrent statements in VHDL are WHEN and GENERATE. Besides them, assignments using
only operators (AND, NOT, +, *, sll, etc.) can also be used to construct concurrent code. Finally, a
special kind of assignment, called BLOCK, can also be employed in this kind of code. In summary,
in concurrent code the following can be used:
Operators
The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
The GENERATE statement;

The BLOCK statement.
This types of modeling style is used in the following program.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gate_and is
Port ( a : in std_logic;
b : in std_logic;
t : out std_logic);
end gate_and;
architecture Behavioral of gate_and is
begin
t<= a and b ;
end Behavioral;
Behavioral
In this modeling style, the behavior of an entity as set of statements is executed sequentially in
the specified order. Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE
are sequential. PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that
are executed sequentially. However, as a whole, any of these blocks is still concurrent with any
other statements placed outside it. One important aspect of behavior code is that it is not limited to
sequential logic. Indeed, with it we can build sequential circuits as well as combinational circuits. The
behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted to be
used in sequential code only. VARIABLE can never be global, so its value can not be passed out
directly.
library IEEE;
entity nand is
b : in std_logic;
c : out std_logic);
end nand;
architecture Behavioral of nand is
begin
process (a,b)
begin
if ((a='1') and (b='1')) then
c<='0';
else
c<='1';
End if;
end process;
end Behavioral;
Structural
In this modeling an entity is described as a set of interconnected components. A component
instantiation statement is a concurrent statement. Therefore the order of these statements is not
important. The structural style of modeling describes only an interconnection of
components(viewed as black boxes), without implying any behavior of the components
themselves nor of the entity that they collectively represent. In these modeling architecture body is
composed of two parts: the declarative part (before the keyword begin) and the statement part
(after the keyword begin).
library IEEE;
entity str_nand is
Port ( x : in std_logic;
y : in std_logic;
z : out std_logic);
end str_nand;
architecture Behavioral of str_nand is
component and1
port (a,b: in std_logic; c: out std_logic);
end component;
component inv_1
port (h: in std_logic ;f: out std_logic);
end component;
signal h: std_logic;
begin
x1: and1 port map (x,y,h);
x2: inv_1 port map (h,z);
end Behavioral;
-- for And1 Gate component
entity and1 is
b : in std_logic;
c : out std_logic);
end and1;
architecture Behavioral of and1 is
begin
c<= a and b;
end Behavioral;
-- for inv_1 Gate component
entity inv_1 is
Port ( h : in std_logic;
f : out std_logic);
end inv_1;
architecture Behavioral of inv_1 is
begin
f <= not h;
end Behavioral;
PRACTICAL-3. SIGNALS AND DATA TYPES

AIM:-TO STUDY SIGNALS AND DATA TYPES
CONSTANT
CONSTANT serves to establish default values. Its syntax is given below.
CONSTANT name : type := value;

Examples: CONSTANT set_bit : std_logic := '0';
A CONSTANT can be declared in a PACKAGE, ENTITY, or ARCHITECTURE. When
declared in a package, it is truly global, for the package can be used by several entities. When
declared in an entity (after PORT), it is global to all architectures that follow that entity. Finally, when
declared in an architecture, it is global only to that architectures code. The most common places
to find a CONSTANT declaration is in an ARCHITECTURE or in a PACKAGE.
SIGNAL
SIGNAL serves to pass values in and out the circuit, as well as between its internal units. In other
words, a signal represents circuit interconnects (wires). For instance, all PORTS of an ENTITY
are signals by default. Its syntax is the following:
SIGNAL name : type [range] [:= initial _value];
Examples:
SIGNAL control: std_logic <= '0';
SIGNAL count: INTEGER RANGE 0 TO 100; SIGNAL y:
STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE
A VARIABLE represents only local information. It can only be used inside a PROCESS,
FUNCTION, or PROCEDURE and its value can not be passed out directly. On the other hand, its
update is immediate, so the new value can be promptly used in the next line of code. To declare a
VARIABLE, the following syntax should be used:
VARIABLE name: type [range] [:= init _value];
Examples:
VARIABLE control: std_logic := '0';

VARIABLE count: INTEGER RANGE 0 TO 100;
VARIABLE y: STD _LOGIC _VECTOR (7 DOWNTO 0):= "10001000";
Since a VARIABLE can only be used in sequential code, its declaration can only be done in the
declarative part of a PROCESS, FUNCTION, or PROCEDURE.
Comparison between SIGNAL and VARIABLE.
Assignment
SIGNAL
<=
VARIABLE
:=
Utility
Scope
Represents circuit interconnects (wires)

Can be global (seen by entire code)
Represents local information

Local (visible only inside the
corresponding PROCESS,
FUNCTION, or PROCEDURE)
Behavior
Update is not immediate in sequential

code (new value generally only available
at the conclusion of the PROCESS,
FUNCTION, or PROCEDURE)
Updated immediately (new value

can be used in the next line of
code)
Usage
In a PACKAGE, ENTITY, or
ARCHITECTURE. In an ENTITY, all
PORTS are SIGNALS by default
Only in sequential code, that is,

in a PROCESS, FUNCTION,
or PROCEDURE
CONSTANT and SIGNAL can be global, and can be used in either type of code, concurrent or
sequential. A VARIABLE, on the other hand, is local, for it can only be used inside a piece of
sequential code (that is, in a PROCESS, FUNCTION, or PROCEDURE) and its value can never
be passed out directly.
Data Types
Pre-Defined Data Types
VHDL contains a series of pre-defined data types, specified through the IEEE 1076 and IEEE 1164
standards. More specifically, such data type definitions can be found in the following packages /
libraries:
Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL data types.
Package std_logic_1164 of library ieee: Defines STD_LOGIC and STD_ULOGIC data types.
Package std_logic_arith of library ieee: Defines SIGNED and UNSIGNED data types,
plus several data conversion functions, like conv_integer(p), conv_unsigned(p, b),
conv_signed(p, b), and conv_std_logic_vector(p, b).
10
Packages std_logic_signed and std_logic_unsigned of library ieee: Contain functions that allow
operations with STD_LOGIC_VECTOR data to be performed as if the data were of type
SIGNED or UNSIGNED, respectively.
All pre-defined data types (specified in the packages/libraries listed above) are described
below.
BIT (and BIT_VECTOR): 2-level logic (0, 1).

Examples: SIGNAL x: BIT;
Here x is declared as a one-digit signal of type BIT.
SIGNAL y: BIT_VECTOR (3 DOWNTO 0);
Here y is a 4-bit vector, with the leftmost bit being the MSB.
SIGNAL w: BIT _VECTOR (0 TO 7);
here w is an 8-bit vector, with the rightmost bit being the MSB.
STD_LOGIC (and STD_LOGIC_VECTOR): 8-valued logic system introduced in the IEEE

1164 standard.
X
0
1
Z
W
L
H
Forcing Unknown (synthesizable unknown)

Forcing Low (synthesizable logic 1)
Forcing High (synthesizable logic 0)
High impedance (synthesizable tri-state buer)
Weak unknown
Weak low
Weak high
Dont care
Examples:
SIGNAL x: STD _LOGIC;
Here x is declared as a one -digit (scalar) signal of type STD_LOGIC.
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";
here y is declared as a 4 -bit vector, with the leftmost bit being the MSB. The initial
value (optional) of y is "0001". Notice that the ":=" operator is used to establish the
initial value.
Most of the std_logic levels are intended for simulation only. However, 0, 1, and Z are
synthesizable with no restrictions. With respect to the weak values, they are resolved in favor of the
forcing values in multiply-driven nodes . Indeed, if any two std_logic signals are connected to the
same node, then conflicting logic levels are automatically resolved according to table 1.
TABLE 1 Resolved logic system (STD_LOGIC).
11
X
0
1
Z
W
L
H
-
X
X
X
X
X
X
X
X
0
X
0
0
0
X
X X X X X
0X 0 0 0
1 1 1 1 1
1 Z W L H
1 W W W W
1 L W L W
1 H W W H
X X X X X
X
0X
X
X
X
X
X
X
STD_ULOGIC (STD_ULOGIC_VECTOR): 9-level logic system introduced in the IEEE

1164 standard (U, X, 0, 1, Z, W, L, H, ). Indeed, the STD_LOGIC system
described above is a subtype of STD_ULOGIC. The latter includes an extra logic value, U,
which stands for unresolved. Thus, contrary to STD_LOGIC, conflicting logic levels are not
automatically resolved here, so output wires should never be connected together directly.
However, if two output wires are never supposed to be connected together, this logic system
can be used to detect design errors.
BOOLEAN: True, False.
INTEGER: 32-bit integers (from 2,147,483,647 to +2,147,483,647).
NATURAL: Non-negative integers (from 0 to +2,147,483,647).
REAL: Real numbers ranging from 1 .0E38 to + 1 .0E38. Not synthesizable.
Physical literals: Used to inform physical quantities, like time, voltage, etc. Useful in
simulations. Not synthesizable.
Character literals: Single ASCII character or a string of such characters. Not synthesizable.
SIGNED and UNSIGNED: data types defined in the std_logic_arith package of the ieee
library. They have the appearance of STD_LOGIC_VECTOR, but accept arithmetic operations,
which are typical of INTEGER data types .
User-Defined Data Types
VHDL also allows the user to define his/her own data types. Two categories of user- defined data
types are shown below: integer and enumerated.
User-defined integer types:
TYPE integer IS RANGE -2147483647 TO +2147483647;
Here this is indeed the pre -defined type INTEGER.
TYPE natural IS RANGE 0 TO +2147483647;
Here this is indeed the pre -defined type natural
User-defined enumerated types:
TYPE bit IS ('0', '1');
Here this is indeed the pre -defined type BIT
Subtypes
A SUBTYPE is a TYPE with a constraint. The main reason for using a subtype rather than
specifying a new type is that, though operations between data of different types are not allowed, they
are allowed between a subtype and its corresponding base type.
12
SUBTYPE my_logic IS STD _LOGIC RANGE '0' TO 'Z';

Here Recall that STD _LOGIC=('X', '0','1','Z', 'W', 'L','H','-'). Therefore, logic=('0', '1', 'Z').
Arrays
Arrays are collections of objects of the same type. They can be one-dimensional (1D), twodimensional (2D), or one-dimensional-by-one-dimensional (1Dx1D). They can also be of higher
dimensions, but then they are generally not synthesizable.
To specify a new array type:
TYPE type name IS ARRAY (specification) OF data type;
Example: 1Dx1D array.
TYPE row IS ARRAY (7 DOWNTO 0) OF STD _LOGIC;-- 1D array
Example: 2D array.
TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD _LOGIC;
Here it is a 2D array
Port Array
In the specification of the input or output pins (PORTS) of a circuit (which is made in the
ENTITY), we might need to specify the ports as arrays of vectors.
PORT (inp: IN VECTOR_ARRAY (0 TO 3);
Signed and Unsigned Data Types
These data types are defined in the std_logic_arith package of the ieee library. Their syntax is
illustrated in the following examples.
Examples:
SIGNAL x: SIGNED (7 DOWNTO 0); SIGNAL y: UNSIGNED (0 TO 3);
13
PRACTICAL-4
To implement various basic logic gates using
VHDL.
1. AND gate using Data flow and Behavioral Style.
2. OR gate using Data flow and Behavioral Style.
3. NOT gate using Data flow and Behavioral Style.
14
AND GATE
AIM:- To write simulate VHDL code for AND gate using data flow.
PROGRAM:library IEEE;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AND1 is
b : in std_logic;
y : out std_logic);
end AND1;
architecture Behavioral of AND1 is
begin
y <= a and b;
end Behavioral;
15
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:-
===============================================================
*
Final Report
===============================================================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format
Optimization Goal
Keep Hierarchy
16
: and1.ngr
: and1
: NGC
: Speed
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Device utilization summary:
---------------------------
Selected Device : 3s50pq208-4
Number of Slices:
1 out of 768
0%
Number of 4 input LUTs:
1 out of 1536
0%
Number of bonded IOBs:
3 out of 124
2%
===============================================================TIMING REPORT
Timing Detail:
-------------All values displayed in nanoseconds (ns)
17
------------------------------------------------------------------------Timing constraint: Default path analysis

Delay:
Source:
Destination:
7.836ns (Levels of Logic = 3)

a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)
LUT2:I0->O
1 0.551 0.240 y1 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total
7.836ns (7.356ns logic, 0.480ns route)

(93.9% logic, 6.1% route)
===============================================================
CPU : 1.44 / 1.83 s | Elapsed : 1.00 / 1.00 s
-->
Total memory usage is 62956 kilobytes
WAVE FORMS:-
18
AND GATE
AIM: - To write simulate VHDL code for AND gate using behavioral.
PROGRAM:use IEEE.STD_LOGIC_ARITH.ALL;
--library UNISIM;
entity AND1 is
b : in std_logic;
y : out std_logic);
end AND1;
architecture Behavioral of AND1 is
begin
process (a,b)
begin
if (a='1' and b='1') then
y <= '1';
else
y <= '0';
end if;
end process;
end Behavioral;
19
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:-
===============================================================
*
Final Report
===============================================================
Final Results
Output Format
20
: and1.ngr
: and1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
--------------------------Selected Device : 3s50pq208-4
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
All values displayed in nanoseconds (ns)
Delay:
Source:
21

a (PAD)
Destination:
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)
LUT2:I0->O
1 0.551 0.240 _n00001 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.55 / 1.94 s | Elapsed : 2.00 / 2.00 s
-->
WAVE FORMS:-
22
OR GATE
AIM:- To write and simulate VHDL code for or gate using data flow.

--library UNISIM;
entity or1 is
b : in std_logic;
c : out std_logic);
end or1;
architecture Behavioral of or1 is
begin
c <= a or b;
end Behavioral;
23
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:===============================================================
*
Final Report
===============================================================
Final Results
Output Format
24
: or1.ngr
: or1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================

Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
25

Delay:
Source:
Destination:

a (PAD)
c (PAD)
Data Path: a to c
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 c1 (c_OBUF)
4.875
c_OBUF (c)
---------------------------------------Total

===============================================================
CPU : 1.31 / 1.70 s | Elapsed : 1.00 / 1.00 s
-->
WAVE FORMS:-
26
OR GATE
AIM: - To write and simulate VHDL code for or gate using behavioral.

--library UNISIM;
entity OR1 is
b : in std_logic;
y : out std_logic);
end OR1;
architecture Behavioral of OR1 is
begin
process (a,b)
begin
27
y <= '0';
else
y <= '1';
end if;
end process;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
28
: or1.ngr

Output Format
: or1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
---------------------------

Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
--------------
29

Delay:
Source:
Destination:
a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 y1 (y_OBUF)
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.33 / 1.72 s | Elapsed : 1.00 / 1.00 s
WAVE FORMS:-
30
NOT GATE
AIM:- To write simulate VHDL code for NOT gate using data flow.

--library UNISIM;
entity not1 is
y : out std_logic);
end not1;
architecture Behavioral of not1 is
begin
y <= not a;
end Behavioral
31
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
Output Format
: Speed
Keep Hierarchy
: NO
Design Statistics
:2
32
: not1
: NGC
Optimization Goal
# IOs
: not1.ngr
Cell Usage :
# BELS
:1
:1
LUT1
# IO Buffers
#
IBUF
OBUF
:2
:1
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
2 out of 124
1%
===============================================================
TIMING REPORT
Timing Detail:

Delay:
33
Source:
Destination:
a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
1 1.679 0.240 a_IBUF (a_IBUF)
LUT1:I0->O
1 0.479 0.240 y1 (y_OBUF)
OBUF:I->O
4.240
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.55 / 1.95 s | Elapsed : 1.00 / 2.00 s
-->
WAVE FORMS:-
34
NOT GATE
AIM: - To write simulate VHDL code for NOT gate using behavioral.

--library UNISIM;
entity NOT1 is
y : out std_logic);
end NOT1;
architecture Behavioral of NOT1 is
begin
process(a)
begin
if (a='1') then
35
y <= '0';
else
y <= '1';
end if;
end process;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
Output Format
36
: not1.ngr
: not1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:2
Cell Usage :
# BELS
:1
:1
LUT1
# IO Buffers
#
IBUF
OBUF
:2
:1
:1
===============================================================
---------------------------

Number of Slices:
1 out of 768
0%
1 out of 1536
0%
2 out of 124
1%
===============================================================
TIMING REPORT
Timing Detail:
-------------------------------------------------------------------------
37
Timing constraint: Default path analysis

Delay:
Source:
Destination:

a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)
LUT1:I0->O
1 0.551 0.240 y1 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.31 / 1.72 s | Elapsed : 2.00 / 2.00 s
-->
WAVE FORMS:-
38
PRACTICAL-5
To implement universal logic gates using

VHDL.
1. NAND gate using Data flow, Behavioral and Structural
Style.
2. NOR gate using Data flow, Behavioral and Structural
Style.
39
NAND GATE
AIM:- To write simulate VHDL code for NAND gate using data flow.

--library UNISIM;
entity NAND1 is
b : in std_logic;
y : out std_logic);
end NAND1;
architecture Behavioral of NAND1 is
begin
y <= a nand b;
end Behavioral;
40
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
Output Format
41
: nand1.ngr
: nand1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
-------------------------------------------------------------------------
42

Delay:
Source:
Destination:

a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.679 0.240 a_IBUF (a_IBUF)

1 0.479 0.240 y1 (y_OBUF)
4.240
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.33 / 1.72 s | Elapsed : 2.00 / 2.00 s
-->
WAVE FORMS:-
43
NAND GATE
AIM: - To write simulate VHDL code for NAND gate using behavioral.
--library UNISIM;
entity NAND1 is
b : in std_logic;
y : out std_logic);
end NAND1;
architecture Behavioral of NAND1 is
begin
process (a,b)
begin
y <= '0';
else
y <= '1';
end if;
44
end process;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
Output Format
Optimization Goal
Keep Hierarchy
45
: nand1.ngr
: nand1
: NGC
: Speed
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
---------------------------
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
46
Delay:
Source:
Destination:

a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 y1 (y_OBUF)
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.31 / 1.72 s | Elapsed : 1.00 / 1.00 s
-->
WAVE FORMS:-
47
NAND GATE
AIM:- To write simulate VHDL code for NAND gate using data structure.

--library UNISIM;
entity nand1 is
b : in std_logic;
c : out std_logic);
end nand1;
architecture Behavioral of nand1 is

component and1
Port ( d : in std_logic;
e : in std_logic;
f : out std_logic);
end component;
48
component inv1
Port ( g : in std_logic;
h : out std_logic);
end component;
signal x: std_logic;
begin
x1:and1 port map(a,b,x);
x2:inv1 port map(x,c);
end Behavioral;
SCHEMATIC DIAGRAM:-
SCHEMATIC DIAGRAM:-
AND2
49
INV
GATE DIAGRAM OF AND GATE:-
GATE DIAGRAM OF INV GATE:-
*
Final Report
===============================================================
Final Results
Output Format
Optimization Goal
50
: nand1.ngr
: nand1
: NGC
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
Delay:
51
Source:
Destination:
a (PAD)
c (PAD)
Data Path: a to c
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 x2_h1 (c_OBUF)
4.875
c_OBUF (c)
---------------------------------------Total

===============================================================
CPU : 1.31 / 1.70 s | Elapsed : 1.00 / 2.00 s
-->
WAVE FORMS:-
52
NOR GATE
AIM:- To write simulate VHDL code for NOR gate using data flow.

--library UNISIM;
entity NOR1 is
b : in std_logic;
y : out std_logic);
end NOR1;
architecture Behavioral of NOR1 is
begin
y <= a nor b;
end Behavioral;
53
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
Output Format
54
: nor1.ngr
: nor1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
---------------------------
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
--------------
55

Delay:
Source:
Destination:

a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
1 1.679 0.240 a_IBUF (a_IBUF)
LUT2:I0->O
1 0.479 0.240 y1 (y_OBUF)
OBUF:I->O
4.240
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.31 / 1.70 s | Elapsed : 1.00 / 1.00 s
-->
WAVE FORMS:-
56
NOR GATE
AIM: - To write simulate VHDL code for NOR gate using behavioral.

--library UNISIM;
entity NOR1 is
b : in std_logic;
y : out std_logic);
end NOR1;
begin
process (a,b)
begin
y <= '1';
57
else
y <= '0';
end if;
end process;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
58
: nor1.ngr

Output Format
: nor1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
-------------------------------------------------------------------------
59

Delay:
Source:
Destination:

a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)
LUT2:I0->O
1 0.551 0.240 _n00001 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.33 / 1.72 s | Elapsed : 1.00 / 2.00 s
-->
WAVE FORMS:-
60
NOR GATE
AIM:- To write simulate VHDL code for NOR gate using data structure.

--library UNISIM;
entity NOR1 is
b : in std_logic;
c : out std_logic);
end NOR1;
component or1
e : in std_logic;
61
f : out std_logic);
end component;
component inv1
h : out std_logic);
end component;
signal x: std_logic;
begin
x1: or1 port map(a,b,x);
x2: inv1 port map(x,c);
end Behavioral;
SCHEMATIC DIAGRAM:-
SCHEMATIC DIAGRAM:-
62
GATE DIAGRAM OF OR GATE:-
GATE DIAGRAM OF INV GATE:-
*
Final Report
===============================================================
Final Results
Output Format
: Speed
Keep Hierarchy
: NO
Design Statistics
:3
63
: nor1
: NGC
Optimization Goal
# IOs
: nor1.ngr
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
---------------------------
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
Delay:
64
Source:
Destination:
a (PAD)
c (PAD)
Data Path: a to c
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 x2_h1 (c_OBUF)
4.875
c_OBUF (c)
---------------------------------------Total

===============================================================
CPU : 1.31 / 1.83 s | Elapsed : 1.00 / 1.00 s
-->
WAVE FORMS:-
65
PRACTICAL-6
To implement XOR & XNOR gate using Data
flow, Behavioral and Structural Style.
1. XOR gate using Data flow, Behavioral and Structural
Style.
2. XNOR gate using Data flow, Behavioral and Structural
Style.
66
EX-OR GATE
AIM:- To write simulate VHDL code for EX-OR gate using data flow.

--library UNISIM;
entity xor1 is
b : in std_logic;
y : out std_logic);
end xor1;
architecture Behavioral of xor1 is

begin
y <= a xor b;
end Behavioral;
67
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
Output Format
68
: xor1.ngr
: xor1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
-------------------------------------------------------------------------
69

Delay:
Source:
Destination:

b (PAD)
y (PAD)
Data Path: b to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.679 0.240 b_IBUF (b_IBUF)

1 0.479 0.240 Mxor_y_Result1 (y_OBUF)
4.240
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.31 / 1.70 s | Elapsed : 1.00 / 2.00 s
-->
WAVE FORMS:-
70
EX-OR GATE
AIM: - To write simulate VHDL code for EX-OR gate using behavioral.
--library UNISIM;
entity XOR1 is
b : in std_logic;
y : out std_logic);
end XOR1;
architecture Behavioral of XOR1 is
begin
process(a,b)
begin
y <= '0';
else if (a='1' and b='1') then
y <= '0';
else
71
y <= '1';
end if;
end if;
end process;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
72
Final Results
Output Format
: xor1.ngr
: xor1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
73

Delay:
Source:
Destination:

a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 _n00041 (y_OBUF)
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================CPU : 1.44 / 1.83 s |

Elapsed : 2.00 / 2.00 s
-->
WAVE FORMS:-
74
EX-OR GATE
AIM:- To write simulate VHDL code for EX-OR gate using stucture.
--library UNISIM;
entity xor1 is
b : in std_logic;
c : out std_logic);
end xor1;
architecture Behavioral of xor1 is
component not1
Port ( p : in std_logic;
q : out std_logic);
end component;
component and1
y : in std_logic;
75
z : out std_logic);
end component;
component or1
h : in std_logic;
i : out std_logic);
end component;
signal s: std_logic;
signal s1: std_logic;
begin
x1:not1 port map(a,s);
x2:not1 port map(b,s1);
x3:and1 port map(s,b,s2);
x4:and1 port map(s1,a,s3);
x5:or1 port map(s2,s3,c);
end Behavioral;
SCHEMATIC DIAGRAM:-
76
GATE DIAGRAM OF NOT GATE:-
*
Final Report
===============================================================
Final Results
Output Format
77
: xor1.ngr
: xor1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
Delay:
Source:
78

a (PAD)
Destination:
c (PAD)
Data Path: a to c
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 x5_i1 (c_OBUF)
4.875
c_OBUF (c)
---------------------------------------Total

===============================================================
CPU : 1.34 / 1.84 s | Elapsed : 2.00 / 2.00 s
-->
WAVE FORMS:-
79
EX-NOR GATE
AIM:- To write simulate VHDL code for EX-NOR gate using data flow.

--library UNISIM;
entity XNOR1 is
b : in std_logic;
y : out std_logic);
end XNOR1;
architecture Behavioral of XNOR1 is
begin
y <= a xnor b;
end Behavioral;
80
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
Output Format
Optimization Goal
81
: xnor1.ngr
: xnor1
: NGC
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
82
Delay:
Source:
Destination:

b (PAD)
y (PAD)
Data Path: b to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.679 0.240 b_IBUF (b_IBUF)

1 0.479 0.240 y1 (y_OBUF)
4.240
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.33 / 1.72 s | Elapsed : 2.00 / 2.00 s
-->
WAVE FORMS:-
83
EX-NOR GATE
AIM: - To write simulate VHDL code for EX-NOR gate using behavioral.
--library UNISIM;
entity xnor1 is
b : in std_logic;
y : out std_logic);
end xnor1;
architecture Behavioral of xnor1 is
begin
process(a,b)
begin
y <= '1';
else if (a='1' and b='1') then
y <= '1';
84
else
y <= '0';
end if;
end if;
end process;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
85
: xnor1.ngr

Output Format
: xnor1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
86

Delay:
Source:
Destination:

a (PAD)
y (PAD)
Data Path: a to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 y1 (y_OBUF)
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.33 / 1.72 s | Elapsed : 1.00 / 1.00 s
-->
WAVE FORMS:-
87
EX-NOR GATE
AIM:- To write simulate VHDL code for EX-NOR gate using structure.
--library UNISIM;
entity xnor1 is
b : in std_logic;
c : out std_logic);
end xnor1;
architecture Behavioral of xnor1 is
component not1
q : out std_logic);
end component;
component and1
y : in std_logic;
z : out std_logic);
88
end component;
component or1
h : in std_logic;
i : out std_logic);
end component;
begin
x1:not1 port map(a,s);
x2:not1 port map(b,s1);
x3:and1 port map(s,b,s2);
x4:and1 port map(s1,a,s3);
x5:or1 port map(s2,s3,s4);
x6:not1 port map(s4,c);
end Behavioral;
SCHEMATIC DIAGRAM:-
89
*
Final Report
===============================================================
Final Results
Output Format
Optimization Goal
90
: xnor1.ngr
: xnor1
: NGC
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Cell Usage :
# BELS
:1
:1
LUT2
# IO Buffers
#
IBUF
OBUF
:3
:2
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
3 out of 124
2%
===============================================================
TIMING REPORT
Timing Detail:
Delay:
91
Source:
Destination:
a (PAD)
c (PAD)
Data Path: a to c
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT2:I0->O
OBUF:I->O
1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 x6_q1 (c_OBUF)
4.875
c_OBUF (c)
---------------------------------------Total

===============================================================
CPU : 1.34 / 1.73 s | Elapsed : 1.00 / 2.00 s
-->
WAVE FORMS:-
92
PRACTICAL-7
To implement different Flip-Flop using VHDL.
1. SR Flip-Flop using Behavioral Style.
2. D Flip-Flop using Behavioral Style.
3. Toggle Flip-Flop using Behavioral Style.
4. JK Flip-Flop using Behavioral Style.
93
SR FLIP FLOP
AIM: - To write simulate VHDL code for SR flip flop using behavioral
entity flipflop is
Port ( s : in std_logic;
r : in std_logic;
clk : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end flipflop;
architecture Behavioral of flipflop is
signal temp: std_logic;
begin
process(s,r,clk)
begin
if(clk='1' and clk'event) then
if(s='1'and r='0')then
temp<='1';
elsif (s='0' and r='1')then
temp<='0';
elsif(s='1'and r='1')then
temp<='Z';
else
temp<=temp;
end if;
end if;
end process;
q<=temp;
qbar<=not temp;
end Behavioral;
94
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:-
=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : srff.ngr
: srff
95
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:5
Macro Statistics :
# Registers
:2
# 1-bit register
:2
# Tristates
:1
# 1-bit tristate buffer
:1
Cell Usage :
# BELS
:5
# GND
:1
# LUT1
:1
# LUT2
:3
# FlipFlops/Latches
:2
# FDE
:1
# FDSE
:1
# Clock Buffers
:1
# BUFGP
:1
# IO Buffers
:4
# IBUF
:2
# IOBUF
:1
# OBUF
:1
=========================================================================
Number of Slices:
3 out of 3584 0%
Number of Slice Flip Flops:
2 out of 7168 0%
4 out of 7168 0%
4 out of 141 2%
Number of GCLKs:
1 out of 8 12%
=========================================================================
TIMING REPORT
Timing Detail:
------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:
Source:
r (PAD)
96
Destination:
Mtridata_temp (FF)
Destination Clock: clk rising
Data Path: r to Mtridata_temp
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
4 1.930 0.629 r_IBUF (r_IBUF)
LUT2:I1->O
1 0.551 0.240 _n00001 (_n0000)
FDSE:S
1.026
Mtridata_temp
---------------------------------------Total
(80.1% logic, 19.9% route)
------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:
Source:
Mtrien_temp (FF)
Destination:
q (PAD)
Source Clock: clk rising
Data Path: Mtrien_temp to q
Gate Net
---------------------------------------- -----------FDE:C->Q
1 0.720 0.240 Mtrien_temp (Mtrien_temp)
IOBUF:T->IO
5.118
q_IOBUF (q)
---------------------------------------Total
=========================================================================
CPU : 2.02 / 2.75 s | Elapsed : 2.00 / 2.00 s
-->
WAVEFORM :-
97
D FLIP FLOP
AIM: - To write simulate VHDL code for D flip flop using behavioral
--library UNISIM;
entity DFF is
clk : in std_logic;
q: out std_logic;
qbar : out std_logic);
end DFF;
architecture Behavioral of DFF is
begin
process(d,clk)
begin
if(clk='1'and clk'event) then
q<=d;
qbar <=not d;
end if;
end process;
end Behavioral;
98
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:-
=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : dff.ngr
: dff
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
99
# IOs
Macro Statistics :
# Registers
# 1-bit register
:4
:2
:2
Cell Usage :
# BELS
:1
# VCC
:1
# FlipFlops/Latches
:2
# FD
:1
# FDR
:1
# Clock Buffers
:1
# BUFGP
:1
# IO Buffers
:3
# IBUF
:1
# OBUF
:2
=========================================================================
Number of Slices:
Number of GCLKs:
2 out of 3584 0%
2 out of 7168 0%
3 out of 141 2%
1 out of 8 12%
=========================================================================
TIMING REPORT
Timing Detail:
Offset:
Source:
d (PAD)
Destination:
qbar (FF)
Data Path: d to qbar
100
Gate Net
---------------------------------------- -----------IBUF:I->O
2 1.930 0.465 d_IBUF (d_IBUF)
FDR:R
1.026
qbar
---------------------------------------Total
(86.4% logic, 13.6% route)
Offset:
Source:
qbar (FF)
Destination:
qbar (PAD)
Data Path: qbar to qbar
Gate Net
---------------------------------------- -----------FDR:C->Q
1 0.720 0.240 qbar (qbar_OBUF)
OBUF:I->O
4.875
qbar_OBUF (qbar)
---------------------------------------Total
=========================================================================
CPU : 1.39 / 1.78 s | Elapsed : 2.00 / 2.00 s
-->
WAVEFORM :-
101
TOGGLE FLIP FLOP
AIM: - To write simulate VHDL code for Toggle flip flop using behavioral
--library UNISIM;
entity TFF is
Port ( t: in std_logic;
clk : in std_logic;
q: inout std_logic;
end TFF;
architecture Behavioral of TFF is
signal temp: std_logic:='0' ;
begin
process(t,clk)
begin
if(clk='1'and clk'event) then
if(t='0')then
temp<=temp;
elsif (t='1') then
temp<= not temp;
end if;
end if;
end process;
q<=temp;
qbar<=not temp;
end Behavioral;
102
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:-
=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : tff.ngr
: tff
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:4
Macro Statistics :
# Registers
:1
# 1-bit register
:1
Cell Usage :
# BELS
103
:1
# LUT1_L
:1
# FlipFlops/Latches
:1
# FDE
:1
# Clock Buffers
:1
# BUFGP
:1
# IO Buffers
:3
# IBUF
:1
# OBUF
:2
=========================================================================
Number of Slices:
1 out of 3584 0%
1 out of 7168 0%
1 out of 7168 0%
3 out of 141 2%
Number of GCLKs:
1 out of 8 12%
=========================================================================
TIMING REPORT
Timing Detail:
------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk'
Delay:
Source:
temp (FF)
Destination:
temp (FF)
Data Path: temp to temp
Gate Net
---------------------------------------- -----------FDE:C->Q
2 0.720 0.465 temp (temp)
LUT1_L:I0->LO
2 0.551 0.000 qbar1 (qbar_OBUF)
FDE:D
0.203
temp
---------------------------------------Total
(76.0% logic, 24.0% route)
Offset:
Source:
t (PAD)
104
Destination:
temp (FF)
Data Path: t to temp
Gate Net
---------------------------------------- -----------IBUF:I->O
1 1.930 0.240 t_IBUF (t_IBUF)
FDE:CE
0.602
temp
---------------------------------------Total
Offset:
Source:
temp (FF)
Destination:
qbar (PAD)
Data Path: temp to qbar
Gate Net
---------------------------------------- -----------FDE:C->Q
2 0.720 0.465 temp (temp)
LUT1_L:I0->LO
2 0.551 0.100 qbar1 (qbar_OBUF)
OBUF:I->O
4.875
qbar_OBUF (qbar)
---------------------------------------Total
=========================================================================
CPU : 1.42 / 1.83 s | Elapsed : 2.00 / 2.00 s
-->
WAVEFORM :-
105
JK FLIP FLOP
AIM: - To write simulate VHDL code for JK flip flop using behavioral
--library UNISIM;
entity JKFF is
Port ( j : in std_logic;
k : in std_logic;
clk : in std_logic;
q : out std_logic;
end JKFF;
architecture Behavioral of JKFF is
signal temp: std_logic;

begin
process(j,k,clk)
begin
if(clk='1' and clk'event) then
if(j='1'and k='0')then
temp<='1';
elsif (j='0' and k='1')then
temp<='0';
elsif(j='1'and k='1')then
temp<=not temp;
else
temp<=temp;
end if;
106
end if;
end process;
q<=temp;
qbar<=not temp;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM :-
107
SYNTHESIS REPORT:-
=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : jkff.ngr
: jkff
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
Macro Statistics :
# Registers
# 1-bit register
:5
:1
:1
Cell Usage :
# BELS
:3
# LUT1
:1
# LUT2
:1
# LUT3_L
:1
# FlipFlops/Latches
:1
# FDSE
:1
# Clock Buffers
:1
# BUFGP
:1
# IO Buffers
:4
# IBUF
:2
# OBUF
:2
=========================================================================
Number of Slices:
108
2 out of 3584 0%
1 out of 7168 0%
3 out of 7168 0%
4 out of 141 2%
Number of GCLKs:
1 out of 8 12%
=========================================================================
TIMING REPORT
Timing Detail:
------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk'
Delay:
Source:
temp (FF)
Destination:
temp (FF)
Data Path: temp to temp
Gate Net
---------------------------------------- -----------FDSE:C->Q
3 0.720 0.577 temp (temp)
LUT3_L:I0->LO
1 0.551 0.000 _n00021 (_n0002)
FDSE:D
0.203
temp
---------------------------------------Total
(71.9% logic, 28.1% route)
Offset:
Source:
k (PAD)
Destination:
temp (FF)
Data Path: k to temp
Gate Net
---------------------------------------- -----------IBUF:I->O
3 1.930 0.577 k_IBUF (k_IBUF)
LUT2:I1->O
1 0.551 0.240 _n00001 (_n0000)
FDSE:S
1.026
temp
---------------------------------------Total
(81.1% logic, 18.9% route)
109

Offset:
Source:
temp (FF)
Destination:
qbar (PAD)
Data Path: temp to qbar
Gate Net
---------------------------------------- -----------FDSE:C->Q
3 0.720 0.577 temp (temp)
LUT1:I0->O
1 0.551 0.240 qbar1 (qbar_OBUF)
OBUF:I->O
4.875
qbar_OBUF (qbar)
---------------------------------------Total
(88.3% logic, 11.7% route)
=========================================================================
CPU : 1.41 / 1.81 s | Elapsed : 2.00 / 2.00 s
-->
WAVEFORM :-
110
PRACTICAL-8
To implement Multiplexer using VHDL.
1.
2 x 1 Multiplexer using Data flow, Behavioral and
Structural Style.
2. 4 x 1 Multiplexer using Data flow, Behavioral and
Structural Style.
111
MULTIPLEXER(2 to 1)
AIM:- To write simulate VHDL code for MULTIPLEXER( 2 to 1 ) gate using data
flow.
--library UNISIM;
entity mux1 is
b : in std_logic;
s : in std_logic;
y : out std_logic);
end mux1;
architecture Dataflow of mux1 is
begin
y<= ((not s) and a) or ( s and b);
end Behavioral;
112
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:-
===============================================================
*
Final Report
===============================================================
Final Results
Output Format
113
: mux1.ngr
: mux1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:4
Cell Usage :
# BELS
:1
:1
LUT3
# IO Buffers
#
IBUF
OBUF
:4
:3
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
4 out of 124
3%
===============================================================
TIMING REPORT
Timing Detail:

Delay:
Source:
Destination:
114

s (PAD)
y (PAD)
Data Path: s to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
1 1.930 0.240 s_IBUF (s_IBUF)
LUT3:I0->O
1 0.551 0.240 y1 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total

CPU : 1.34 / 1.73 s | Elapsed : 1.00 / 2.00 s

WAVE FORMS:-
115
MULTIPLEXER(2 to 1)
AIM:- To write simulate VHDL code for MULTIPLEXER( 2 to 1 ) gate using

behavioural.
--library UNISIM;
entity mux21 is
b : in std_logic;
s : in std_logic;
y : out std_logic);
end mux21;
architecture Behavioral of mux21 is
begin
process(a,b,s)
begin
case s is
when '0' => y<=a;
when others => y<=b;
116
end case;
end process;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:-
===============================================================
*
Final Report
===============================================================
Final Results
117
: mux21.ngr
: mux21
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:4
Macro Statistics :
# Multiplexers
#
:1
2-to-1 multiplexer
:1
Cell Usage :
# BELS
:1
:1
LUT3
# IO Buffers
#
IBUF
OBUF
:4
:3
:1
===============================================================
Number of Slices:
1 out of 768
0%
1 out of 1536
0%
4 out of 124
3%
===============================================================
TIMING REPORT
Delay:
118
Source:
Destination:
s (PAD)
y (PAD)
Data Path: s to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
1 1.930 0.240 s_IBUF (s_IBUF)
LUT3:I0->O
1 0.551 0.240 Mmux_y_Result1 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.36 / 1.75 s | Elapsed : 1.00 / 2.00 s
WAVE FORMS:-
119
MULTIPLEXER(2 to1)

stucture.

--library UNISIM;
entity mux1 is
b : in std_logic;
c : in std_logic;
y : out std_logic);
end mux1;
architecture structure of mux1 is
component not1
120
q : out std_logic);
end component;
component and1
e : in std_logic;
f : out std_logic);
end component;
component or1
h : in std_logic;
i : out std_logic);
end component;
begin
x1: not1 port map(c,s);
x2: and1 port map(a,c,s1);
x3: and1 port map(s,b,s2);
x4: or1 port map(s1,s2,y);
end Behavioral;
121
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
Final Results
122

Output Format
: mux1.ngr
: mux1
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:4
Cell Usage :
# IO Buffers
#
IBUF
OBUF
:4
:3
:1
# Others
:4
and1
:2
not1
:1
or1
:1
===============================================================
4 out of 124
3%
================================================================================
TIMING REPORT
Timing Detail:
123

Delay:
Source:
Destination:

x4:i (PAD)
y (PAD)
Data Path: x4:i to y

Gate
Cell:in->out
Net
---------------------------------------- -----------or1:i
OBUF:I->O
1 0.000 0.240 x4 (y_OBUF)

4.875
y_OBUF (y)
---------------------------------------Total

CPU : 1.58 / 1.97 s | Elapsed : 2.00 / 2.00 s

WAVE FORMS:-
124
MULTIPLEXER(4 to 1)
AIM:- To write simulate VHDL code for MULTIPLEXER( 4 to 1 ) gate using data
flow.
--library UNISIM;
entity mux2 is
b : in std_logic;
c : in std_logic;
d : in std_logic;
s0 : in std_logic;
s1 : in std_logic;
y : out std_logic);
end mux2;
architecture dataflow of mux2 is
begin
y <= ((not s0)and(not s1)and a) or ( s0 and(not s1)and b) or ((not s0) and s1 and c) or
and d);
end Behavioral;
125
(s0 and s1
SCHEMATIC DIAGRAM:-
126
GATE DIAGRAM:-
SYNTHESIS REPORT:-
===============================================================
*
Final Report
===============================================================
Final Results
Output Format
: mux2.ngr
: mux2
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:7
Cell Usage :
# BELS
:3
LUT3
:2
MUXF5
:1
# IO Buffers
:7
IBUF
OBUF
:6
:1
===============================================================
Number of Slices:
1 out of 768
0%
2 out of 1536
0%
7 out of 124
5%
127
===============================================================
TIMING REPORT
Timing Detail:
Delay:
Source:

s0 (PAD)
Destination:
y (PAD)
Data Path: s0 to y
Gate
Cell:in->out
IBUF:I->O
Net

2 1.930 0.465 s0_IBUF (s0_IBUF)
LUT3:I1->O
1 0.551 0.000 y28_F (N280)
MUXF5:I0->O
1 0.360 0.240 y28 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total

CPU : 1.41 / 1.80 s | Elapsed : 2.00 / 2.00 s

WAVE FORMS:-
128
MULTIPLEXER(4 to 1)

behavioural.
--library UNISIM;
entity mux41 is
Port ( a : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux41;
begin
process(a,s)
begin
case s is
when "00" => y <= a(0);
when "01" => y <= a(1);
when "10" => y <= a(2);
129
when others => y <= a(3);

end case;
end process;
end Behavioral;
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:-
===============================================================
*
Final Report
===============================================================
Final Results
130

Output Format
: mux41.ngr
: mux41
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:7
Macro Statistics :
# Multiplexers
#
:1
1-bit 4-to-1 multiplexer : 1
Cell Usage :
# BELS
:3
LUT3
:2
MUXF5
:1
# IO Buffers
:7
IBUF
:6
OBUF
:1
===============================================================Device utilization
summary:
Number of Slices:
1 out of 768
0%
2 out of 1536
0%
7 out of 124
5%
===============================================================
TIMING REPORT
131

Delay:
Source:

s<0> (PAD)
Destination:
y (PAD)
Data Path: s<0> to y

Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
2 1.930 0.465 s_0_IBUF (s_0_IBUF)
LUT3:I0->O
1 0.551 0.000 Mmux_y_inst_lut3_01 (Mmux_y__net0)
MUXF5:I0->O
1 0.360 0.240 Mmux_y_inst_mux_f5_0 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.38 / 1.76 s | Elapsed : 1.00 / 2.00 s
WAVE FORMS:-
132
MULTIPLEXER(4 to 1)

stucture.
--library UNISIM;
entity mux2 is
b : in std_logic;
c : in std_logic;
d : in std_logic;
k : in std_logic;
m : in std_logic;
y : out std_logic);
end mux2;
component not1
q : out std_logic);
end component;
component and1 is
Port ( u : in std_logic;
133
is
v : in std_logic;
x : in std_logic;
w : out std_logic);
end component;
component or1 is
h : in std_logic;
l : in std_logic;
g : in std_logic;
i : out std_logic);
end component;
begin
x1: not1 port map(k,s);
x2: not1 port map(m,s1);
x3: not1 port map(k,s2);
x4: not1 port map(m,s3);
x5: and1 port map(s,s1,a,s4);
134
x6: and1 port map(s2,m,b,s5);

x7: and1 port map(k,s3,c,s6);
x8: and1 port map(k,m,d,s7);
x9: or1 port map(s4,s5,s6,s7,y);
end Behavioral;
SCHEMATIC DIAGRAM:-
135
*
Final Report
===============================================================
Final Results
Output Format
: Speed
Keep Hierarchy
: NO
Design Statistics
:7
Cell Usage :
# BELS
:3
LUT3
:2
MUXF5
136
: mux2
: NGC
Optimization Goal
# IOs
: mux2.ngr
:1
# IO Buffers
#
IBUF
OBUF
:7
:6
:1
===============================================================
Number of Slices:
1 out of 768
0%
2 out of 1536
0%
7 out of 124
5%
===============================================================
Timing Detail:

Delay:
Source:
Destination:
137

k (PAD)
y (PAD)
Data Path: k to y
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT3:I1->O
2 1.930 0.465 k_IBUF (k_IBUF)

1 0.551 0.000 x9_i28_F (N358)
MUXF5:I0->O
1 0.360 0.240 x9_i28 (y_OBUF)
OBUF:I->O
4.875
y_OBUF (y)
---------------------------------------Total

===============================================================
CPU : 1.34 / 1.73 s | Elapsed : 2.00 / 2.00 s
WAVE FORMS:-
138
PRACTICAL-9
To implement decoder/Encoder using VHDL.
1 .To implement 3 X 8 decoder using Behavioral Style.
2 .To implement 8 X 3 encoder using Behavioral Style.
139
DECODER (3 to 8)
AIM:- To write simulate VHDL code for DECODER(3 to 8) gate using

behavioral.

--library UNISIM;
entity decoder38 is
Port ( x : in std_logic_vector(2 downto 0);
d : out std_logic_vector(7 downto 0));
end decoder38;
architecture Behavioral of decoder38 is
begin
process(x)
begin
case x is
when "000" =>
d(0)<='1';
d(7 downto 1)<="0000000";
140
when "001" =>
d(1)<='1';
d(7 downto 2)<="000000";
d(0)<='0';
when "010" =>
d(2)<='1';
d(7 downto 3)<="00000";
d(1 downto 0)<="00";
when "011" =>
d(3)<='1';
d(7 downto 4)<="0000";
d(2 downto 0)<="000";
when "100" =>
d(4)<='1';
d(7 downto 5)<="000";
d(3 downto 0)<="0000";
when "101" =>
d(5)<='1';
d(7 downto 6)<="00";
d(4 downto 0)<="00000";
when "110" =>
d(6)<='1';
d(7)<='0';
d(5 downto 0)<="000000";
when others => d(7)<='1';

d(6 downto 0)<="0000000";
end case;
end process;
end Behavioral;
141
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
142
*
Final Report
===============================================================
Final Results
143

Output Format
: decoder38.ngr
: decoder38
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 11
Cell Usage :
# BELS
:8
:8
LUT3
# IO Buffers
#
IBUF
OBUF
: 11
:3
:8
===============================================================
Number of Slices:
5 out of 768
0%
8 out of 1536
11 out of 124
0%
8%
==============================================================
TIMING REPORT
144

Delay:
Source:
Destination:

x<2> (PAD)
d<7> (PAD)
Data Path: x<2> to d<7>

Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT3:I0->O
OBUF:I->O
8 1.930 0.747 x_2_IBUF (x_2_IBUF)

1 0.551 0.240 _n00071 (d_7_OBUF)
4.875
d_7_OBUF (d<7>)
---------------------------------------Total

(88.2% logic, 11.8% route)
=========================================================================
CPU : 1.34 / 1.73 s | Elapsed : 1.00 / 2.00 s
WAVE FORMS:-
145
ENCODER (8 to 3)
AIM:- To write simulate VHDL code for ENCODER(8 to 3) gate using

behavioral.

-- library UNISIM;
-- use UNISIM.VComponents.all;
entity encoder83 is
Port ( d : in std_logic_vector(7 downto 0);
x : out std_logic_vector(2 downto 0));
end encoder83;
architecture Behavioral of encoder83 is
begin
process(d)
begin
case d is
146
when "00000001"
=> x(2 downto 0)<="000";
when "00000010"
=> x(2 downto 1)<="00";

x(0)<='1';
when "00000100"
=>
x(2)<='0';
x(1)<='1';
x(0)<='0';
when "00001000"
=>
x(2)<='0';
x(1 downto 0)<="11";
when "00010000"
=>
x(2)<='1';
x(1 downto 0)<="00";

when "00100000"
=>
x(2)<='1';
x(1)<='0';
x(0)<='1';
when "01000000"
=>
x(2 downto 1)<="11";

x(0)<='0';
when others
end case;
end process;
end Behavioral;
147
=>
x(2 downto 0)<="111";
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
*
Final Report
===============================================================
148
Final Results
Output Format
: encoder83.ngr
: encoder83
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 11
Cell Usage :
# BELS
: 12
LUT3
:3
LUT4
:9
# IO Buffers
#
IBUF
OBUF
: 11
:8
:3

Number of Slices:
7 out of 768
0%
12 out of 1536
0%
11 out of 124
8%
===============================================================
Timing Detail:
Delay:
149
Source:
Destination:
d<0> (PAD)
x<2> (PAD)
Data Path: d<0> to x<2>

Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
6 1.930 0.688 d_0_IBUF (d_0_IBUF)
LUT4:I3->O
1 0.551 0.240 _n003045_SW0 (N1165)
LUT3:I2->O
1 0.551 0.240 _n003045 (CHOICE152)
LUT4:I3->O
1 0.551 0.240 _n003057 (x_0_OBUF)
OBUF:I->O
4.875
x_0_OBUF (x<0>)
---------------------------------------Total

(85.7% logic, 14.3% route)
=========================================================================
CPU : 1.41 / 1.81 s | Elapsed : 1.00 / 1.00 s
WAVE FORMS:-
150
PRACTICAL-10
To implement 4 bit adder/subtractor using
VHDL.
1.To implement 1-bit adder using Data flow Style.
2 . To implement 4-bit adder using Structural Style.
151
1-BIT ADDER
AIM: - To implement 1-bit adder using data flow style

--library UNISIM;
entity halfadder is
b : in std_logic;
s : out std_logic;
c : out std_logic);
end halfadder;
architecture Dataflow of halfadder is
begin
s <= ((a and (not b))or ((not a) and b));
c <= a and b;
end Dataflow;
152
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
SYNTHESIS REPORT:=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : halfadder.ngr
: halfadder
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
Cell Usage :
# BELS
# LUT2
153
:4
:2
:2
# IO Buffers
:4
# IBUF
:2
# OBUF
:2
=========================================================================
Number of Slices:
1 out of 3584 0%
2 out of 7168 0%
4 out of 141 2%
=========================================================================
TIMING REPORT
Timing Detail:
Delay:
Source:
a (PAD)
Destination:
c (PAD)
Data Path: a to c
Gate Net
---------------------------------------- -----------IBUF:I->O
2 1.930 0.465 a_IBUF (a_IBUF)
LUT2:I0->O
1 0.551 0.240 c1 (c_OBUF)
OBUF:I->O
4.875
c_OBUF (c)
---------------------------------------Total
=========================================================================
CPU : 1.39 / 1.78 s | Elapsed : 2.00 / 2.00 s
-->
WAVEFORM :-
154
4-BIT ADDER
AIM: - To implement 4-bit using structural style.
--library UNISIM;
entity fourbitadder is
Port ( x : in std_logic_vector(3 downto 0);
y : in std_logic_vector(3 downto 0);
incarry : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end fourbitadder;
architecture Behavioral of fourbitadder is
component onebitadder
port (a,b,c :in std_logic;
sum, carry: out std_logic);
end component;
signal intcarry : std_logic_vector(2 downto 0):="000";
begin
out1: onebitadder port map(x(0),y(0),incarry,s(0),intcarry(0));
out2: onebitadder port map(x(1),y(1),intcarry(0),s(1),intcarry(1));
out3: onebitadder port map(x(2),y(2),intcarry(1),s(2),intcarry(2));
out4: onebitadder port map(x(3),y(3),intcarry(2),s(3),cout);
end Behavioral;
155
One bit adder: as a component

library IEEE;
--library UNISIM;
entity onebitadder is
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end onebitadder;
architecture Dataflow of onebitadder is
begin
sum<= a xor (b xor c);
carry<= (a and b)or (b and c) or (a and c);
end Dataflow;
SCHEMATIC DIAGRAM:-
156
GATE DIAGRAM:-
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : fourbitadder.ngr
: fourbitadder
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 14
Macro Statistics :
# Xors
:4
# 1-bit xor3
:4
Cell Usage :
# BELS
:8
# LUT3
:8
# IO Buffers
: 14
# IBUF
:9
# OBUF
:5
=========================================================================
157

Number of Slices:
5 out of 3584 0%
8 out of 7168 0%
14 out of 141 9%
=========================================================================
TIMING REPORT
Timing Detail:
Delay:
Source:
x<0> (PAD)
Destination:
cout (PAD)
Data Path: x<0> to cout
Gate Net
---------------------------------------- -----------IBUF:I->O
2 1.930 0.465 x_0_IBUF (x_0_IBUF)
LUT3:I0->O
2 0.551 0.465 out1_carry1 (intcarry<0>)
LUT3:I2->O
LUT3:I2->O
LUT3:I1->O
1 0.551 0.240 out4_Mxor_sum_Xo<1>1 (s_3_OBUF)
OBUF:I->O
4.875
s_3_OBUF (s<3>)
---------------------------------------Total
(81.1% logic, 18.9% route)
=========================================================================
CPU : 1.45 / 1.84 s | Elapsed : 2.00 / 2.00 s
-->
WAVEFORM :-
158
PR-11.
4-BIT ADDER FOR CARRY LOOK
AIM: - To implement 4-bit aadr for carry look ahead concept.
entity lookadder is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
s : out std_logic_vector(3 downto 0));
end lookadder;
architecture Behavioral of lookadder is
signal g : std_logic_vector(3 downto 0);
signal p : std_logic_vector(3 downto 0);
signal inc : std_logic_vector(3 downto 0);
begin
inc(0)<=c;
ADDER: for i in 0 to 3 generate
p(i)<= a(i) xor b(i);
g(i)<= a(i) and b(i);
s(i)<= p(i) xor inc(i);
end Generate;
inc(1)<= g(0) or (inc(0) and p(0));
inc(2)<= g(1) or (p(1) and g(0)) or (p(1) and (p(0) and inc(0)));
inc(3)<= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1) and
p(0) and inc(0));
end Behavioral;
159
SCHEMATIC DIAGRAM:-
GATE DIAGRAM:-
160
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : lookadder.ngr
: lookadder
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 13
Cell Usage :
# BELS
:8
# LUT2
:2
# LUT3
:4
# LUT4
:2
# IO Buffers
: 13
# IBUF
:9
# OBUF
:4
=========================================================================
Number of Slices:
5 out of 3584 0%
8 out of 7168 0%
13 out of 141 9%
=========================================================================
TIMING REPORT
Timing Detail:
-------------------------------------------------------------------------
161

Delay:
Source:
a<0> (PAD)
Destination:
s<3> (PAD)
Data Path: a<0> to s<3>
Gate Net
---------------------------------------- -----------IBUF:I->O
3 1.930 0.577 a_0_IBUF (a_0_IBUF)
LUT3:I0->O
1 0.551 0.240 _n0034_SW1 (N892)
LUT3:I2->O
2 0.551 0.465 _n0034 (inc<2>)
LUT3:I0->O
1 0.551 0.240 Mxor_s<2>_Result1 (s_2_OBUF)
OBUF:I->O
4.875
s_2_OBUF (s<2>)
---------------------------------------Total
(84.7% logic, 15.3% route)
=========================================================================
CPU : 1.47 / 1.86 s | Elapsed : 1.00 / 2.00 s
-->
WAVEFORM :-
162

Practical - 1. VHDL Introduction: Design Flow

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Practical - 1. VHDL Introduction: Design Flow

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PRACTICAL -1.

Figure 1: Design Flow

VHDL Code Structure

Figure 2 : Fundaments sections of a basic VHDL code

Figure 3: Fundamental Parts of a Library

PRACTICAL -2. VHDL ENTITIES AND CODING STYLES

VHDL coding Styles

1. Data flow : As a set of concurrent assignment statements

The GENERATE statement;

PRACTICAL-3. SIGNALS AND DATA TYPES

CONSTANT name : type := value;

VARIABLE control: std_logic := '0';

Comparison between SIGNAL and VARIABLE.

Represents circuit interconnects (wires)

Represents local information

Update is not immediate in sequential

Updated immediately (new value

Only in sequential code, that is,

BIT (and BIT_VECTOR): 2-level logic (0, 1).

STD_LOGIC (and STD_LOGIC_VECTOR): 8-valued logic system introduced in the IEEE

Forcing Unknown (synthesizable unknown)

TABLE 1 Resolved logic system (STD_LOGIC).

STD_ULOGIC (STD_ULOGIC_VECTOR): 9-level logic system introduced in the IEEE

SUBTYPE my_logic IS STD _LOGIC RANGE '0' TO 'Z';

architecture Behavioral of AND1 is

Selected Device : 3s50pq208-4

Number of 4 input LUTs:

Number of bonded IOBs:

------------------------------------------------------------------------Timing constraint: Default path analysis

7.836ns (Levels of Logic = 3)

fanout Delay Delay Logical Name (Net Name)

1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 y1 (y_OBUF)

7.836ns (7.356ns logic, 0.480ns route)

Number of 4 input LUTs:

Number of bonded IOBs:

7.836ns (Levels of Logic = 3)

fanout Delay Delay Logical Name (Net Name)

1 1.930 0.240 a_IBUF (a_IBUF)

1 0.551 0.240 _n00001 (y_OBUF)

7.836ns (7.356ns logic, 0.480ns route)

-- Uncomment the following lines to use the declarations that are

architecture Behavioral of or1 is

Device utilization summary:

Number of 4 input LUTs:

Number of bonded IOBs:

------------------------------------------------------------------------Timing constraint: Default path analysis

7.836ns (Levels of Logic = 3)

fanout Delay Delay Logical Name (Net Name)

1 1.930 0.240 a_IBUF (a_IBUF)

7.836ns (7.356ns logic, 0.480ns route)

-- Uncomment the following lines to use the declarations that are

architecture Behavioral of OR1 is

Top Level Output File Name

Selected Device : 3s50pq208-4

Number of 4 input LUTs:

Number of bonded IOBs:

All values displayed in nanoseconds (ns)

7.836ns (Levels of Logic = 3)

fanout Delay Delay Logical Name (Net Name)

1 1.930 0.240 a_IBUF (a_IBUF)

7.836ns (7.356ns logic, 0.480ns route)

-- Uncomment the following lines to use the declarations that are