8051

Chapter 7 : Intel 8051 Microcontroller

7.1 7.2 7.3 7.4 7.5 7.6 Introduction to microcontrollers Microprocessors Vs. Microcontrollers Introduction to 8051 Microcontroller Features of the standard 8051 Block diagram of 8051 Memory Organization 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7 Program Memory External Data Memory Internal Data Memory On-Chip Memory. Bit Memory Special Function Register (SFR) Memory
8051 SFRs 7.7.1 SFR Types 7.7.1.1 7.7.1. 2 7.7.1.3 7.7.1. 4 7.7.1.5 7.7.1.6 7.7.1.7 7.7.1.8 7.7.1.9 SFR Descriptions P0 (Port 0, Address 80h, Bit-Addressable) SP (Stack Pointer, Address 81h): DPL/DPH (Data Pointer Low/High, Addresses 82h/83h) PCON (Power Control, Addresses 87h): TCON (Timer Control, Addresses 88h, Bit-Addressable) TMOD (Timer Mode, Addresses 89h): TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Bh) TL1/TH1 (Timer 1 Low/High, Addresses 8Ch/8Dh)
7.7.1.10 P1 (Port 1, Address 90h, Bit-Addressable) 7.7.1.11 SCON (Serial Control, Addresses 98h, Bit-Addressable) 7.7.1.12 SBUF (Serial Control, Addresses 99h): 7.7.1.13 P2 (Port 2, Address A0h, Bit-Addressable) 7.7.1.14 7.7.1.15 7.7.1.16 IE (Interrupt Enable, Addresses A8h) P3 (Port 3, Address B0h, Bit-Addressable) IP(Interrupt Priority, Addresses B8h, Bit- Addressable)
Chapter 7 : Intel 8051 Microcontroller 7.7.1.17 PSW (Program Status Word, Addresses D0h, Bit-Addressable) 7.7.1.18 7.7.1.19 7.8 ACC (Accumulator, Addresses E0h, Bit-Addressable): B (B Register, Addresses F0h, Bit-Addressable):
8051 Basic Registers 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.8.6 Accumulator "R" registers "B" Register Data Pointer (DPTR) Program Counter (PC) Stack Pointer (SP)
7.9
8051 Addressing Modes 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 Immediate Addressing Direct Addressing Indirect Addressing External Direct External Indirect
7.10 8051 Timers 7.10 .1 Timer SFRs 7.10 .1.1 7.10 .1.2 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 TMOD SFR TCON SFR
Initializing a Timer Reading the Timer Reading the value of a Timer Detecting Timer Overflow Using Timers As Event Counters
7.11 Interrupt Service Routine Unit 7.11.1 External Interrupts 7.11.2 Timer 0 and Timer 1 Interrupts 7.11.3 Serial Port Interrupt 7.11.4 Priority Level Structure 7.11.5 Interrupt Vectors
Chapter 7 : Intel 8051 Microcontroller 7.11.6 Interrupt Detect 7.12 Power Management Unit 7.12.1 Idle Mode 7.12.2 Stop Mode 7.12.3 Power Management Implementation 7.13 Serial Interface 7.13.1 Serial Port 0 7.13.2 Multiprocessor Communication 7.13.3 Serial Port Control Register (SCON) 7.13.4 Generating Variable Baud Rate in Modes 1 and 3 7.13.5 Generating Variable Baud Rate in Modes 1 and 3 7.14 8051 Microcontroller Instruction Set
Chapter 7 :
Intel 8051 Microcontroller
7.1 Introduction to microcontrollers The powerful component is actually very simple in its essence. It was built using the tested solutions and ingredients by the following recipe: 1. Processor was removed from the simplest of computers to be used as the "brain" for the upcoming system. 2. Depending on the manufacturers' taste, some memory was added, a few A/D converters, timers, I/O communication lines, etc. 3. It was all placed in a standard casing. 4. Simple software that everybody could learn was developed for controlling the thing. There are three decisive facts responsible for such a success of microcontrollers: 1. Their powerful, cleverly chosen electronics is able to control a variety of processes and devices (industrial automatics, voltage, temperature, engines, etc) independently or by means of I/O instruments such as switches, buttons, sensors, LCD screens, relays 2. Their low cost makes them suitable for installing in places which attracted no such interest in the past. This is the fact accountable for today's market being swamped with cheap automatons and "intelligent" toys. 3. Writing and loading a program into microcontroller requires practically no previous schooling. All that is required is: any PC (software is very friendly and intuitive) and one simple device (programmer) for loading a written program into microcontroller. 7.2 Microprocessors Vs. Microcontrollers Microprocessor CPU is stand-alone, RAM, ROM, I/O, timer are separate Designer can decide on the amount of ROM, RAM and I/O ports. Expansive Their instructions operate on nibbles, bytes, words, or even double words.
Chapter 7 : Intel 8051 Microcontroller Addressing modes provide access to large arrays of data using pointers and offsets. Versatility General-purpose
Microcontroller CPU, RAM, ROM, I/O and timer are all on a single chip Fix amount of on-chip ROM, RAM, I/O ports They have instructions to set and clear individual bits and perform bit operations. They have instructions for input/output operations, event timing, enabling and setting priority levels for interrupts caused by external stimuli For applications in which cost, power and space are critical Single-purpose
CPU I/O Port
RAM ROM
A single chip
Serial COM Port
Timer
7.3 Introduction to 8051 Microcontroller The 8051 is one of the most popular microcontrollers in use today. Many derivative microcontrollers have since been developed that are based on and compatible with the 8051. Thus, the ability to program an 8051 is an important skill for anyone who plans to develop products that will take advantage of microcontrollers. 7.4 Features of the standard 8051 4K bytes internal ROM (program) 128 bytes internal RAM (data) Four 8-bit I/O ports Two 16-bit timers
Chapter 7 : Intel 8051 Microcontroller Serial interface 64K external code memory space 64K external data memory space 210 bit-addressable locations 7.5 Block diagram of 8051
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter
On-chip RAM
Timer 1 Timer 0
Counter Inputs
CPU Serial Port
OSC
Bus Control
4 I/O Ports
P0 P1 P2 P3
TxD RxD
Address/Data
Figure 1 : Block diagram of 8051
Chapter 7 : Intel 8051 Microcontroller Architecture of 8051 (* Theory to be include)
Figure 2 : Architecture of 8051
Chapter 7 : Intel 8051 Microcontroller Architecture of 8051 Accumulator (ACC) : The accumulator register act as an operand register, in case of some instructions .This may either be implicit or specified in the instruction. The Acc register has been allotted and address in the on chip special function register bank. B Register : The register in used to store one of the operands for multiply and divide instructions . In other instructions, it may just be used as a scratch pad. This register is considered as a special faction register. Program status word (PSW) This set of flags contains the status information and is considered as one on of the special registers. Stack pointer (Sp) : This 8 bit wide register is incremented before the data is stored on to the stack using push or call instructions. The register contains 8 bit stack top address. This stack may be defined anywhere in the on chip 128 by the RAM. After reset, the SP register is initialized to 07. After each write to stack operation, the 8 bit contents of the operand are stored on to the stack after incrementing the SP register by one . Thus if SP contains 07H, the forthcoming PUSH operation will store the data at address 08 H in the internal RAM .The SP content will be incremented to 08.The 8051 stack is not a top down data structure, like other Intel processors This register has also been allotted an address in the special function register bank . Data Pointer (DTPR) This 16 bit register contains a higher byte (DPH) and the lower byte (DPL) of a 16 bit external data RAM address. It is accessed as a 16 bit register or two 8bit register as specified above. It has been allotted two address in the special Function register bank for its two bytes DPH and DPL Port 0 to 3 latches and Drivers: These four latches and drivers pairs are allotted to each of the four on chip I/O Ports. These latches have been allotted addresses in the special function register bank
Chapter 7 : Intel 8051 Microcontroller using the allotted address the user can communicate with these ports. These are identified as P0, P1, P2 and P3 Serial data buffer: The serial data buffer internally contains two independent registers. one of them is a transmit buffer which is necessarily a parallel . Timing and control unit : This unit derives all the necessary timing and control signal required for the internal operation of the circuit It also derives control signal required for controlling the external system bus oscillator : This circuit generates the basic timing clock signal for the operation of the circuit using crystal oscillator . Instruction Register : This register decodes the opcode of an instruction to be executed and gives information to the timing and control unit to generate necessary signals for the execution of the instruction EPROM and Program Address Register : These blocks provide an on chip EPROM and a mechanism to internally adders it Note that EPROM is not available in all 8051 versions. RAM and RAM address Register . This block provide internal 128 bytes of RAM and mechanism to address it internally . ALU : The arithmetic and logic unit performs 8 bit arithmetic and logical operations over the operands held by the temporary registers TMPI and TMP2 .Users cannot access these temporary registers . SFR Register Bank : This is a set of special function registers which can be addressed using their respective address which lie in the range 80 H to FFH . Finally the interrupt , serial port and timer units control and perform their special functions under the control of the timing and control unit in serial out register . The other is called receive butter which in a serial in parallel out register. Loading a byte to the transmit buffer initiates serial transmission of that byte. The serial data butter in identified as SBUF and is one of the
Chapter 7 : Intel 8051 Microcontroller special function registers. If a byte is written to SBUF, it initiates serial transmission and if the SBUF is read, it reads received serial data . Timer Register : These two 16 bit register can be accessed as their lower and upper bytes. For example TL0 represents the lower byte of the timing register 0, while TH0 represents higher bytes of the timing register 0. Similarly TL1 and TH1 represents lower and higher bytes of timing register 1. All these registers can be accessed using the 4 addresses allotted to them which lies in the special function registers. SFR address range, ie 80H to FFH . Control Registers : The special function registers IP, IE, TMOD, TCON, SCON and PCON contain control and status information for interrupt timer/ counters and serial port.These register have been allotted address in the SFR bank of 8051 . 7.6 Memory Organization The 8051 microcontroller utilizes the Harvard architecture, with separate code and data spaces. Memory organization in 8051 is similar to that of the industry standard 8051. There are three memory areas, as shown in Figure 3: Program Memory (Internal RAM, External RAM, or External ROM) External Data Memory (External RAM) Internal Data Memory (Internal RAM)
Figure 3: 8051 Memory Map
Chapter 7 : Intel 8051 Microcontroller 7.6.1 Program Memory 8051 can address up to 64kB of program memory space, from 0000H to FFFFH. The External Bus Interface services program memory when the MEMPSRD signal is active. Program memory is read when the CPU performs fetching instructions or MOVC. After reset, the CPU starts program execution from location 0000H. The lower part of the program memory includes interrupt and reset vectors. The interrupt vectors are spaced at eight-byte intervals, starting from 0003H. Program memory can be implemented as Internal RAM, External RAM, External ROM, or a combination of all three.
Figure 4: Program memory 7.6.2 External Data Memory 8051 can address up to 64kB of external data memory space, from 0000H to FFFFH. The External Bus Interface services data memory when the MEMRD signal is active. Writing to external program memory is only supported in debug mode using the OCI logic block and external debugger hardware and software. 8051 writes into external data memory when the CPU executes MOVX @Ri ,A or MOVX @DPTR,A instructions. The external data memory is read when the CPU executes MOVX A, @Ri or MOVX A,@DPTR instructions. There is improved variable length of the MOVX instructions to
Chapter 7 : Intel 8051 Microcontroller access fast or slow external RAM and external peripherals. The three low-ordered bits of the CKCON register control stretch memory cycles. Setting CKCON stretch bits to logic 1 values enables access to very slow external RAM or external peripherals. There are two types of instructions; one provides an 8-bit address to the external data RAM, the other a 16-bit indirect address to the external data RAM. In the first instruction type, the contents of R0 or R1 in the current register bank provide an 8-bit address. The eight high ordered bits of address are stuck at zero. Eight bits are sufficient for external l/O expansion decoding or a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins are controlled by an output instruction preceding the MOVX. In the second type of MOVX instructions, the data pointer generates a 16-bit address. This form is faster and more efficient when accessing very large data arrays (up to 64kB), since no additional instructions are needed to set up the output ports. In some situations, it is possible to mix the two MOVX types. A large RAM array, with its high-order address lines, can be addressed via the data pointer or with code to output high-order address bits to any port followed by a MOVX instruction using R0 or R1. 7.6.3 Internal Data Memory The internal data memory interface services up to 256 bytes of off-core data memory. The internal data memory address is always one byte wide. The memory space is 256 bytes large (00H to FFH) and can be accessed by direct or indirect addressing. The SFRs occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing accesses the upper 128 bytes of internal RAM. The lower 128 bytes contain work registers and bit addressable memory. The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addressees 00H-7FH. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. The internal data memory is not instantiated in 8051. The user may use internal memory resources if the ProASICPLUS or Axcelerator families are used. The SX-A and RTSXS-S families have no internal memory resources, thus the user would need to either create and instantiate a distributed RAM or use an external memory device.
Lower 128 Bytes of Internal RAM
Upper 128 Bytes of Internal RAM
Figure 5: Internal Data Memory 7.6.4 On-Chip Memory. The 8051 includes a certain amount of on chip memory. On-chip memory is really one of two (SFR) memory. The layout of the 8051's internal memory is presented in the following memory map:
Figure 6 : On-Chip Memory As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM. This Internal RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is also the most flexible in terms of reading, writing, and modifying its contents. Internal RAM is volatile, so when the 8051 is reset this memory is cleared. The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes (00h - 07h) are "register bank 0". By manipulating certain SFRs, a program may choose to use register banks 1, 2, or 3. These alternative register banks are located in internal RAM in addresses 08h through 1Fh. We'll discuss "register banks" more in a later chapter. For now it is sufficient to know that they "live" and are part of internal RAM. Bit Memory also lives and is part of internal RAM. Bit memory actually resides in internal RAM, from addresses 20h through 2Fh. The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by user variables that need to be accessed frequently or at high-speed. This area is also utilized by the microcontroller as a storage area for the operating stack. This fact severely limits the 8051s stack since, as illustrated in the memory map, the area reserved for the stack is only 80 bytes and usually it is less since this 80 bytes has to be shared between the stack and user variables. 7.6.5 Bit Memory The 8051, being a communications oriented microcontroller, gives the user the ability to access a number of bit variables. These variables may be either 1 or 0. There are 128 bit variables available to the user, numbered 00h through 7Fh. The user may
Chapter 7 : Intel 8051 Microcontroller make use of these variables with commands such as SETB and CLR. It is important to note that Bit Memory is really a part of Internal RAM. In fact, the 128 bit variables occupy the 16 bytes of Internal RAM from 20h through 2Fh. Thus, if you write the value FFh to Internal RAM address 20h youve effectively set bits 00h through 07h. But since the 8051 provides special instructions to access these 16 bytes of memory on a bit by bit basis it is useful to think of it as a separate type of memory. However, always keep in mind that it is just a subset of Internal RAMand that operations performed on Internal RAM can change the values of the bit variables. Bit variables 00h through 7Fh are for user defined functions in their programs. However, bit variables 80h and above are actually used to access certain SFRs on a bitby-bit basis. 7.6.6 Special Function Register (SFR) Memory Special Function Registers (SFRs) are areas of memory that control specific functionality of the 8051 processor. For example, four SFRs permit access to the 8051s 32 input/output lines. Another SFR allows a program to read or write to the 8051s serial port. Other SFRs allow the user to set the serial baud rate, control and access timers, and configure the 8051s interrupt system. When programming, SFRs have the illusion of being Internal Memory. When using this method of memory access (its called direct address), any instruction that has an address of 00h through 7Fh refers to an Internal RAM memory address; any instruction with an address of 80h through FFh refers to an SFR control register. 7.7 8051 SFRs What Are SFRs? The 8051 is a flexible microcontroller with a relatively large number of modes of operations. Your program may inspect and/or change the operating mode of the 8051 by manipulating the values of the 8051's Special Function Registers (SFRs). SFRs are accessed as if they were normal Internal RAM. The only difference is that Internal RAM is from address 00h through 7Fh whereas SFR registers exist in the address range of 80h through FFh. Each SFR has an address (80h through FFh) and a name. The following chart provides a graphical presentation of the 8051's SFRs, their names, and their address.
Chapter 7 : Intel 8051 Microcontroller As you can see, although the address range of 80h through FFh offer 128 possible addresses, there are only 21 SFRs in a standard 8051. All other addresses in the SFR range (80h through FFh) are considered invalid. Writing to or reading from these registers may produce undefined values or behavior 7.7.1 SFR Types As mentioned in the chart itself, the SFRs that have a blue background are SFRs related to the I/O ports. The 8051 has four I/O ports of 8 bits, for a total of 32 I/O lines. Whether a given I/O line is high or low and the value read from the line are controlled by the SFRs in green. The SFRs with yellow backgrounds are SFRs which in some way control the operation or the configuration of some aspect of the 8051. For example, TCON controls the timers, SCON controls the serial port. The remaining SFRs, with green backgrounds, are "other SFRs." These SFRs can be thought of as auxiliary SFRs in the sense that they don't directly configure the 8051 but obviously the 8051 cannot operate without them. For example, once the serial port has been configured using SCON, the program may read or write to the serial port using the SBUF register.
Figure 7 : SFR 7.7.1.1 SFR Descriptions This section will endeavor to quickly overview each of the standard SFRs found in the above SFR chart map. It is not the intention of this section to fully explain the
Chapter 7 : Intel 8051 Microcontroller functionality of each SFR--this information will be covered in separate chapters of the tutorial. This section is to just give you a general idea of what each SFR does. 7.7.1. 2 P0 (Port 0, Address 80h, Bit-Addressable): This is input/output port 0. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. 7.7.1.3 SP (Stack Pointer, Address 81h): This is the stack pointer of the microcontroller. This FR indicates where the next value to be taken from the stack will be read from in Internal RAM. If you push a value onto the stack, the value will be written to the address of SP + 1. That is to say, if SP holds the value 07h, a PUSH instruction will push the value onto the stack at address 08h. This SFR is modified by all instructions which modify the stack, such as PUSH, POP, LCALL, RET, RETI, and whenever interrupts are provoked by the microcontroller. 7.7.1. 4 DPL/DPH (Data Pointer Low/High, Addresses 82h/83h): The SFRs DPL and DPH work together to represent a 16-bit value called the Data Pointer. The data pointer is used in operations regarding external RAM and some instructions involving code memory. Since it is an unsigned two-byte integer value, it can represent values from 0000h to FFFFh (0 through 65,535 decimal). 7.7.1.5 PCON (Power Control, Addresses 87h): The Power Control SFR is used to control the 8051's power control modes. Certain operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode which requires much less power. These modes of operation are controlled through PCON. Additionally, one of the bits in PCON is used to double the effective baud rate of the 8051's serial port. 7.7.1.6 TCON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control SFR is used to configure and modify the way in which the 8051's two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in the TCON SFR. These bits are used to
Chapter 7 : Intel 8051 Microcontroller configure the way in which the external interrupts are activated and also contain the external interrupt flags which are set when an external interrupt has occurred. Timer/Counter Control Register (TCON) Table displays the TCON register flags. MSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 Table TCON Register Bit Functions Bit Symbol Function 7 6 5 4 3 TF1 TR1 TF0 TR0 IE1 Timer 1 overflow flag. This flag is set when Timer 1 overflows. This flag should be cleared by the users software. Timer 1 Run control bit. If cleared, Timer 1 stops. Timer 0 overflow flag. This flag is set when Timer 0 overflows. This flag should be cleared by the users software. Timer 0 Run control bit. If cleared, Timer 0 stops. Interrupt 1 edge flag. This flag is set when a falling edge on the external pin int1 is observed. This flag is cleared when an interrupt is processed. 2 IT1 Interrupt 1 type control bit. This bit selects whether a falling edge or a low level on input pin int1 causes an interrupt. 1 IE0 Interrupt 0 edge flag. This flag is set when a falling edge on the external pin int0 is observed. This flag is cleared when an interrupt is processed. 0 IT0 Interrupt 0 type control bit. This bit selects whether a falling edge or a low level on input pin int0 causes an interrupt. LSB IT0
7.7.1.7 TMOD (Timer Mode, Addresses 89h): The Timer Mode SFR is used to configure the mode of operation of each of the two timers. Using this SFR your program may configure each timer to be a 16-bit timer, an 8-bit auto reload timer, a 13-bit timer, or two separate timers. Additionally, you may configure the timers to only count when an external pin is activated or to count "events" that are indicated on an external pin.
Chapter 7 : Intel 8051 Microcontroller Timer/Counter Mode Control Register (TMOD) MSB GATE C/T M1 M0 GATE C/T M1 LSB M0
< ------------- Timer 1 -------- <------------ Timer 1 ------ Table TMOD Register Bits Description Bit Symbol Function 7,3 GATE If set, enables external gate control (pin int0 or int1 for Counter 0 or Counter 1, respectively). When int0 or int1 is high, and the trx bit is set (see TCON register), the counter is incremented every falling edge on the t0 or t1 input pin. 6, 2 C/T Selects Timer or Counter operation. When set to logic 1, a Counter operation is performed. When cleared to logic 0, the corresponding register will function as a Timer. 5, 1 4, 0 M1 M0 Selects the mode for Timer/Counter 0 or Timer/Counter 1. Selects the mode for Timer/Counter 0 or Timer/Counter 1.
Table provides timer and counter mode descriptions. M1 0 M0 0 Mode Mode 0 Function 13-bit Counter/Timer, with five lower bits in the tl0 or tl1 register and eight bits in the th0 or th1 register (for Timer 0 and Timer 1, respectively). The three high order bits of the tl0 and tl1 registers are held at zero. 0 1 1 0 Mode 1 16-bit Counter/Timer
Mode2 8-bit auto-reload Counter/Timer. The reload value is kept in the TH0 or TH1 register, while the tl0 or tl1 register is incremented every machine cycle. When the tl0 or tl1 register overflows, the value in the th0 or th1 register is copied to the tl0 or tl1 register, respectively.
Mode3 If the M1 and M0 bits in Timer 1 are set to logic 1, Timer 1 stops. If the M1 and M0 bits in Timer 0 are set to logic 1, Timer 0 acts as two independent 8-bit Timers/Counters.
Chapter 7 : Intel 8051 Microcontroller 7.7.1.8 TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Bh): These two SFRs, taken together, represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value. 7.7.1.9 TL1/TH1 (Timer 1 Low/High, Addresses 8Ch/8Dh): These two SFRs, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value. 7.7.1.10 P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. 7.7.1.11 SCON (Serial Control, Addresses 98h, Bit-Addressable): The Serial Control SFR is used to configure the behavior of the 8051's on-board serial port. This SFR controls the baud rate of the serial port, whether the serial port is activated to receive data, and also contains flags that are set when a byte is successfully sent or received. 7.7.1.12 SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is used to send and receive data via the on-board serial port. Any value written to SBUF will be sent out the serial port's TXD pin. Likewise, any value which the 8051 receives via the serial port's RXD pin will be delivered to the user program via SBUF. In other words, SBUF serves as the output port when written to and as an input port when read from. 7.7.1.13 P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.
Chapter 7 : Intel 8051 Microcontroller 7.7.1.14 IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where as the highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is enabled by setting a lower bit. 7.7.1.15 P3 (Port 3, Address B0h, Bit-Addressable): This is input/output port 3. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. 7.7.1.16 IP (Interrupt Priority, Addresses B8h, Bit-Addressable): The Interrupt Priority SFR is used to specify the relative priority of each interrupt. On the 8051, an interrupt may either be of low (0) priority or high (1) priority. An interrupt may only interrupt interrupts of lower priority. For example, if we configure the 8051 so that all interrupts are of low priority except the serial interrupt, the serial interrupt will always be able to interrupt the system, even if another interrupt is currently executing. However, if a serial interrupt is executing no other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt routine has the highest priority. 7.7.1.17 PSW (Program Status Word, Addresses D0h, Bit-Addressable): The Program Status Word is used to store a number of important bits that are set and cleared by 8051 instructions. The PSW SFR contains the carry flag, the auxiliary carry flag, the overflow flag, and the parity flag. Additionally, the PSW register contains the register bank select flags which are used to select which of the "R" register banks are currently selected. 7.7.1.18 ACC (Accumulator, Addresses E0h, Bit-Addressable): The Accumulator is one of the most used SFRs on the 8051 since it is involved in so many instructions. The Accumulator resides as an SFR at E0h, which means the instruction MOV A,#20h is really the same as MOV E0h,#20h. However, it is a good
Chapter 7 : Intel 8051 Microcontroller idea to use the first method since it only requires two bytes whereas the second option requires three bytes. 7.7.1.19 B (B Register, Addresses F0h, Bit-Addressable): The "B" register is used in two instructions: the multiply and divide operations. The B register is also commonly used by programmers as an auxiliary register to temporarily store values. 7.8 8051 Basic Registers 7.8.1 Accumulator If youve worked with any other assembly languages you will be familiar with the concept of an Accumulator register. The Accumulator, as its name suggests, is used as a general register to accumulate the results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the most versatile register the 8051 has due to the shear number of instructions that make use of the accumulator. More than half of the 8051s 255 instructions manipulate or use the accumulator in some way. For example, if you want to add the number 10 and 20, the resulting 30 will be stored in the Accumulator. Once you have a value in the Accumulator you may continue processing the value or you may store it in another register or in memory. 7.8.2 "R" registers The "R" registers are a set of eight registers that are named R0, R1, etc. up to and including R7. These registers are used as auxiliary registers in many operations. The use of the "R" registers as a way to store values temporarily. 7.8.3 "B" Register The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-byte) value. The "B" register is only used by two 8051 instructions: MUL AB and DIV AB. Thus, if you want to quickly and easily multiply or divide A by another number, you may store the other number in "B" and make use of these two instructions. Aside from the MUL and DIV instructions, the "B" register is often used as yet another temporary storage register much like a ninth "R" register. 7.8.4 Data Pointer (DPTR) The Data Pointer (DPTR) is the 8051s only user-accessible 16-bit (2-byte) register. The Accumulator, "R" registers, and "B" register are all 1-byte values. DPTR, as
Chapter 7 : Intel 8051 Microcontroller the name suggests, is used to point to data. It is used by a number of commands which allow the 8051 to access external memory. When the 8051 accesses external memory it will access external memory at the address indicated by DPTR. While DPTR is most often used to point to data in external memory, many programmers often take advantage of the fact that its the only true 16- bit register available. It is often used to store 2- byte values which have nothing to do with memory locations. 7.8.5 Program Counter (PC) The Program Counter (PC) is a 2-byte address which tells the 8051 where the next instruction to execute is found in memory. When the 8051 is initialized PC always starts at 0000h and is incremented each time an instruction is executed. It is important to note that PC isnt always incremented by one. Since some instructions require 2 or 3 bytes the PC will be incremented by 2 or 3 in these cases. The Program Counter is special in that there is no way to directly modify its value. That is to say, you cant do something like PC=2430h. On the other hand, if you execute LJMP 2340h youve effectively accomplished the same thing. It is also interesting to note that while you may change the value of PC (by executing a jump instruction, etc.) there is no way to read the value of PC. 7.8.6 Stack Pointer (SP) The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1byte) value. The Stack Pointer is used to indicate where the next value to be removed from the stack should be taken from. When you push a value onto the stack, the 8051 first increments the value of SP and then stores the value at the resulting memory location. When you pop a value off the stack, the 8051 returns the value from the memory location indicated by SP, and then decrements the value of SP. This order of operation is important. When the 8051 is initialized SP will be initialized to 07h. If you immediately push a value onto the stack, the value will be stored in Internal RAM address 08h. This makes sense taking into account what was mentioned two paragraphs above: First the 8051 will increment the value of SP (from 07h to 08h) and then will store the pushed value at that memory address (08h). SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically whenever an interrupt is triggered
Chapter 7 : Intel 8051 Microcontroller 7.9 8051 Addressing Modes An "addressing mode" refers to how you are addressing a given memory location. In summary, the addressing modes are as follows, with an example of each: Immediate Addressing Direct Addressing Indirect Addressing External Direct Code Indirect MOV A,#20h MOV A,30h MOV A,@R0 MOVX A,@DPTR MOVC A,@A+DPTR
Each of these addressing modes provides important flexibility. 7.9.1 Immediate Addressing Immediate addressing is so-named because the value to be stored in memory immediately follows the operation code in memory. That is to say, the instruction itself dictates what value will be stored in memory. For example, the instruction: MOV A,#20h This instruction uses Immediate Addressing because the Accumulator will be loaded with the value that immediately follows; in this case 20 (hexadecimal). Immediate addressing is very fast since the value to be loaded is included in the instruction. However, since the value to be loaded is fixed at compile-time it is not very flexible. 7.9.2 Direct Addressing Direct addressing is so-named because the value to be stored in memory is obtained by directly retrieving it from another memory location. For example: MOV A,30h This instruction will read the data out of Internal RAM address 30 (hexadecimal) and store it in the Accumulator. Direct addressing is generally fast since, although the value to be loaded isnt included in the instruction, it is quickly accessible since it is stored in the 8051s Internal RAM. It is also much more flexible than Immediate Addressing since the value to be loaded is whatever is found at the given address which may be variable. Also, it is important to note that when using direct addressing any instruction which refers to an address between 00h and 7Fh is referring to Internal Memory. Any instruction which refers to an address between 80h and FFh is referring to the SFR control registers that control the 8051 microcontroller itself.
Chapter 7 : Intel 8051 Microcontroller 7.9.3 Indirect Addressing Indirect addressing is a very powerful addressing mode which in many cases provides an exceptional level of flexibility. Indirect addressing is also the only way to access the extra 128 bytes of Internal RAM found on an 8052. Indirect addressing appears as follows: MOV A,@R0 This instruction causes the 8051 to analyze the value of the R0 register. The 8051 will then load the accumulator with the value from Internal RAM which is found at the address indicated by R0. 7.9.4 External Direct External Memory is accessed using a suite of instructions which use what I call "External Direct" addressing. I call it this because it appears to be direct addressing, but it is used to access external memory rather than internal memory. There are only two commands that use External Direct addressing mode: MOVX A,@DPTR MOVX @DPTR,A As you can see, both commands utilize DPTR. In these instructions, DPTR must first be loaded with the address of external memory that you wish to read or write. Once DPTR holds the correct external memory address, the first command will move the contents of that external memory address into the Accumulator. The second command will do the opposite: it will allow you to write the value of the Accumulator to the external memory address pointed to by DPTR. 7.9.5 External Indirect External memory can also be accessed using a form of indirect addressing which I call External Indirect addressing. This form of addressing is usually only used in relatively small projects that have a very small amount of external RAM. An example of this addressing mode is: MOVX @R0,A Once again, the value of R0 is first read and the value of the Accumulator is written to that address in External RAM. Since the value of @R0 can only be 00h through FFh the project would effectively be limited to 256 bytes of External RAM. There are relatively simple hardware/software tricks that can be implemented to access more than 256 bytes of memory using External Indirect
Chapter 7 : Intel 8051 Microcontroller addressing; however, it is usually easier to use External Direct addressing if your project has more than 256 bytes of External RAM. 7.10 8051 Timers The 8051 comes equipped with two timers, both of which may be controlled, set, read, and configured individually. The 8051 timers have three general functions: 1) Keeping time and/or calculating the amount of time between events, 2) Counting the events themselves, or 3) Generating baud rates for the serial port. 7.10 .1 Timer SFRs As mentioned before, the 8051 has two timers which each function essentially the same way. One timer is TIMER0 and the other is TIMER1. The two timers share two SFRs (TMOD and TCON) which control the timers, and each timer also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1). Weve given SFRs names to make it easier to refer to them, but in reality an SFR has a numeric address. It is often useful to know the numeric address that corresponds to an SFR name. When you enter the name of an SFR into an assembler, it internally converts it to a number. The SFRs relating to timers are: SFR Name TH0 TL0 TH1 TL1 TCON TMOD Description Timer 0 High Byte Timer 0 Low Byte Timer 1 High Byte Timer 1 Low Byte Timer Control Timer Mode SFR Address 8Ch 8Ah 8Dh 8Bh 88h 89h
7.10 .1.1 TMOD SFR The TMOD SFR is used to control the mode of operation of both timers. Each bit of the SFR gives the microcontroller specific information concerning how to run a timer. The high four bits (bits 4 through 7) relate to Timer 1 whereas the low four bits (bits 0 through 3) perform the exact same functions, but for timer 0. The individual bits of TMOD have the following functions:
Chapter 7 : Intel 8051 Microcontroller Bit Name Explanation of Function When this bit is set the timer will only run when INT1 (P3.3) is 7 GATE1 high. When this bit is clear the timer will run regardless of the state 1 of INT1. 6 5 4 C/T1 T1M1 T1M0 When this bit is set the timer will count events on T1 (P3.5). When this bit is clear the timer will be incremented every machine cycle. Timer mode bit (see below) Timer mode bit (see below) When this bit is set the timer will only run when INT0 (P3.2) is 3 GATE0 high. When this bit is clear the timer will run regardless of the state 0 of INT0. 2 1 0 C/T0 T0M1 T0M0 When this bit is set the timer will count events on T0 (P3.4). When this bit is clear the timer will be incremented every machine cycle. Timer mode bit (see below) Timer mode bit (see below) 0 0 0 1 1 1 Timer
As you can see in the above chart, four bits (two for each timer) are used to specify a mode of operation. The modes of operation are: TxM1 TxM0 0 0 1 1 0 1 0 1 Timer Mode 0 1 2 3 Description Mode 13-bit Timer. 16-bit Timer 8-bit auto-reload Split timer mode of
13-bit Time Mode (mode 0) Timer mode "0" is a 13-bit timer. This is a relic that was kept around in the 8051 to maintain compatibility with its predecessor, the 8048. Generally the 13-bit timer mode is not used in new development. When the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx is incremented from 31, it will "reset" to 0 and increment THx. Thus, effectively, only 13 bits of the two timer bytes are being used: bits 0-4 of TLx and bits 07 of THx. This also means, in essence, the timer can only contain 8192 values. If you set a 13-bit timer to 0, it will overflow back to zero 8192 machine cycles later.
Chapter 7 : Intel 8051 Microcontroller 16-bit Time Mode (mode 1) Timer mode "1" is a 16-bit timer. This is a very commonly used mode. It functions just like 13-bit mode except that all 16 bits are used. TLx is incremented from 0 to 255. When TLx is incremented from 255, it resets to 0 and causes THx to be incremented by 1. Since this is a full 16- bit timer, the timer may contain up to 65536 distinct values. If you set a 16-bit timer to 0, it will overflow back to 0 after 65,536 machine cycles. 8-bit Time Mode (mode 2) Timer mode "2" is an 8-bit auto-reload mode. When a timer is in mode 2, THx holds the "reload value" and TLx is the timer itself. Thus, TLx starts counting up. When TLx reaches 255 and is subsequently incremented, instead of resetting to 0 (as in the case of modes 0 and 1), it will be reset to the value stored in THx. Split Timer Mode (mode 3) Timer mode "3" is a split-timer mode. When Timer 0 is placed in mode 3, it essentially becomes two separate 8-bit timers. That is to say, Timer 0 is TL0 and Timer 1 is TH0. Both timers count from 0 to 255 and overflow back to 0. All the bits that are related to Timer 1 will now be tied to TH0. While Timer 0 is in split mode, the real Timer 1 (i.e. TH1 and TL1) can be put into modes 0, 1 or 2 normally however, you may not start or stop the real timer 1 since the bits that do that are now linked to TH0. The real timer 1, in this case, will be incremented every machine cycle no matter what. The only real use I can see of using split timer mode is if you need to have two separate timers and, additionally, a baud rate generator. In such case you can use the real Timer 1 as a baud rate generator and use TH0/TL0 as two separate timers. 7.10 .1.2 TCON SFR Finally, theres one more SFR that controls the two timers and provides valuable information about them. The TCON SFR has the following structure: Bit Name Bit Addres 7 TF1 8Fh Explanation of Function Timer 1 Overflow. This bit is set by the microcontroller when Timer 1 overflows. Timer 1 Run. When this bit is set Timer 1 is turned on. When this bit is clear Timer 1 is off. Timer 1
TR1
8Eh
Chapter 7 : Intel 8051 Microcontroller Timer 0 Overflow. This bit is set by the microcontroller when Timer 0 overflows. Timer 0 Run. When this bit is set Timer 0 is turned on. When this bit is clear Timer 0 is off.
TF0
8Dh
TR0
8Ch
As you may notice, weve only defined 4 of the 8 bits. Thats because the other 4 bits of the SFR dont have anything to do with timers they have to do with Interrupts A new piece of information in this chart is the column "bit address." This is because this SFR is "bit-addressable." Bit addressable means, if you want to set the bit TF1 which is the highest bit of TCON you could execute the command: MOV TCON, #80h or, since the SFR is bit addressable, you could just execute the command: SETB TF1 This has the benefit of setting the high bit of TCON without changing the value of any of the other bits of the SFR. Usually when you start or stop a timer you dont want to modify the other values in TCON, so you take advantage of the fact that the SFR is bit-addressable. 7.10.2 Initializing a Timer Now that weve discussed the timer related SFRs we are ready to write code that will initialize the timer and start it running. As youll recall, we first must decide what mode we want the timer to be in. In this case we want a 16-bit timer that runs continuously; that is to say, it is not dependent on any external pins. We must first initialize the TMOD SFR. Since we are working with timer 0 we will be using the lowest 4 bits of TMOD. The first two bits, GATE0 and C/T0 are both 0 since we want the timer to be independent of the external pins. 16-bit mode is timer mode 1 so we must clear T0M1 and set T0M0. Effectively, the only bit we want to turn on is bit 0 of TMOD. Thus to initialize the timer we execute the instruction: MOV TMOD,#01h Timer 0 is now in 16-bit timer mode. However, the timer is not running. To start the timer running we must set the TR0 bit We can do that by executing the instruction: SETB TR0 Upon executing these two instructions timer 0 will immediately begin counting, being incremented once every machine cycle (every 12 crystal pulses). 7.10.3 Reading the Timer There are two common ways of reading the value of a 16-bit timer; which you use depends on your specific application. You may either read the actual value of the timer as a 16-bit number, or you may simply detect when the timer has overflowed.
Chapter 7 : Intel 8051 Microcontroller 7.10.4 Reading the value of a Timer If your timer is in an 8-bit mode that is, either 8-bit Auto Reload mode or in split timer mode then reading the value of the timer is simple. You simply read the 1-byte value of the timer and youre done. However, if youre dealing with a 13-bit or 16-bit timer the chore is a little more complicated. Consider what would happen if you read the low byte of the timer as 255, then read the high byte of the timer as 15. In this case, what actually happened was that the timer value was 14/255 (high byte 14, low byte 255) but you read 15/255. Why? Because you read the low byte as 255. But when you executed the next instruction a small amount of time passed but enough for the timer to increment again at which time the value rolled over from 14/255 to 15/0. But in the process youve read the timer as being 15/255. You read the high byte of the timer, then read the low byte, then read the high byte again. If the high byte read the second time is not the same as the high byte read the first time you repeat the cycle. In code, this would appear as: REPEAT: MOV A,TH0 MOV R0,TL0 CJNE A,TH0,REPEAT In this case, we load the accumulator with the high byte of Timer 0. We then load R0 with the low byte of Timer 0. Finally, we check to see if the high byte we read out of Timer 0 which is now stored in the Accumulator is the same as the current Timer 0 high byte. If it isnt it means weve just "rolled over" and must reread the timers value which we do by going back to REPEAT. When the loop exits we will have the low byte of the timer in R0 and the high byte in the Accumulator. Another much simpler alternative is to simply turn off the timer run bit (i.e. CLR TR0), read the timer value, and then turn on the timer run bit (i.e. SETB TR0). This implies that the timer will be stopped for a few machine cycles. 7.10.5 Detecting Timer Overflow Often it is necessary to just know that the timer has reset to 0. That is to say, you are not particularly interest in the value of the timer but rather you are interested in knowing when the timer has overflowed back to 0. Whenever a timer overflows from its highest value back to 0, the microcontroller automatically sets the TFx bit in the TCON register. This is useful since rather than checking the exact value of the timer you can just check if
Chapter 7 : Intel 8051 Microcontroller the TFx bit is set. If TF0 is set it means that timer 0 has overflowed; if TF1 is set it means that timer 1 has overflowed. We can use this approach to cause the program to execute a fixed delay. As youll recall, we calculated earlier that it takes the 8051 1/20th of a second to count from 0 to 46,079. However, the TFx flag is set when the timer overflows back to 0. Thus, if we want to use the TFx flag to indicate when 1/20th of a second has passed we must set the timer initially to 65536 less 46079, or 19,457. If we set the timer to 19,457, 1/20th of a second later the timer will overflow. Thus we come up with the following code to execute a pause of 1/20th of a second: MOV TH0,#76 MOV TL0,#01 ;High byte of 19,457 (76 * 256 = 19,456) ;Low byte of 19,457 (19,456 + 1 = 19,457)
MOV TMOD,#01 ;Put Timer 0 in 16-bit mode SETB TR0 JNB TF0,$ ;Make Timer 0 start counting ;If TF0 is not set, jump back to this same instruction
In the above code the first two lines initialize the Timer 0 starting value to 19,457. The next two instructions configure timer 0 and turn it on. Finally, the last instruction JNB TF0,$, reads "Jump, if TF0 is not set, back to this same instruction." The "$" operand means, in most assemblers, the address of the current instruction. Thus as long as the timer has not overflowed and the TF0 bit has not been set the program will keep executing this same instruction. After 1/20th of a second timer 0 will overflow, set the TF0 bit, and program execution will then break out of the loop. 7.10.6 Using Timers As Event Counters The 8051 also allows us to use the timers to count events. How can this be useful? Let's say you had a sensor placed across a road that would send a pulse every time a car passed over it. This could be used to determine the volume of traffic on the road. We could attach this sensor to one of the 8051's I/O lines and constantly monitor it, detecting when it pulsed high and then incrementing our counter when it went back to a low state. This is not terribly difficult, but requires some code. 7.11 Interrupt Service Routine Unit 8051 provides 13 interrupt sources with four priority levels. Each source has its own request flag(s) located in a SFR (TCON, SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in the ien0
Chapter 7 : Intel 8051 Microcontroller and ien1 registers. There are two external interrupts accessible through pins int0 and int1: edge or level sensitive (falling edge or low level). There are also internal interrupts associated with Timer 0 and Timer 1, and an internal interrupt from the serial port. 7.11.1 External Interrupts The choice between external (int0 and int1) interrupt level or transition activity is made by setting the IT1 and IT0 bits in the SFR TCON. When the interrupt event happens, a corresponding interrupt control bit is set in the TCON register (IE0 or IE1). This control bit triggers an interrupt if the appropriate interrupt bit is enabled. When the interrupt service routine is vectored, the corresponding control bit (IE0 or IE1) is cleared provided the edge triggered mode was selected. If level mode is active, the external requesting source controls flags IE0 or IE1 by the logic level on pins int0 or int1 (logic 0 or logic 1). During high to low transitions, recognition of an interrupt event is possible if both high and low levels last at least one machine cycle. 7.11.2 Timer 0 and Timer 1 Interrupts Timer 0 and 1 interrupts are generated by the TF0 and TF1 flags in the TCON register, which are set by the rollover of Timer 0 and 1, respectively. When an interrupt is generated, the flag that caused this interrupt is cleared if 8051 has accessed the corresponding interrupt service vector. This can be done only if the interrupt is enabled in the ien0 register. 7.11.3 Serial Port Interrupt The serial port interrupt is generated by logical OR of the TI and RI flags in the SFR SCON. The TI flag is set after the data transmission completes. The RI flag is set when the last bit of the incoming serial data was read. Neither RI nor TI is cleared by 8051, so the users interrupt service routine must clear these flags. Special Function Registers Table1 displays the Interrupt Enable 0 register (ie0). MSB eal es0 et1 ex1 et0 LSB ex0
Table 2 provides the ien0 bit functions. Bit 7 Symbol Function eal eal=0 disable all interrupts
Chapter 7 : Intel 8051 Microcontroller 6 5 4 3 2 1 0 es0 et1 ex1 et0 ex0 Not used for interrupt control Not used for interrupt control es0=0 disable serial channel 0 interrupt et1=0 disable timer 1 overflow interrupt ex1=0 disable external interrupt 1 et0=0 disable timer 0 overflow interrupt ex0=0 disable external interrupt 0
Table 3 displays the Interrupt Enable 1 register (ien1). MSB ex7 ex6 ex5 ex4 ex3 ex2 LSB ex1 ex0
Table 4 provides the ien1 bit functions. Bit 7 6 5 4 3 2 1 0 Symbol ex7 ex6 ex5 ex4 ex3 ex2 ex1 ex0 Function ex7=0 disable int7 ex6=0 disable int6 ex5=0 disable int5 ex4=0 disable int4 ex3=0 disable int3 ex2=0 disable int2 ex1=0 disable int1a ex0=0 disable int0a
7.11.4 Priority Level Structure All interrupt sources are combined in priority level groups and controlled in terms of priority level by bits in the ip0 and ip1 registers.
Table 5 displays the Interrupt Priority 0 register (ip0). MSB ip0.5 ip0.4 ip0.3 ip0.2 LSB ip0.1 ip0.0
Chapter 7 : Intel 8051 Microcontroller Table 6 displays the Interrupt Priority 1 register (ip1). MSB ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 LSB ip1.0
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register ip0 and one in ip1. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced first. For example, in Table 8 the two interrupts, Timer 0 interrupt and external pin int2, are combined in a priority group and are priority level controlled by the combination of bit0 from the ip0 register and bit0 from the ip1 register. Table 7 displays the priority levels. ip1.x 0 0 1 1 ip0.x 0 1 0 1 Priority Level Level0 (lowest) Level1 Level2 Level3 (highest)
Table 8 displays the groups of priority. Bit Group
ip1.0,ip0.0 External interrupt 0(ie0), int0a, int1a ip1.1,ip0.1 Timer 0 interrupt, int2 ip1.2,ip0.2 External interrupt 1(ie1), int3 ip1.3,ip0.3 Timer 1 interrupt, int4 ip1.4,ip0.4 Serial channel 0 interrupt, int5 ip1.5,ip0.5 int6, int7
Table 9 displays the polling sequence. External interrupt 0(ie0) int0a int1a Timer 0 interrupt
Chapter 7 : Intel 8051 Microcontroller int2 External interrupt 1(ie1) int3 Timer 1 interrupt int4 Serial channel 0 interrupt int5 int6 int7
7.11.5 Interrupt Vectors Table 10 Interrupt Vector Addresses Interrupt Request Flags ie0 External interrupt 0 tf0 Timer 0 interrupt ie1 External interrupt 1 tf1 Timer 1 interrupt ri0/ti0 Serial channel 0 interrupt int6 int0a int1a int2 int3 int4 int5 int7 Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0083H 0043H 004BH 0053H 005BH 0063H 006BH
7.11.6 Interrupt Detect The interrupts int0a, int1a, and int2 to int7 are activated by level and the active state is logic 1 (high). Each of these interrupt pins must be held at a logic 1 value until 8051 starts to service the affected interrupt. The user's software must take the appropriate
Chapter 7 : Intel 8051 Microcontroller action to clear each interrupt request (by writing to external peripherals via the external SFR interface). 7.11.7 External Interrupt Connection (int) Interrupt ie0 ie1 Tf0 Tf1 Ri0 Ti0 int0a int1a int2 int3 int4 int5 int6 int7 Device Timer 0 Timer 1 Serial 0 Serial 0 Source External pin External pin External pin External pin External pin External pin External pin External pin External pin External pin
Chapter 7 : Intel 8051 Microcontroller ISR Structure
Figure 8 : Overview Of The Interrupt Service Routine
Chapter 7 : Intel 8051 Microcontroller 7.12 Power Management Unit The Power Management Unit monitors two power management modes: IDLE and STOP. 7.12.1 Idle Mode Setting the idle bit of the pcon register invokes the IDLE mode. The IDLE mode can be used to leave internal clocks and peripherals running. Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts or a reset. 7.12.2 Stop Mode Setting the stop bit of the pcon register invokes the STOP mode. All internal clocking in this mode can be turned off. The CPU will exit this state from a non-clocked external interrupt or a reset condition. Internally generated interrupts (timer, serial port, etc.) are not useful since they require clocking activity. Special Function Registers Table 1 displays the pcon register. MSB smod gf1 gf0 stop Table 2 pcon Bit Functions Bit 7 6 5 6 3 4 1 Symbol smod gf1 gf0 stop Function Not used for power management General purpose flag 1 General purpose flag 0 Stop mode control bit. Setting this bit places 8051 into Stop Mode. This bit is always read as logic 0. 0 idle Idle mode control bit. Setting this bit places 8051 into Idle Mode. This bit is always read as logic 0. LSB idle
7.12.3 Power Management Implementation
Chapter 7 : Intel 8051 Microcontroller 8051 contains internal logic that allows the user to implement clock gating for the clkcpu (CPU clock) and clkper (peripheral clock) domains. If the user doesnt require usage of the IDLE or STOP modes, Actel recommends connecting the three clock inputs (clk, clkcpu, and clkper) together, as shown in Figure 9 (leaving the clkcpu_en and clkper_en output signals unconnected). If the user wishes to implement the IDLE and STOP power-saving modes, this can be realized by connecting 8051 as shown in Figure 10, where the user must connect two AND gates, external to 8051, to accomplish the clock gating (making use of the clkcpu_en and clkper_en signals as well as the clk signal); the gated clock signals must then connect to the clkcpu and clkper input signals, as shown in Figure 10. If the user connects 8051 as shown in Figure 10, Actel recommends using the CLKPER signal to connect to peripherals, as it will be active during the IDLE mode.
Figure 9 : 8051 Unified Clock Domain Connection Diagram
Figure 10 : 8051 Power Management Connection Diagram
Chapter 7 : Intel 8051 Microcontroller 7.13 Serial Interface 7.13.1 Serial Port 0 The serial buffer consists of two separate registers: transmit buffer and receive buffer. Writing data to the SFR sbuf sets this data in the serial output buffer and starts the transmission. Reading from the sbuf register reads data from the serial receive buffer. The serial port can simultaneously transmit and receive data. It can also buffer one byte at receive, which prevents the receive data from being lost if the CPU reads the first byte before transmission of the second byte is completed. The serial port can operate in one of four modes. a) Mode 0 In this mode, the rxd0i pin receives serial data and the rxd0o pin transmits serial data. The txd0 pin outputs the shift clock. Eight bits are transmitted with LSB first. The baud rate is fixed at 1/12 of the crystal (clk input) frequency. b) Mode 1 In this mode, the rxd0i pin receives serial data and the txd0 pin transmits serial data. No external shift clock is used, and the following 10 bits are transmitted: One Start Bit (always 0) Eight Data Bits (LSB first) One Stop Bit (always 1) On receive, a start bit synchronizes the transmission, eight data bits are available by reading the sbuf register, and a stop bit sets the flag RB8 in the SFR scon. c) Mode 2 This mode is similar to Mode 1 but has two main differences. The baud rate is fixed at 1/32 or 1/64 of the oscillator (clk input) frequency, and the following 11 bits are transmitted or received: One Start Bit (0) Eight Data Bits (LSB first) One Programmable Ninth Bit One Stop Bit (1)
Chapter 7 : Intel 8051 Microcontroller The ninth bit can be used to control the parity of the serial interface. At transmission, the TB8 bit in the scon register is output as the ninth bit, and at receive, the ninth bit affects the RB8 bit in the SFR scon. d) Mode 3 The only difference between Mode 2 and Mode 3 is that the baud rate is variable in Mode 3. Reception is initialized in Mode 0 by setting the RI flag in the scon register to logic 0 and the REN flag in the scon register to logic 1. In other modes, if the REN flag is a logic 1, the reception of serial data will begin with a start bit. 7.13.2 Multiprocessor Communication The nine-bit reception feature in Modes 2 and 3 can be used for multiprocessor communication. In this case, the SM2 bit in the scon register is set to logic 1 by the slave processors. When the master processor outputs the slave address, it sets the ninth bit to logic 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received byte with their network address. If there is a match, the addressed slave will clear SM2 and receive the rest of the message, while other slaves will leave the SM2 bit unaffected and ignore this message. After addressing the slave, the master will output the rest of the message with the ninth bit set to logic 0, so no serial port receive interrupt will be generated in unselected slaves. 7.13.3 Serial Port Control Register (SCON) The function of the serial port depends on the setting of the Serial Port Control Register scon. The various register flags, bit descriptions, mode descriptions, and baud rates are listed in Table 3 to Table 6. Note that in the following tables, fosc represents the frequency of the clk input signal. 7.13.4 Generating Variable Baud Rate in Modes 1 and 3 In Modes 1 and 3, the Timer 1 overflow rate is used to generate baud rates. If Timer 1 is configured at auto in auto-reload mode to establish a baud rate, the following equation is useful: Table 3 SCON Register Flags MSB LSB
SM0 SM1 SM2 REN TB8 RB8 TI RI
Chapter 7 : Intel 8051 Microcontroller Table 4 SCON Bit Functions Bit Symbol Function 7 6 5 4 3 SM0 SM1 SM2 REN TB8 Sets baud rate Sets baud rate Enables multiprocessor communication feature If set, enables serial reception. Cleared by software to disable reception. The ninth transmitted data bit in Modes 2 and 3. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication, etc.). 2 RB8 In Modes 2 and 3, the ninth data bit received. In Mode 1, if SM2 is '0', RB8 is the stop bit. In Mode 0 this bit is not used. Must be cleared by the software. 1 TI Transmits the interrupt flag and is set by the hardware after completion of a serial transfer. Must be cleared by the software. 0 RI Receives the interrupt flag and is set by the hardware after completion of a serial reception. Must be cleared by the software. Table 5 Serial Port Modes SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate fosc/12 variable fosc/32 or /64 variable
Table 6 Serial Port Baud Rates Mode Mode 0 Mode 1,3 Mode 2 Baud Rate fosc12 Timer 1 overflow rate SMOD = 0 fosc/64 SMOD = 1 fosc/32
7.13.5 Generating Variable Baud Rate in Modes 1 and 3 In Modes 1 and 3, the Timer 1 overflow rate is used to generate baud rates. If Timer 1 is configured at auto in auto-reload mode to establish a baud rate, the following equation is useful: Baud Rate 2SMOD fosc / 32 12 (256 - th1)
Chapter 7 : Intel 8051 Microcontroller 7.14 8051 Microcontroller Instruction Set 8051 instructions have 8-bit opcode Some instructions have one or two additional bytes for data or address There are 139 1-byte instructions, 92 2-byte instructions, and 24 3-byte instruction Instructions that Affect Flag Settings Instruction Flag C ADD ADDC SUBB MUL DIV DA RRC RLC SETB C X X X O O X X X 1 OV X X X X X AC X X X CLR C CPL C ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit CJNE Instruction Flag C O X X X X X X X OV AC
The Instruction Set and Addressing Modes Rn direct Register R7-R0 of the currently selected Register Bank. 8-bit internal data locations address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)]. @Ri #data #data 16 addr 16 8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0. 8-bit constant included in instruction. 16-bit constant included in instruction. 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K byte Program Memory address space. addr 11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of program memory as the first byte of the following instruction.
Chapter 7 : Intel 8051 Microcontroller rel Signed (twos complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. bit Direct Addressed bit in Internal Data RAM or Special Function Register.
ARITHMETIC OPERATION Mnemonic ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A Description Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Accumulator with Carry Add direct byte to Accumulator with Carry Add indirect RAM to Accumulator with Carry Add immediate data to Acc with Carry Subtract Register from Acc with borrow Subtract direct byte from Acc with borrow Subtract indirect RAM from ACC with borrow Subtract immediate data from Acc with borrow Increment Accumulator Increment register Increment direct byte Increment direct RAM Decrement Accumulator Decrement Register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A & B Divide A by B Decimal Adjust Accumulator
Chapter 7 : Intel 8051 Microcontroller LOGICAL OPERATIONS Mnemonic ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC A,Rn A,direct A,@Ri A,#data direct,A Description AND Register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte
direct,#data AND immediate data to direct byte A,Rn A,direct A,@Ri A,#data direct,A OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte
direct,#data OR immediate data to direct byte A,Rn A,direct A,@Ri A,#data direct,A Exclusive-OR register to Accumulator Exclusive-OR direct byte to Accumulator Exclusive-OR indirect RAM to Accumulator Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct byte
direct,#data Exclusive-OR immediate data to direct byte A A A A A A Clear Accumulator Complement Accumulator Rotate Accumulator Left Rotate Accumulator Left through the Carry Rotate Accumulator Right Rotate Accumulator Right through the Carry
Chapter 7 : Intel 8051 Microcontroller SWAP A Swap nibbles within the Accumulator
DATA TRANSFER MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD A,Rn A,direct A,@Ri A,#data Rn,A Rn,direct Rn,#data direct,A direct,Rn direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data DPTR,#data16 A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rn A,direct A,@Ri A,@Ri Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load Data Pointer with a 16-bit constant Move Code byte relative to DPTR to Acc Move Code byte relative to PC to Acc Move External RAM (8-bit addr) to Acc Move Exernal RAM (16- bit addr) to Acc Move Acc to External RAM (8-bit addr) Move Acc to External RAM (16-bit addr) Push direct byte onto stack Pop direct byte from stack Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low-order Digit indirect RAM with Acc
BOOLEAN VARIABLE MANIPULATION CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV JC JNC JB JNB JBC ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ CJNE addr11 addr16 rel @A+DPTR rel rel A,direct,rel C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C rel rel bit,rel bit,rel bit,rel addr11 addr16 Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to CARRY AND complement of direct bit to Carry OR direct bit to Carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry not set Jump if direct Bit is set Jump if direct Bit is Not set Jump if direct Bit is set & clear bit Absolute Subroutine Call Long Subroutine Call Return from Subroutine Return from interrupt Absolute Jump Long Jump Short Jump (relative addr) Jump indirect relative to the DPTR Jump if Accumulator is Zero Jump if Accumulator is Not Zero Compare direct byte to Acc and Jump if Not Equal
Chapter 7 : Intel 8051 Microcontroller CJNE CJNE CJNE DJNZ DJNZ NOP A,#data,rel Rn,#data,rel @Ri,#data,rel Rn,rel direct,rel Compare immediate to Acc and Jump if Not Equal Compare immediate to register and Jump if Not Equal Compare immediate to indirect and Jump if Not Equal Decrement register and Jump if Not Zero Decrement direct byte and Jump if Not Zero No Operation
Chapter 7 : Intel 8051 Microcontroller Two Marks Questions And Answer 1. What is mean by microcontroller? A device which contains the microprocessor with integrated peripherals like memory, serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC,DAC is called microcontroller. 2. Explain DJNZ instructions of intel 8051 microcontroller? a. DJNZ Rn, rel Decrement the content of the register Rn and jump if not zero. b. DJNZ direct , rel Decrement the content of direct 8-bit address and jump if not zero. 3. Explain the contents of the accumulator after the execution ot the following program segments: MOV A,#3CH MOV R4,#66H ANL A,R4 A 3C R4 66 A 24
4. State the function of RS1 and RS0 bits in the flag register of intel 8051 microcontroller? RS1, RS0 Register bank select bits RS1 0 0 1 1 RS0 0 1 0 1 Bank Selection Bank0 Bank1 Bank2 Bank3
Chapter 7 : Intel 8051 Microcontroller 5. Write a program using 8051 assembly language to change the date 55H stored in the lower byte of the data pointer register to AAH using rotate instruction. MOV DPL,#55H MOV A, DPL RL A Label : SJMP Label 6. Give the alternate functions for the port pins of port3?
RD
WR
T1
T0
INT1
INT0
TXD
RXD
RD Read data control output. WR Write data control output. T1 Timer / Counter1 external input or test pin. T0 Timer / Counter0 external input or test pin. INT1- Interrupt 1 input pin. INT 0 Interrupt 0 input pin. TXD Transmit data pin for serial port in UART mode. RXD - Receive data pin for serial port in UART mode. 7. Specify the single instruction, which clears the most significant bit of B register of 8051, without affecting the remaining bits. Single instruction, which clears the most significant bit of B register of 8051, without affecting the remaining bits is CLR B.7. 8. Explain the function of the pins PSEN and EA of 8051. PSEN : PSEN stands for program store enable. In 8051 based system in which an external ROM holds the program code, this pin is connected to the OE pin of the ROM. EA : EA stands for external access. When the EA pin is connected to Vcc, program fetched to addresses 0000H through 0FFFH are directed to the internal ROM and program fetches to addresses 1000H through FFFFH are directed to external
Chapter 7 : Intel 8051 Microcontroller ROM/EPROM. When the EA pin is grounded, all addresses fetched by program are directed to the external ROM/EPROM. 9. Explain the 16-bit registers DPTR and SP of 8051. DPTR: DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16- bit address. It may be manipulated as a 16-bit data register or as two independent 8-bit registers. It serves as a base register in indirect jumps, lookup table instructions and external data transfer. SP: SP stands for stack pointer. SP is a 8- bit wide register. It is incremented before data is stored during PUSH and CALL instructions. The stack array can reside anywhere in on-chip RAM. The stack pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H. 10. Name the special functions registers available in 8051. a. Accumulator b. B Register c. Program Status Word. d. Stack Pointer. e. Data Pointer. f. Port 0 g. Port 1 h. Port 2 i. Port 3 j. Interrupt priority control register. k. Interrupt enable control register.
Chapter 7 : Intel 8051 Microcontroller 11. Write down the different operating modes for serial communication of 8051. Serial communication of 8051 operate under four modes. They are mode 0 , mode 1, mode 2 and mode3 .SM0 and SM1 bits of SCON register specifies the mode. SM0 0 0 1 SM1 0 1 0 Mode 0 1 2 Baud rate fixed 8-bit data, 1 stop bit, 1 start bit. Baud rate variable. 8-bit data, 9th programmable bit,1 stop bit, 1 start bit, Baud rate fixed. 1 1 3 8-bit data, 9th programmable bit,1 stop bit, 1 start bit, Baud rate variable.
12. Explain the register IE format of 8051. EA -ET2 ES ET1 EX1 ET0 EX0
EA- Enable all control bit. ET2- Timer 2 interrupt enable bit. ES Enable serial port control bit. ET1 Enable Timer1 control bit. EX1- Enable external interrupt1 control bit. ET0 Enable Timer0 control bit. EX0- Enable external interrupt0 control bit. 13. Compare Microprocessor and Microcontroller. S.No Microprocessor Microcontroller
Microprocessor contains ALU,general Microcontroller contains the circuitry purpose registers,stack pointer, of microprocessor and in addition it
program counter, clock timing circuit has built- in ROM, RAM, I/O and interrupt circuit. 2 devices, timers and counters.
It has many instructions to move data It has one or two instructions to move between memory and CPU data between memory and CPU.
It has one or two bit handling It has many bit handling instructions. instructions.
Chapter 7 : Intel 8051 Microcontroller 4 Access times for memory and I/O Less access times for built-in memory devices are more. 5 and I/O devices. based system
Microprocessor based system requires Microcontroller more hardware.
requires less hardware reducing PCB size and increasing the reliability.
14. Name the five interrupt sources of 8051?. The interrupts are: Vector address External interrupt 0 : Timer interrupt 0 : External interrupt 1 : Timer Interrupt 1 : Serial Interrupt Receive interrupt : Transmit interrupt: RI : TI : 0023H 0023H IE0 : 0003H
TF0 : 000BH IE1 : 0013H TF1 : 001BH
15. Write a program to load accumulator A, DPH and DPL with 30H. MOV A,#30 MOV DPH,A MOV DPL,A 16. Write a program to subtract the contents of R1 of Bank0 from the contents of R0 of Bank2. MOV PSW,#10 MOV A,R0 MOV PSW,#00 SUBB A,R1 17.How the RS -232C serial bus is interfaced to TTL logic device ? The RS-232C signal voltage levels are not compatible with TTL logic levels. Hence for interfacing TTL devices to RS- 232C serial bus, level converters are used. The popularly used level converters are MC 1488 & MC 1489 or MAX 232.
Chapter 7 : Intel 8051 Microcontroller 18. List some of the features of 8096 microcontroller. a. The 8096 is a 16-bit microcontroller. b. The 8096 is designed to use in applications which require high speed calculations and fast I/O operations. c. The high speed I/O section of an 8096 includes a 16 bit timer, a 16 bit counter, a 4 input programmable edge detector, 4 software timers and a 6-output programmable event generator. d. It has 100 instructions, which can operate on bit,byte,word ,double words. e. The bit operations are possible and these can be performed on any bit in the register file or in the special function register. 19. What is HS0 of 8096? HS0: The High Speed Output unit (HS0) is used to trigger events at specific times with minimal CUP overhead. These events include : starting an A to D conversion, resetting Timer2, setting 4 software flags, and switching up to 6 output lines. 20. List the features of 8051 microcontroller? The features are *single_supply +5 volt operation using HMOS technology. *4096 bytes program memory on chip(not on 8031) *128 data memory on chip. *Four register banks. *Two multiple mode,16-bit timer/counter. *Extensive boolean processing capabilities. *64 KB external RAM size *32 bidirectional individually addressible I/O lines. *8 bit CPU optimized for control applications. 21 .Explain the operating mode0 of 8051 serial ports? In this mode serial enters &exits through RXD, TXD outputs the shift clock.8 bits are transmitted/received:8 data bits(LSB first).The baud rate is fixed at 1/12 the oscillator frequency.
Chapter 7 : Intel 8051 Microcontroller 22. Explain the operating mode2 of 8051 serial ports? In this mode 11 bits are transmitted(through TXD)or received (through RXD):a start bit(0), 8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).ON transmit the 9th data bit (TB* in SCON)can be assigned the value of 0 or 1.Or for eg:, the parity bit(P, in the PSW)could be moved into TB8.On receive the 9th d ata bit go in to the RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32or1/64 the oscillator frequency. 23. .Write A program to perform multiplication of 2 nos using 8051? MOV A,#data 1 MOV B,#data 2 MUL AB MOV DPTR,#5000 MOV @DPTR,A(lower value) INC DPTR MOV A,B MOVX @ DPTR,A 24. Write a program to mask the 0th &7th bit using 8051? MOV A,#data ANL A,#81 MOV DPTR,#4500 MOVX @DPTR,A LOOP SJMP LOOP 25.Write about CALL statement in 8051? There are two subroutine CALL instructions. They are *LCALL(Long CALL) *ACALL(Absolute CALL) Each increments the PC to the 1st byte of the instruction & pushes them in to the stack.
Chapter 7 : Intel 8051 Microcontroller 26. .Write about the jump statement? There are three forms of jump. They are LJMP(Long jump)-address 16 AJMP(Absolute Jump)-address 11 SJMP(Short Jump)-relative address 27. Write program to load accumulator ,DPH,&DPL using 8051? MOV A,#30 MOV DPH,A MOV DPL,A 28.Write a program to find the 2s complement using 8051? MOV A,R0 CPL A INC A 29.Write a program to add 2 8-bit numbers using 8051? MOV A,#30H ADD A,#50H 30.Write a program to swap two numbers using 8051? MOV A, #data SWAP A 31.Write a program to subtract 2 8-bit numbers &exchange the digits using 8051? MOV A,#9F MOV R0,#40 SUBB A,R0 SWAP A 32.Write a program to subtract the contents of R1 of Bank 0from the contents of R0 of Bank 2 using 8051? MOV PSW,#10 MOV A,R0 MOV PSW,#00 SUBB A,R1
Chapter 7 : Intel 8051 Microcontroller 33. What is an Interrupt? Interrupt is a signal send by an external device to the processor so as to request the processor to perform a particular task or work 34. What is program counter? How is it useful in program execution? The program counter keeps track of program execution. To execute a program the starting address of the program is loaded in program counter. The PC sends out an address to fetch a byte of instruction from memory and increments its content automatically. 35. Define stack Stack is a sequence of RAM memory locations defined by the programmer.

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Chapter 7 : Intel 8051 Microcontroller

Chapter 7 : Intel 8051 Microcontroller

Chapter 7 : Intel 8051 Microcontroller

Intel 8051 Microcontroller

CPU I/O Port

CPU Serial Port

Figure 1 : Block diagram of 8051

Chapter 7 : Intel 8051 Microcontroller Architecture of 8051 (* Theory to be include)

Figure 2 : Architecture of 8051

Figure 3: 8051 Memory Map

Chapter 7 : Intel 8051 Microcontroller

Lower 128 Bytes of Internal RAM

Upper 128 Bytes of Internal RAM

Chapter 7 : Intel 8051 Microcontroller

Table 8 displays the groups of priority. Bit Group

Chapter 7 : Intel 8051 Microcontroller ISR Structure

Figure 8 : Overview Of The Interrupt Service Routine

7.12.3 Power Management Implementation

Figure 9 : 8051 Unified Clock Domain Connection Diagram

Figure 10 : 8051 Power Management Connection Diagram

SM0 SM1 SM2 REN TB8 RB8 TI RI

Chapter 7 : Intel 8051 Microcontroller

Microprocessor based system requires Microcontroller more hardware.

TF0 : 000BH IE1 : 0013H TF1 : 001BH

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