Microelectronics

Wafers and Chips
FIGURE 13.1 (a) A 300-mm (11.8 in.) wafer with a large number of dies fabricated onto its surface. (b) Detail view of an Intel 45-nm chip including a 153 Mbit SRAM (static random access memory) and logic test circuits. (c) Image of the Intel Itanium2 processor; (d) Pentium processor motherboard. Source: Courtesy of Intel Corporation.
(a) (b)
(c)
(d)
Manufacturing Processes for Engineering Materials, 5th ed. Kalpakjian !Schmid 2008, Pearson Education ISBN No. 0-13-227271-7
Basic Fabrication Approach

Cross-section Silicon nitride p-type silicon (a) CVD SiO2 SiO2 p n+ (d) p+ n+ (e) SiO2 p n+ p+ n+ (f) SiO2 SiO2 p n+ p+ p (b) SiO2 Boron implant p+ Polysilicon p+ SiO2 p SiO2
(c)
Phosphorus or arsenic SiO2
Source
Al Gate Drain SiO2
n+
FIGURE 13.2 Cross-sectional views of the fabrication of a metal oxide semiconductor (MOS) transistor. Source: After R.C. Jaeger.
(a) Single-crystal growing
IC Fabrication Sequence
Internal diameter saw Silicon wafer Silicon ingot
(b) Wafer preparation
1
Silicondioxide layer Silicon nitride layer Silicon substrate Photoresist
Prepared silicon wafer Projected light Reticle (or mask) Lens
(c) Lithography/ Doping/Etching cycle
6
Metal connector
Similar cycle is repeated 2 to lay down metal links between transistors Patterns are projected repeatedly onto wafer New photoresist is spun on wafer, and steps 2 to 4 are repeated
5
All photoresist is removed Doped region
3
Exposed photoresist is removed Areas unprotected by photoresist are etched by gases or doped with ions
(d) Bonding
FIGURE 13.3 General fabrication sequences for integrated circuits.

(e) Packaging
(f) Testing
Clean Rooms
100,000 (3500) Total number of particles/ft3 equal to or larger than stated particle size 10,000 (350) 1000 (35) 100 (3.5) 10 (.35) 1 0.1 0.01 0.05
Cl as s Cl 10 as 0, 00 s Cl 10 as 0 ,0 (3 s Cl 00 10 50 as 0 0) (3 s 0 5 1 ( 0) 35 Cl 00 Cl as ) (3 as s .5 1 s ) 0 1 ( 0. (0 35 .0 35 ) )
0.1
0.5 1.0 5 10 Particle diameter (m)
100
FIGURE 13.4 Allowable particle size concentrations for different clean-room classes.
Silicon Crystallographic Structure
(a)
(b)
[001]
(110)
[001]
[001]
(111) [111]
[100] [010] (100) (c) [010] [110]
[100] [010]
[100]
FIGURE 13.5 Crystallographic structure and Miller indices for silicon. (a) Construction of a diamond-type lattice from interpenetrating face-centered cubic cells (one of eight penetrating cells shown). (b) The diamondtype lattice of silicon. The interior atoms have been shaded darker than the surface atoms. (c) Miller indices for a cubic lattice.
Finishing Operations on Silicon Ingot

Silicon Pulley ingot Silicon ingot
Diamondmetal bonded wheel Electroplated band saw (a) Internal diameter saw Silicon wafer Silicon ingot (c) Silicon ingot (d) (b)
Diamondmetal bonded wheel
FIGURE 13.6 Finishing operations on a silicon ingot to produce wafers. (a) and (b) Grinding of the end and cylindrical surfaces of a silicon ingot; (c) machining of a notch or at; (d) slicing of wafers; (e) end grinding of wafers; and (f) chemical-mechanical polishing of wafers.
Polishing pad
Silicon wafer Diamond edging wheel Slurry (e) (f)
Wafer Identication
45 Primary flat Secondary flat Primary flat
{111} n -type
{111} p -type
180 Secondary flat Primary flat 90 Primary flat
{100} n -type (a)
Secondary flat {100} p -type
{110} plane
{100} planes
{100} plane
FIGURE 13.7 Identication of single-crystal wafers of silicon. This identication scheme is common for 150 mm (6 in.) diameter wafers, but notches are more common for larger wafers.
Secondary flat 45 Primary flat
(b)
CVD and Oxide Growth

N2 Gas N2 Wafers Pressure sensor 3-zone furnace Pump
Heater
FIGURE 13.8 Schematic diagrams of a (a) continuous, atmosphericpressure CVD reactor and (b) low-pressure CVD reactor. Source: After S.M. Sze.
Exhaust (a)
Conveyor belt
Load door
Gas inlet (b)
Wafers
SiO2 surface Original Si interface SiO2 Silicon substrate
FIGURE 13.9 Growth of silicon dioxide, showing consumption of silicon.
Visible photons Air 0.5 mm eDirect write Resist
Electrons
Vacuum e-
Contact mask Resist
Lithography Techniques
FIGURE 13.10 Comparison of four different lithography techniques: (a) Photolithography, (b) electron-beam lithography, (c) X-ray lithography, and (d) ion-beam lithography.
Substrate Photolithography line-widths of 23 m (a) X-rays Air Proximity mask
Substrate Electron-beam lithography line-widths of 0.1 m (b) Ions
Air Resist Substrate
Vacuum Direct write Substrate Ion-beam lithography line-widths of 0.1 m (d)
Resist
X-ray lithography line-widths of 0.2 m (c)
Method Ultraviolet (Photolithography) Deep UV Extreme UV X-ray Electron beam Source: After P.K. Wright.
Wavelength (nm) 365 193 10-20 0.01-1 -
Finest feature size (nm) 350 190 30-100 20-100 80
TABLE 13.1 General characteristics of lithography techniques.

Spinning of Organic Coating

Application Photoresist Substrate Chuck 1. Dispense 2. Spread cycle Skin Liquid resist
Liquid resist spun out from beneath skin
Evaporation of solvent
3. Ramp-up
4. Final spin speed
FIGURE 13.11 Spinning of an organic coating on a wafer. (a) Liquid dispensed; (b) liquid is spread over the wafer surface by spinning at low speed; (c) speed is increased, developing a uniform coating thickness and expelling excess liquid; (d) evaporation of solvent at nal spin speed to obtain organic coating.
Wafer Stepping and Step-and-Scan

Light source exposes entire reticle Reticle with pattern Light source exposes line in reticle Reticle with pattern Reticle motion Stepper Step-and-scan optics
Wafer Exposed image Wafer motion (a) (b)
Wafer Exposed image
FIGURE 13.12 Schematic illustration of (a) wafer stepper technique for pattern transfer and (b) step-and-scan technique.
Lithography
UV radiation Photoresist Negative reticle UV radiation
SiO2
UV radiation 1 2
Positive reticle 3
Photoresist removed
SiO2 etched
Developed image
FIGURE 13.13 Pattern transfer by lithography. Note that the mask in Step 3 can be either a positive or a negative image of the pattern. Source: After W.C. Till and J.T. Luxon.
SCALPAL
Electron beam Interferometer Mask stage Scan Step x,y wafer Lens Aperture Stitching deflector Interferometer x,y mask
Wafer stage
Scan
Step
FIGURE 13.14 Schematic illustration of the SCALPEL process.
PDMS Stamp Production

PDMS Developed photoresist Cured PDMS stamp
Silicon substrate (a) (b) (c)
FIGURE 13.15 Production of a polydimethylsiloxane (PDMS) mold for soft lithography. (a) A developed photoresist is produced through standard lithography (see Fig. 13.13). (b) A PDMS stamp is cast over the photoresist. (c) The PDMS stamp is peeled off the substrate to produce a stamp. The stamp shown has been rotated to emphasize replication of surface features; the master pattern can be used several times. Source: After Y. Xia and G.M. Whitesides.
Soft Lithography
1. Prepare PDMS stamp 1. Prepare PDMS stamp Liquid polymer droplet Stamp Substrate 2. Fill cavities with polymer precursor 2. Press stamp against surface; apply drop of liquid polymer to end of stamp.
3. Press stamp against surface; allow precursor to cure
3. Remove excess liquid; allow polymer to cure
FIGURE 13.16 Soft lithography techniques. (a) Microtransfer molding (TM), and (b) micromolding in capillaries (MIMIC). Source: After Y. Xia and G.M. Whitesides.
4. Peel off stamp (a) 4. Peel off stamp (b)
Etch Rates
Etchant Wet etchants Concentrated HF (49%) 25:1 HF:H2 O 5:1 BHFb Silicon etchant (126 HNO3 :60H2 O:5NH4 F) Aluminum etchant (16H3 PO4 :1HNO3 :1HAc:2H2O) Titanium etchant (20 H2 O:1 H2 O2 :1HF) Piranha (50 H2 SO4 :1H2 O2 ) Acetone (CH3 COOH) Dry etchants CF4 +CHF3 +He, 450W SF6 +He, 100W SF6 m 125 W O2 , 400W Target material Silicon oxides Silicon oxides Silicon oxides Silicon Aluminum Titanium Cleaning o metals and organics Photoresist Silicon oxides Silicon nitride Thin silicon nitrides Ashing photoresist Polysilicon n+ 0 0 9 310 <1 1.2 0 Polysilicon, undoped 0 2 100 <1 0 SiO2 2300 9.7 100 9 0 12 0 Etch rate (nm/min)a Phosphosilicate glass, AlumSiN annealed inum 14 0.6 0.9 0.2 0 0.8 0 3600 150 440 170 <1 210 0 4.2 140 400 660 > 10 180 Titanium > 1000 > 1000 300 0 880 240 Photoresist (OCG820PR) 0 0 0 0 0 0 > 10
0 190 73 170 0
0 210 67 280 0
0 470 31 110 0
0 180 82 280 0
0 620 61* 140 0
0 > 1000 0
0 > 1000 69 > 1000 0
> 4000 220 310 340
Notes: a Results are for fresh solutions at room temperature unless otherwise noted. Actual etch rates will vary with temperature and prior use of solution, area of exposure of lm, other materials present, and lm impurities and microstructure. b Buered hydrouoric acid, 33% NH4F and 8.3% HF by weight.
TABLE 13.2 Comparison of etch rates.

Etching Operations
Wet etching HF:HNO3 :CH3 COOH 25 1-20 Low 10-30 No KOH 70-90 0.5-2 100:1 <1 10 Yes Ethylene-diamine 115 0.75 35:1 0.1 0.2 Yes pyrochatechol (EDP) N(CH3 )4 OH (TMAH) 90 0.5-1.5 50:1 < 0.1 < 0.1 Yes Dry (plasma) etching SF6 0-100 0.1-0.5 200 10 No SF6 /C4 F8 (DRIE) 20-80 1-3 200 10 No Source: Adapted from N. Maluf, An Introduction to Microelectromechanical Systems Engineering, Artech House, 2000.
Temperature ( C)
Etch rate (m/min)
{111}/{100} selectivity
Nitride etch rate (nm/min)
SiO2 etch rate nm/min)
p++ etch stop
TABLE 13.2 General characteristics of silicon etching operations.
Etching Directionality
Undercut Mask layer {111} face 54.7 Etch material (e.g. silicon) Etch front (a) Etch front Final shape (b) Etch front (c)
Etch rate (m/hour)
FIGURE 13.17 Etching directionality. (a) Isotropic etching: etch proceeds vertically and horizontally at approximately the same rate; note the signicant mask undercut. (b) Orientationdependent etching (ODE): etch proceeds vertically, terminating on {111} crystal planes, with little mask undercut. (c) Vertical etching: etch proceeds vertically, with little mask undercut. Source: Courtesy of K.R. Williams. FIGURE 13.18 Etch rates of silicon at different crystallographic orientations, using ethylene-diamine/pyrocatechol-in-water as the solution. Source: After H. Seidel, et al., J. Electrochemical Society, 1990, pp. 3612-3626.
102
120
100
Temperature (C) 80 60
40
101
<110> <100>
100
10-1 <111> 10-2 2.5 2.7 2.9 1/T (3 10-3 K-1) 3.1 3.3
Boron Etch Stop

Si 1. Oxidation SiO2 SiO2 p+ Si 2. Lithography and development Membrane SiO2 Si 3. Boron diffusion SiO2
Si Orifice 4. Anisotropic etching
Si Orifice
SiO2
5. Stripping and reoxidation
FIGURE 13.19 Application of a boron etch stop and back etching to form a membrane and orice. Source: After I. Brodie and J.J. Murray.
Processing step 1.
Cross section
Description
Silicon Oxide
Sample of n-type silicon
2.
n Photoresist n UV light Mask
Grow silicon dioxide by oxidation
Processing Doped Silicon
3.
Apply photoresist
4.
Expose photoresist using appropriate lithographic mask
5.
Develop photoresist
6.
Etch silicon dioxide
7.
Remove photoresist
8. n
Implant boron
p 9. n Remove silicon dioxide
FIGURE 13.20 Sequence in processing of a p-type region in n-type silicon.
Dry Etching
Ion Neutral Volatile product
(a)
(b)
Neutral Ion
Volatile product
Neutral Ion
Volatile product
Inhibitor (c) (d)
FIGURE 13.21 Machining proles associated with different dry-etching techniques: (a) sputtering, (b) chemical, (c) ion-enhanced energetic, and (d) ion-enhanced inhibitor. Source: After M. Madou.
Reactive Plasma Etching

1. Generation of etchant species 6. Diffusion into bulk gas 4. Reaction 5. Desorption
2. Diffusion to surface 3. Adsorption
Film (a) (b)
(c)
(d)
FIGURE 13.22 (a) Schematic illustration of reactive plasma etching. Source: After M. Madou. (b) Example of deep reactive ion etched trench; note the periodic undercuts, or scalloping. (c) Near vertical sidewalls produced through DRIE with an anisotropic etching process. (d) An example of cryogenic dry etching, showing a 145 m deep structure etched into Si using a 2.0 m thick oxide masking layer. The substrate temperature was -140C during etching. Source: for (b) to (d): R. Kassing and I.W. Rangelow, University of Kassel, Germany.
Hole Proles
Scalloping (a) (b) (c) (d) (e) (f)
FIGURE 13.23 Various types of holes generated from a square mask in (a) isotropic (wet) etching, (b) orientation-dependent etching (ODE), (c) ODE with a larger hole, (d) ODE of a rectangular hole, (e) deep reactive ion etching, and (f) vertical etching. Source: After M. Madou.
IC Connections
Level 0Interconnects Level 1DIP leads Level 2Printed circuit board
Level 3Busses
Level 4Cable harness
Level Level 0 Level 1 Level 2 Level 3 Level 4 Level 5
Element example Transistor within an IC ICs, other discrete components IC packages Printed circuit boards Chassis or box System, e.g., computer
Interconnection method IC metallization Package leads or module interconnections Printed circuit board Connectors (busses) Connectors/cable harnesses
FIGURE 13.24 Connections between elements in the hierarchy for integrated circuits.
Interconnects & Inspection

Via Second-level metal Interlevel dielectric n+
SiO2
Contact
First-level metal
SiO2 Si
FIGURE 13.25 (a) Scanning electron microscope photograph of a two-level metal interconnect; note the varying surface topography. (b) Cross-section of a two-level metal interconnect structure. Source: After R.C. Jaeger.
(a)
(b)
FIGURE 13.26 A probe (top center) checking for defects in a wafer; an ink mark is placed on each defective die. Source: Intel Corp.
Wire Bonds
(a)
(b)
(c)
FIGURE 13.27 (a) SEM photograph of wire bonds connecting package leads (left-hand side) to die bonding pads. (b) and (c) Detailed views of (a). Source: Courtesy of Micron Technology, Inc.
Thermosonic Ball-and-Stitch Process

Wire clamp Gold wire Bonding tip Arc generator Die 1. Arcing forms gold ball 2. Ball bonds while applying heat and/or ultrasonic vibration Force Gold wire
Bond pad Die Package lead
3. Position tip over package lead
Wire loop
Force
Wire loop
Die
Package lead
Die
Package lead 5. Break wire
4. Stitch bond on lead
FIGURE 13.28 Schematic illustration of the thermosonic ball and stitch process. Source: After N. Maluf.
Summary of Packages
Package Through-hole mount Dual in-line Single in-line Zigzag in-line Quad in-line package Surface mount Small-outline IC Thin small-outline package Small-outline J-lead Plastic leaded chip carrier Thin quad at pack Abbreviation DIP SIP ZIP QUIP SOIC TSOP SOJ PLCC TQFP Pins min. max. 8 11 16 16 8 26 24 18 32 64 40 40 64 28 70 32 84 256 Description Two in-line rows of leads. One in-line row of leads. Two rows with staggered leads. Four in-line rows of staggered leads. Small package with leads on two sides. Thin version of SOIC. Same as SOIC, with leads in a J-shape. J-shaped leads on four sides. Wide but thin package with leads on four sides.
TABLE 13.4 Summary of molded-plastic IC packages.
IC Packages
Ceramic cover Molding compound Monolithic circuit die Bond wires Eutectic preform Bonding pad (typical 10 places)
5 43
Spot plate Lead frame Die Die-support paddle
Glass seal (typical for 10 leads)
Bonding wire Ceramic package base (b)
78
9 10
(a)
Solder
Signal/ ground via
Wire bond
Mold compound
Die pad
Plated copper conductor
Through hole
Butt joint
Crow!s foot (c)
Gull wing
Solder mask
BT epoxy PCB
IC
Thermal/ ground via (d)
Solder bump
FIGURE 13.29 Schematic illustration of various IC packages: (a) dual in-line (DIP), (b) ceramic at pack, (c) common surface-mount congurations, and (d) ball-grid array (BGA). Source: After R.C. Jaeger, A.B. Glaser, and G.E. Subak-Sharpe.
Flip Chips
IC
(a)
(b)
(c)
(d)
FIGURE 13.30 Illustration of ip-chip technology. (a) Flip-chip package with solder-plated metal balls and pads on the printed circuit board, (b) ux application and placement, (c) reow soldering, and (d) encapsulation. Source: After P.K. Wright.
Printed Circuit Boards

DIP package Insertion hole Buried via hole Surface signal track
Solder
Internal signal track Insulation layers
Lead Surface mount land
Partially buried via hole
Gull wing surface mount lead removed for clarity Via hole
Internal signal track
FIGURE 13.31 Printed circuit board structures and design features.
Example: Accelerometer
Stationary polysilicon fingers Spring (beam) Suspended inertial mass Direction of acceleration
C1 Anchor to substrate C2
FIGURE 13.32 The Analog Devices ADXL-50 accelerometer. This MEMS-based product contains a surface-micromachined sensor, on-chip excitation, self-test, and signal-controlling circuitry. The schematic illustration shows the structure of the suspended mass. The entire chip measures 0.500 mm x 0.625 mm. Source: Courtesy of Analog Devices, Inc.
Bulk and Surface Micromachining

Substrate (e.g. n-type Si) Diffused layer (e.g. p-type Si) Non-etching mask (e.g. silicon nitride) Free-standing cantilever (111) planes
1.
2.
3.
FIGURE 13.33 Schematic illustration of the steps in bulk micromachining. (1) Diffuse dopant in desired pattern, (2) deposit and pattern masking lm, and (3) orientationdependent etch, leaving behind a freestanding structure. Source: After K.R. Williams.
Phosphosilicate glass (spacer layer)
Polysilicon
FIGURE 13.34 Schematic illustration of the steps in surface micromachining. (1) deposition of a phosphosilicate glass (PSG) spacer layer, (2) etching of spacer layer, (3) deposition of polysilicon, (4) etching of polysilicon, and (5) selective wet etching of PSG, leaving the silicon substrate and the deposited polysilicon unaffected.
Silicon (a) Step 1 (b) Step 2 (c) Step 3
Suspended cantilever
(d) Step 4
(e) Step 5
Bulk & Surface Micromachining Example

Film 2 mm thick
Cavity 0.1 mm across
FIGURE 13.35 A microlamp produced by a combination of bulk and surface micromachining processes. Source: K.R. Williams, Agilent Technologies.
Stiction after Wet Etching

Polysilicon beam Spacer oxide Rinse water
Substrate 1. 2.
3.
FIGURE 13.36 Stiction after wet etching. (1) Unreleased beam, (2) released beam before drying, and (3) released beam pulled to the surface by capillary forces during drying. Once contact is made, adhesive forces prevent the beam from returning to its original shape. Source: After B. Bhushan.
Fabrication of Micromirror
FIGURE 13.37 (a) SEM image of a deployed micromirror and (b) detail of the micromirror hinge. Source: Sandia National Laboratories.
(a)
(b)
Spacer layer 1
Poly1
Spacer layer 2
FIGURE 13.38 Schematic illustration of the steps in manufacturing a hinge. (1) Deposition of a phosphosilicate glass (PSG) spacer layer and polysilicon layer (see Fig. 13.34), (2) deposition of a second spacer layer, (3) selective etching of the PSG, (4) deposition of polysilicon to form a staple for the hinge, and (5) after selective wet etching of the PSG, the hinge can rotate.
Silicon (a) Step 1 Poly2 (b) Step 2 (c) Step 3
(d) Step 4
(e) Step 5
SCREAM Process
Photoresist Oxide Silicon
1. Deposit oxide and photoresist
2. Lithography and oxide etching
3. Silicon etching
Suspended beam
Sharp tip
4. Coat sidewalls with PECVD oxide
5. Remove oxide at bottom and etch silicon
6. Plasma etching in SF6 to release structures
FIGURE 13.39 Steps involved in the SCREAM process. Source: After N. Maluf.
SIMPLE
Photoresist
Oxide
Suspended feature
pn+ pSilicon 2. Lithography and oxide etching 3. Plasma etching p+ doped silicon
pp4. Isotropic etching of n- doped silicon
n+
1. Deposit oxide and photoresist on layered substrate
FIGURE 13.40 Schematic illustration of silicon micromachining by the single-step plasma etching (SIMPLE) process.
Glass reticle Oxide Mask Resist Oxide Silicon Silicon Silicon Embedded cavity 1. Expose resist 2. Etch cavity 3. Silicon-diffusion bonding Silicon
Silicon Fusion Bonding & DRIE
Resist CMOS circuits Suspended beam
4. Fabricate CMOS
5. Expose resist (a)
6. Etch (DRIE) beam
FIGURE 13.41 (a) Schematic illustration of silicon fusion bonding combined with deep reactive ion etching to produce large suspended cantilevers. Source: After N. Maluf. (b) A micro-uid-ow device manufactured by applying the DRIE process to two separate wafers and then aligning and silicon fusion bonding them together. Afterward, a Pyrex layer (not shown) is anodically bonded over the top to provide a window for observing uid ow. Source: After K.R. Williams.
100 m (b)
Example: Inkjet Printer

Ink Bubble
Heating element 1. Actuation 2. Droplet formation Satellite droplets
3. Droplet ejection
4. Liquid refills
FIGURE 13.42 Sequence of operations of a thermal ink-jet printer. (1) Resistive heating element is turned on, rapidly vaporizing the ink and forming a bubble. (2) Within ve microseconds, the bubble has expanded and displaced liquid ink from the nozzle. (3) Surface tension breaks the ink stream into a bubble, which is discharged at high velocity. The heating element is turned off at this time, so that the bubble collapses as heat is transferred to the surrounding ink. (4) Within 24 microseconds, an ink droplet (and undesirable satellite droplets) are ejected, and surface tension of the ink draws more liquid from the reservoir. Source: From F.G. Tseng, Microdroplet Generators, in M. Gad-el-hak (ed.), The MEMS Handbook, CRC Press, 2002.
Phosphosilicate glass Silicon nitride
Silicon
FIGURE 13.43 The manufacturing sequence for producing thermal ink-jet printer heads. Source: From F.G. Tseng, Microdroplet Generators,' in M. Gad-el-hak (ed.), The MEMS Handbook, CRC Press, 2002.
Silicon dioxide 1. Silicon nitride deposition 2. Wet etch manifold, remove PSG Aluminum interconnect 3. Wet etch, enlarge chamber
Tantalum heater
4. Heater and interconnection formulation
5. Laser nozzle
Synchrotron radiation Mask membrane Absorber structure PMMA Resist Substrate 1. Irradiation Plastic Electrically conductive substrate 2. Mold filling 1. Mold insert (from LIGA) Mold cavity
LIGA
PMMA Structure
2. Developing
Metal PMMA Resist 3. Mold removal
Plastic structure as mold or final product
3. Electroforming 4. Second electroforming
Metal from electroforming or ceramic from slip casting
Final product (a)
Mold insert 5. Final product (b)
Metal or ceramic structure
FIGURE 13.44 The LIGA (lithography, electrodeposition, and molding) technique. (a) Primary production of a metal product or mold insert. (b) Use of the primary part for secondary operations, or replication. Source: Courtesy of IMM Institute fr Mikrotechnik.
4. Resist removal
Electroforming & Mold Production

500 m 100 m
FIGURE 13.45 (a) Electroformed nickel structures. (b) Detail of nickel lines and spaces. Source: After T. Christenson, The MEMS Handbook, CRC Press, 2002.
(a) (b)
TABLE 13.5 Comparison manufacturing techniques.
of
micromold
Production technique LIGA Laser machining EDM Aspect ratio 10-50 10 up to 100 Surface roughness < 50 nm 100 nm 0.3-1 m Accuracy < 1 m 1-3 m 1-5 m Mask Required? Yes No No Maximum height 1-500 m 200-500 m m to mm Source: L. Weber, W. Ehrfeld, H. Freimuth, M. Lacher, M. Lehr, and P. Pech, SPIE Micromachining and Microfabrication Process Technology II, Austin, TX, 1996.
10 ksi
Rare-earth powder and binder PMMA mold Sacrificial layer (copper) Substrate (alumina) 1. Press 35 kOe 2. Lap
Rare-Earth Magnet Production
3. Magnetize
4. Release
(a) (b)
FIGURE 13.46 Fabrication process used in producing rare-earth magnets for microsensors. Source: After T. Christenson, Sandia National Laboratories.
Energy product (Gauss-Oersted 106 ) 0.20 0.65 1.4 1.0 6.5 40 9
Material Carbon steel 36% cobalt steel Alnico I Vicalloy I Platinum-cobalt Nd2 Fe14 B, fully dense Nd2 Fe14 B, bonded
FIGURE 13.47 SEM images of Nd2Fe{14}B permanent magnets. Powder particle size ranges from 1 to 5 m; the binder is a methylenechloride resistant epoxy. Mild distortion is present in the image, due to magnetic perturbation of the imaging electrons. Maximum-energy products of 9 MGOe have been obtained with this process. Source: T. Christenson, in Gad-el-Hak, (ed.), The MEMS Handbook, CRC Press, 2002.
TABLE 13.6 Comparison of properties of permanentmagnet materials.

Wafer-Scale Diffusion Bonding

Alumina substrate Sacrificial layer Alignment gauge pin Nickel substrate (structural)
Diffusion bond and release
All-nickel structure (a) (b)
FIGURE 13.48 (a) Multilevel MEMS fabrication through wafer-scale diffusion bonding. (b) A suspended ring structure, for measurement of tensile strain, formed by two-layer waferscale diffusion bonding. Source: After T. Christenson, Sandia National Laboratories.
HEXSIL Process
1. Etch deep in silicon wafer 6. Deposit electroless nickel
2. Deposit sacrificial oxide
7. Lap and polish to oxide layer
3. Deposit undoped poly
8. HF etch release and mold ejection 9. Go to step 2: Repeat mold cycle 4. Deposit in-situ doped poly Wafer Sacrificial oxide Undoped poly Doped poly 5. Blanket etch planar surface layer to oxide Electroless nickel
FIGURE 13.49 Illustrations of the HEXagonal honeycomb structure, SILicon micromachining, and thin-lm deposition (HEXSIL process).
HEXSIL Example
(a)
(b)
FIGURE 13.50 (a) SEM image of micro-scale tweezers, used in microassembly and microsurgery. (b) Detailed view of the tweezers. Source: Courtesy of MEMS Precision Instruments.
Instant Masking
Developed mask (elastomer) + Anode Elastomeric insulator Selectively deposited material
Substrate 1.
Plating bath 2.
Substrate
Substrate 3.
FIGURE 13.51 The instant masking process: (1) bare substrate, (2) during deposition, with the substrate and instant mask in contact, and (3) the resulting pattern deposit. Source: After A. Cohen, MEMGen Corporation.
Carbon Nanotubes
Graphite structure Armchair Zigzag Chiral
FIGURE 13.52 Forms of carbon nanotubes: armchair, zigzag, and chiral. Armchair nanotubes are noteworthy for their high electrical conductivity, whereas zigzag and chiral nanotubes are semiconductors.
Mirror Mirror -10 Hinge Mirror +10
Mirror support post Landing tips Yoke Torsion hinge Hinge support post Address electrode Electrode support post
Landing sites Metal 3 address pads Bias/Reset bus To SRAM (a) (b) Yoke Landing tip CMOS substrate
Case Study: Digital Micromirror Device

FIGURE 13.53 The Texas Instruments Digital Pixel Technology (DPTTM) Device. (a) Exploded view of a single digital micromirror device (DMDTM); (b) view of two adjacent DMD pixels; (c) images of DMD arrays, with some mirrors removed for clarity; each mirror measures approximately 17 m (670 in.) on a side; (d) a typical DPT device, used for digital projection systems, high denition televisions, and other image display systems. The device shown contains 1,310,720 micromirrors and measures less than 50 mm (2 in.) per side. Source: Texas Instruments Corp.
(c)
(d)
Fabrication Sequence for Case Study

CMOS Metal-3 level Sacrificial spacer-1 CMP oxide Hinge Yoke Hinge post Silicon substrate with CMOS circuits 1. Pattern spacer-1 layer 4. Etch yoke and strip oxide
Mirror Oxide hinge mask Hinge metal
Mirror mask
Spacer-2
2. Deposit hinge metal; deposit and pattern oxide hinge mask
5. Deposit spacer-2 and mirror
Mirror Yoke metal Oxide mask Yoke
Mirror post
Hinge
FIGURE 13.54 Manufacturing sequence for the Texas Instruments DMD device.
3. Deposit yoke and pattern yoke oxide mask 6. Pattern mirror and etched sacrificial spacers
Ceramic Flat Package for DMD

Hermetic optical window (Corning 7056) Glass-to-metal fused seal Seam weld Ceramic header DMD Gold wire bonds Kovar frame Kovar seal ring Zeolite getters
Heat sink
FIGURE 13.55 Ceramic at package construction used for the DMD device. See also Fig. 13.29.

Microelectronics

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Wafers and Chips

Basic Fabrication Approach

Phosphorus or arsenic SiO2

Al Gate Drain SiO2

(a) Single-crystal growing

Internal diameter saw Silicon wafer Silicon ingot

(b) Wafer preparation

Prepared silicon wafer Projected light Reticle (or mask) Lens

(c) Lithography/ Doping/Etching cycle

FIGURE 13.3 General fabrication sequences for integrated circuits.

0.5 1.0 5 10 Particle diameter (m)

Silicon Crystallographic Structure

[100] [010] (100) (c) [010] [110]

Finishing Operations on Silicon Ingot

Diamondmetal bonded wheel

Silicon wafer Diamond edging wheel Slurry (e) (f)

180 Secondary flat Primary flat 90 Primary flat

{100} n -type (a)

Secondary flat {100} p -type

Secondary flat 45 Primary flat

CVD and Oxide Growth

Gas inlet (b)

SiO2 surface Original Si interface SiO2 Silicon substrate

FIGURE 13.9 Growth of silicon dioxide, showing consumption of silicon.

Visible photons Air 0.5 mm eDirect write Resist

Contact mask Resist

Substrate Photolithography line-widths of 23 m (a) X-rays Air Proximity mask

Substrate Electron-beam lithography line-widths of 0.1 m (b) Ions

Air Resist Substrate

Vacuum Direct write Substrate Ion-beam lithography line-widths of 0.1 m (d)

X-ray lithography line-widths of 0.2 m (c)

Wavelength (nm) 365 193 10-20 0.01-1 -

Finest feature size (nm) 350 190 30-100 20-100 80

TABLE 13.1 General characteristics of lithography techniques.

Spinning of Organic Coating

Liquid resist spun out from beneath skin

4. Final spin speed

Wafer Stepping and Step-and-Scan

Wafer Exposed image Wafer motion (a) (b)

Wafer Exposed image

FIGURE 13.14 Schematic illustration of the SCALPEL process.

PDMS Stamp Production

Silicon substrate (a) (b) (c)

3. Press stamp against surface; allow precursor to cure

3. Remove excess liquid; allow polymer to cure

0 620 61* 140 0

0 > 1000 69 > 1000 0

> 4000 220 310 340

TABLE 13.2 Comparison of etch rates.

Etch rate (m/min)

Nitride etch rate (nm/min)

SiO2 etch rate nm/min)

p++ etch stop

TABLE 13.2 General characteristics of silicon etching operations.

Etch rate (m/hour)

Boron Etch Stop

Si Orifice 4. Anisotropic etching

5. Stripping and reoxidation

Sample of n-type silicon

n Photoresist n UV light Mask

Grow silicon dioxide by oxidation

Processing Doped Silicon

Expose photoresist using appropriate lithographic mask