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Direct Digital-Frequency Synthesis by Analog Interpolation

Alistair McEwan, Member, IEEE, and Steve Collins, Member, IEEE
AbstractA highly compact 9-bit CMOS direct digital synthesizer without read-only memory that consumes 8 W/MHz is described. The circuit is based upon a small nonlinear array of six current sources and six current switches. This array converts an analog voltage that represents the signal phase to an output current that represents the corresponding amplitude. Measurement results show that the resulting 3.3-V 0.35- m system is robust to mismatch and capable of generating a signal with a spurious free dynamic range as good as 48 dBc with a circuit area of 0.0085 mm2 . This level of performance and the compactness of the analog circuit make it an attractive starting point for the arrays of frequency synthesizers that will be needed in a range of instrumentation systems. Index TermsROM-less direct digital-frequency synthesis (DDFS) instrumentation.
Fig. 1. New DDFS architecture showing the accumulator on the left. The output from the accumulator forms the input to the digital circuits needed to exploit the half-wave symmetry of the output wave. The output from this circuit is converted to an analog voltage that represents the instantaneous phase of the signal by a linear DAC. Finally, this analog signal forms the input to a nonlinear interpolating circuit whose output current represents the amplitude corresponding to the instantaneous phase.

I. INTRODUCTION CONVENTIONAL direct digital-frequency synthesis (DDFS) architecture consists of a large overowing accumulator to generate an instantaneous digital phase. This digital phase word then forms the input to a ROM look-up table, which converts the phase input to the corresponding amplitude. Finally, a digital-to-analog converter (DAC) converts the digital amplitude word to an equivalent analog value [1]. The performance of this type of DDFS architecture, particularly its power consumption, is often limited by the ROM. Several techniques that employ additional digital circuitry to reduce the size of the ROM and hence, the power consumption, yet achieve a particular maximum output frequency and spectral purity have therefore been developed [2][5], and a good summary is given by Vankka et al. [6] and Langlois and Al-Khalili [7]. The trend to reduce the size of the ROM has naturally led to the development of DDFS systems in which phase-to-amplitude conversion is performed without resorting to a ROM. One approach to designing a ROM-less DDFS system is to simply calculate the digital amplitude corresponding to a digital phase [8]. Alternatively, the functions of the ROM and the DAC in the conventional architecture can be combined within a nonlinear DAC [9][11]. This brief describes a more compact DDFS architecture based on the nonlinear interpolation previously presented in [9] and
Manuscript received March 3, 2006; revised May 10, 2006. This work was supported by the EPSRC under Grant GR/N18048. This paper was recommended by Associate Editor S. Callegari. A. McEwan was with the Department of Engineering Science, University of Oxford, Oxford OX1 3PJ, U.K. He is now with the Medical Physics and Bioengineering, University College London, London WC1E BT, U.K. (e-mail: a.mcewan@ucl.ac.uk). S. Collins is with the Department of Engineering Science, University of Oxford, Oxford OX1 3PJ, U.K. (e-mail: collins@robots.ox.ac.uk). Digital Object Identier 10.1109/TCSII.2006.882349

[10]. The interpolation technique used here is similar to that used in an interpolating or folding ash analog-to-digital converter (ADC). This architecture is based upon a simple analog circuit that converts an input voltage that represents the phase of the signal to an output current that represents the amplitude of the signal. Simulation results indicate that the spurious-free dynamic range (SFDR) of the output signal from the new architecture with only six current cells can be as good as 50 dBc. Instrumentation systems commonly use frequency synthesis as a standard reproducible source that can be used to guarantee the accuracy of a measurement. One of the advantages of DDFS in instrumentation is its good frequency resolution, which allows ne trimming or calibration to remove variations in the synthesizer itself or in the rest of the measurement system. This level of performance together with the simplicity and compactness of the analog circuit makes the new architecture attractive for generating the stimulus for resonant micromechanical sensors, which require an SFDR of better than 40 dB [12], and the electric elds needed for noncontact sorting of particles using dielectrophoresis, which require an SFDR of better than 30 dB [13], [14]. The electric eld may also be used to identify or image biological particles and tissues via their impedance spectra [15], [16] with sinusoidal signals with an SFDR of better than 40 dBc. In these instrumentation systems, the output frequency requirement spans from dc to 1 MHz. II. PROPOSED ARCHITECTURE A schematic diagram of the proposed new DDFS architecture is shown in Fig. 1. As in a conventional system, this architecture contains an accumulator to calculate the digital word that represents the instantaneous phase of the output signal. The most

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Fig. 2. Simple three-transistor circuits, which form the basis of the interpolating circuit.

signicant bits of the output from the accumulator are then used to determine the phase of the output signal. The rst stage in this process is to use the most signicant bit to exploit the half-wave symmetry of the output to minimize the size of the circuits that are needed to transform this digital word into its corresponding analog amplitude. Unlike other architectures, the digital output from this block then forms the input to a linear DAC, which is referred to as the phase DAC. The output from this circuit is an analog voltage that represents the phase of the signal. Finally, this voltage forms the input to the interpolating circuit that converts the input phase to the output amplitude. To understand the operation of the interpolating circuit, consider the circuit shown that acts in Fig. 2. This circuit consists of a MOSFET as a constant-current source connected to a pair of MOSFETs and , which act as a differential input. If the differential input devices in the circuit are well matched, all the transistors , then the output curare operating in saturation, and rent from the circuit can be calculated using

Fig. 3. System used to convert an input phase voltage to an output current that represents the corresponding amplitude.

the half-wave symmetry of a sinusoidal output, the interpolating circuit only needs to represent the output signal over the range of 0 . Thus, to ensure that the six current sources represent half a period, the bias current of each current cell must be (4) (5) (6) (7) (8) (9) is the current that represents the amplitude of the where output signal. The quarter-wave symmetry of the cosine wave ) means that , , and . Since (about the reference voltages are equally spaced over the range of input voltages, then to accommodate the different bias current values, the parameter for the input devices in each current cell must is the same in each current cell. be chosen to ensure that Then, the only undetermined parameter that can control the performance of the interpolating circuit is the total output current, and the which will determine the relationship between differential input voltage needed to saturate the output from each circuit. III. CIRCUIT SIMULATIONS The optimum total output current and the corresponding performance of the interpolating circuit were determined by simulating the circuit in Fig. 3 using the device parameters for

(1) However, if , then , or if , . This saturation of the output current from the then can be exploited to convert circuit in Fig. 2 to either 0 or an input phase voltage to the corresponding amplitude. In the circuit in Fig. 3, this is achieved by connecting six circuits in parallel. Each circuit receives an input voltage that represents the instantaneous phase of the output signal; however, each of the six circuits has a different reference voltage. These reference , and the voltages are chosen to have uniform spacing and given by input voltage must range between (2) (3) This choice of reference voltages and input-voltage range means that as the input voltage increases from to , each pair of differential devices successively steers their associated current toward the output node. Since the system exploits

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an 0.35- m CMOS process. To determine the transistor sizes and reference voltages for this circuit, the following requirements need to be considered: The voltage supply is limited to 3.3 V. Within this voltage range, a saturated current source and differential input and output voltage swing must be allocated. With this in mind, the circuit was designed to operate with a gatesource voltage of approximately 1 V for the MOSFETs used as current sources. Then, to ensure that these current sources remain saturated, the minimum input voltage to this circuit should be approximately 1 V. The minimum difference between the reference voltages of adjacent devices was then chosen to be 200 mV. Once the various voltage levels had been determined, the next stage of the design was to use information provided by the circuit manufacturer to determine the dimensions of the devices in the interpolating circuit. A critical criterion throughout this design process was to try to achieve a high yield of working circuits despite both the process and parameter variations that occur in any manufacturing process. When MOSFETs are used to create constant-current sources with different output currents, it is good practice to use several unit MOSFET current sources acting in parallel within each current to create a ratio of output currents that is robust to process variations. Simulations suggested that the SFDR of the output signal could be maintained if 4, 11, and 15 1- m-wide and 10- m-long MOSFETs are used as the unit current sources to create the three different bias currents that are needed in the interpolating circuit. In addition, to scale the transconductance parameter of the input transistors to be proportional to the bias current in each circuit, different sizes of the input transistor are required. All the input transistors were designed to be 3.5 m long, and the three different widths of the devices used with the three different bias currents were 4.05, 11.5, and 16 m. The simulation results from the circuit with these device sizes and bias voltages are shown in Fig. 4. These results show that is too low, the output from each cell saturates before when its neighboring cell starts to contribute to the output. The resulting ripples on the output amplitude reduce the SFDR of the signal. In contrast, at high bias voltages, the input-voltage range is too small to saturate the output of any of the current sources. All six circuits are then effectively operating in a linear regime, and the output resembles a triangular wave. As shown in the central panel of Fig. 4, between these two extremes, there is a range of bias voltages between 0.85 and 0.9 V for this particular circuit, which gives the best approximation to a sinusoidal output. In this bias range, the SFDR of the output is 52 dBc. Furthermore, this creditable performance has been achieved using a simple circuit, which for the target 0.35- m process, occupies only 8400 m (Fig. 5), which is less than the area that is needed for a bond pad. The output frequency may be changed by increasing either the frequency of the clock or the phase word stored in the accumulator, i.e., PW (10)

Fig. 4. Simulation results showing the output waveform for three current source bias voltages.

cumulator and XOR gates implemented in Verilog and a phase DAC with a settling time of 10 ns were used to simulate the change of the output frequency. As the phase word is increased, the dominant harmonics of the clock alias spur began to con. For structively interfere with the dominant harmonics of example, there was degradation in SFDR to 48 dBc when the MHz phase word was increased to 51 with MHz , while at MHz and PW MHz , there was no degradation in SFDR. Therefore, inby increasing the phase word degrades the SFDR creasing by increasing the clock frequency. more than increasing This is expected, as increases in the phase word cause larger voltage changes at the gates of the current switches as well as faster changes, while increases in the clock rate only increase the frequency of changes and not the magnitude. With MHz, the SFDR was maintained at 50 dBc up to MHz. 1 MHz and degraded to 40 dBc by IV. MEASUREMENT RESULTS The simulated interpolating circuit has been manufactured using the AMS 0.35- m CSX process. To test the performance of these circuits, an analog input voltage that represents the phase of the output signal was generated using one channel of an Agilent 4155B semiconductor parameter analyzer. A second channel generated the gate bias voltage for all the unit current sources, while another channel was used to measure the output current from the circuit. The various reference voltages were generated using a PowerDAQ PDIO-210 that was supplied by United Electronic Industries and controlled by the same Agilent VEE software used to control the Agilent 4155B. The output data for different current source bias voltages were transferred from the Agilent 4155B into a personal computer (PC). Matlab was then used to calculate the spectrum of each response and to determine the magnitude of the dominate spurs in the spectrum. Results from one circuit at different bias voltages (Fig. 6) shows

where PW is the phase word stored in the accumulator and is the number of phase bits, 9 of which were used in this design to ensure that the SFDR was not limited by phase resolution. Mixed-signal simulations of the circuit with a phase ac-

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Fig. 7. Relative power of the dominant spurious output of all the available sample circuits at different current source bias voltages. Fig. 5. Microphotograph of the manufactured chip. To minimize bias-voltage drop, the entire circuit was covered in the top metal layer, which obscures the transistors from view; however, the photo compares the size of the circuit to a typical bond pad, illustrating the compactness of the circuit.

Fig. 6. Relative output power of several important harmonics of the output frequency at different current source bias voltages.

that at low bias voltages, the dominant spur is the fth harmonic. As the bias voltage increases, the SFDR of the output improves as the power in the fth harmonic reduces. However, eventually, a different harmonic becomes dominant, and the SFDR of the system is maximum at an optimum bias voltage. For the particular circuit whose results are shown in Fig. 6, the optimum bias point occurs at a voltage that is slightly less than 0.9 V, and at this bias voltage, the SFDR of the output signal is better than 50 dBc. Results from all the sample circuits provided by the manufacturer are shown in Fig. 7. As expected, differences between the effects of device mismatch in different circuits mean that each circuit has a slightly different response. Despite these variations, the trends in the dominant harmonic shown in Fig. 7 are quite similar for different circuits. The largest differences between the circuits occur in the optimum bias-voltage range of 0.81.0 V. In this range, a combination of process and parameter variations means that the dominant harmonic varies between circuits. Most dramatically, the spectral purity of the output of two

of the circuits is limited by a larger-than-expected second-harmonic component caused by parameter variations within these circuits. Although this suggests that further improvements to the design could be made, the overall conclusion from these results is that these circuits have an estimated yield of 70% for systems with an SFDR of better than 50 dBc at a bias voltage of 0.87 V and a yield of 100% for an SFDR of better than 45 dBc. The yield measurement results show that with careful design to match the transistors in the circuit, the conversion from phase to amplitude is achieved to the accuracy needed for an SFDR of better than 45 dBc. To facilitate higher frequency measurements, an OPA655 amplier was used to amplify the output voltage so that its spectrum could be measured using an HP8590L spectrum analyzer. The input to the interpolating circuit was generated using the memory in an Agilent 33250A function generator to create an analog phase signal that emulates the output of the accumulator and the phase DAC at high frequencies. Since it takes at least 1 s to output all 65536 B of this memory, a high frequency could only be emulated by storing more than one cycle of the output signal in this memory. Using this technique, the effective clock frequency is limited to less than 100 MHz by the 200 Msa/s output rate of the function generator. The amplitude resolution of the function generator was 8 bits, which limits the following measurements to 48 dBc due to phase truncation. The results obtained using this equipment showed that with a signal equivalent to a clock frequency between 1 kHz and 1 MHz, the spectral purity of the output signal was consistent at 48 dBc and hence is limited by the measuring equipment. However, when the function generator output represents clock frequencies of 10 and 50 MHz, the SFDR of the output from the interpolating circuit reduced to 40 and 36 dBc, respectively. These results are worse than simulations, and the discrepancy is probably due to parasitic impedances not included in the simulations, such as bond wires, the chip socket, PCB tracks, and cables. The settling time of the phase DAC is the same proporMHz in the measuretion of the clock period for 50 MHz in the simulation. Hence, with the ment and available equipment, the measurement was frequency limited to MHz with an SFDR of 40 dBc. However, with an

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TABLE I COMPARISON WITH STATE-OF-THE-ART COMPACT DDFS

integrated 9-bit phase DAC, a 50 dBc SFDR at MHz is expected. It is difcult to compare this system with state-of-the-art DDFS systems, as most previous systems target communication applications at higher frequencies (Table I). However, the power and area savings from using the compact system presented here are improvements on similar systems; hence, this system is particularly attractive for arrays of synthesizers for use in integrated microsystems. In the developed circuit, only the nonlinear interpolator is realized. Phase accumulator, DAC, and reference and bias voltages are not realized and are all emulated by using an external testing equipment. In an integrated system, the nonideality of linear DAC will degrade spurious performances. Moreover, reference and bias voltages would be generated by using on-chip circuitry with mismatch/nonuniformity, resulting in SFDR degradation. The silicon area and the power dissipation in Table I do not include the required components for the system shown in Fig. 1, which are a 9-bit accumulator and an 8-bit linear phase DAC. As a rst-order estimate, these components would add approximately 0.01 mW/MHz and 0.01 mm [4], [21] and hence dominate the required silicon area and power dissipation. Including these gures, the performance still compares favorably with the state of the art in Table I, as [2], [4], and [20] do not include an output DAC. V. CONCLUSION A new ROM-less DDFS architecture has been proposed. The critical novel component of this architecture is a simple analog circuit whose output current represents the amplitude that corresponds to a phase represented by an input voltage. Results that show that despite device and process variations, this simple very compact circuit is capable of generating an output signal with an SFDR that is better than 40 dBc and as good as 50 dBc with clock frequencies of up to 50 MHz have been presented. This level of performance makes the new architecture unsuitable for use in wireless communications systems, which are the target application of previous DDFS systems. However, there are other emerging applications, including resonant micromechanical sensors and dielectrophoretic cell sorting and characterization systems, for which this system appears to be ideal.

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