Design of A Low-Cost Airborne Radar Target Simulator Based on FPGA

Li Lu1, 2, Jianming Lei*1, Xuecheng Zou1, Xiancai Zhang2

Department of Electronic Science and Technology, Huazhong University Science and Technology, Wuhan, P. R. China 2 Air Force Radar Academy, Wuhan, P. R. China e-mail: *leijianming@mail.hust.edu.cn
AbstractIn this paper, we present a low-cost airborne radar target simulator based on FPGA, which consists of three parts: control and video processing module, intermediate frequency (IF) processing module and radio frequency (RF) processing module. The system is capable of simulating target echoes with range, Doppler, direction and the other information in real time. We also elaborate the highlights of design methodology and implementation from theory to practice. The results show that using FPGA technique make The simulator based on FPGA makes the systems reliability and stability are enhanced with low-cost. Index TermsRadar, Target Simulator, FPGA
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others. The control data from the PDA controller are sent into the radar target simulator. After being analyzed by the control and video processing module, the controlling instructions are set as the real properties of target. In accordance with the properties, the video processing module produces the range gate pulses, and The IF Doppler processing module generates Doppler frequency shift of a certain speed. Afterwards, the target information is transported to the RF processing module, in which the simulated radar echo signals can be obtained. Finally, these signals are emitted by antennas to test the performance of radar system.

I.

INTRODUCTION

Radar target simulator is an essential requirement in the defense industry for electronic countermeasure and performance evaluation of radars [1]. It is widely used to simulate the variety of radar target echo signals, which can effectively promote radar detecting performance and enforce radar operators training. To enhance electronic countermeasure capabilities of the radar, the target simulator can be used to store the intercepted radar pulse and using them to display at different ranges, speeds and the other information for the seekers [2]. We propose a low-cost airborne radar target simulator is developed exploiting this principle. With the development and widely application of EDA technology, the field-programmable gate array (FPGA) is brought out a brand new transition in digital system design because it can quickly be prototyped, tested and modified during the development. In this paper, we present a low-cost airborne radar target simulator based on FPGA, which consists of three parts: control and video processing module, IF processing module and RF processing module. The system is capable of simulating target echoes with range, Doppler, direction and the other information in real time. II. DESIGN METHODOLOGY Fig. 1 shows a block diagram of the radar target simulator. It mainly consists of three parts: control and video processing module, IF Doppler processing module and RF Processing Module. The peripheral equipments maintain systems normal operation including a PDA (Personal Digital Assistant) controller, power supplies and antenna systems. The PDA controller is implemented to configure parameters of target quantities, ranges, speeds, flight directions and the

Figure 1. Diagram of Radar target simulator.

A. Control and Video Processing Module The control and video processing module mainly receives the controlling and order instructions from the PDA controller about targets properties. After analyzing the related information, the video processing component produces the amplitude control words, the Doppler frequency shift control words and the range gate pulses, respectively. These three control words are sent to the IF Doppler processing module and the RF processing module. The block diagram of the control and video processing module is shown in Fig. 2.

Figure 2. Diagram of control and video porcessing module.

The instructions form the PDA controller are analyzed controlling and order information required for the other modules of the simulator. The radar synchronous pulses are sent to FPGA unit and are converted to the range gate pulses, which can be used as the modulation signals to target A, B and C in the RF processing module. The controlling and order

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information include targets speed and echo signals amplitude. The speed information directly can be used to produce the Doppler frequency shift in the IF Doppler processing module. The attenuated information of echo signal can be used to control the digital attenuator in the RF processing module. B. IF Doppler Processing Module The IF Doppler processing module is used to simulate the speed of target. It consists of five units, which are direct digital synthesizers (DDS), variable frequency source, phase locked loops (PLL), frequency mixers and band-pass filters [3]. The block diagram is shown in Fig.3.

the video processing module are changed into binary ASK signals. The binary signals pass by digital attenuators are sent to the radar antennas.

Figure 4. Diagram of RF porcessing module.

III. DESIGN IMPLEMENTATION FPGA technique has undergone a major transition in the last decade, because it offers a cost effectiveness method for the complex system in a short term [5]. We choose FPGA resources to implement the main parts of radar target simulator. The core components of these parts are a type of MCU (C8051F020) and an FPGA. We choose EP2C8 and EPCS4 chips of ALTERA Cyclone II to download in active serial mode, as shown in Fig. 5.

Figure 3. Diagram of IF Doppler porcessing module.

The DDS unit produces a modulation signal with a Doppler frequency shift. Its frequency can be expressed as

f = 10M f d

(1)

, where f d is the Doppler frequency shift determined by the speed of simulated target. This modulation signal can be used as the input of down-converter component of the IF Doppler processing module. The frequency of input carrier signal in down-converter component is f input . After being converted by the frequency mixer and filtered by the band-pass filter, the frequency of IF signal can be expressed as
f IF = f input f = finput (10 MHz f d )

(2)
Figure 5. Link of active serial mode.

The input carrier signal is generated by the variable frequency source using alternative frequency reference: the internal reference and the external one. The internal frequency reference depends on the high stable crystal oscillator. If it acts as the input of the variable frequency source, the radar target simulator will work at non-coherent mode. The external frequency reference comes from the output of the airborne radars coherent frequency source. If it acts as the input of the variable frequency source, the radar target simulator will work at coherent mode.
C. RF Processing Module The RF processing module is composed of five units including limiting amplifiers, power splitters, frequency mixers, band-pass filters, and digital attenuators [4]. As shown in Fig.4.

In implementation of control and video processing module, we use the FPGA as the peripheral devices of MCU, which can effectively utilize the time sequence of MCU and programmable in firmware of FPGA. The simulation waveforms of writing control are shown in Fig. 6. We can see bus data are latched at the rising edge of writing control signal at write operation.

The RF processing module receives the local oscillated signal of radar. After processed by a limiting amplifiers and a power splitter, the received signal is divided into two branches: The output signals of the IF processing module are transformed to the RF signals of X-band by frequency mixers (up-converter and down-converter). After being filtered by the band-pass filters, the RF signals controlled by the range gate pulses from

Figure 6. Simulation waveforms of writing control.

Except for the design of data latch, the address decoder and the logic gate circuits are necessary. The simulation waveforms of address decoder are shown in Fig. 7. The address decoder is listed in Table I.

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Figure 8. Top level diagram of dual port RAM. Figure 7. Simulation waveforms of address decoder. TABLE I. Address 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 LIST OF ADDRESS DECODER
Meaning

Target A: initial range Target A: speed Target A: amplitude attenuation Target B, C: initial range Target B, C: speed Target B: amplitude attenuation Target C: amplitude attenuation Target quantities control

D. Anti-interference Design During the digital signal transmission, various interferences are inevitable, some of which can result in errors. For the synchronous pulses of Radar target simulator, these interferences can produce the error range gate pulses, which lead to be false alarms in the simulator. If the received signal of simulator can be represent as NRZ format, whose width is Ts. During Ts, the input signal with interference pulse is int, the filtered output signal is s. The clock period of this filter is always T0. When (n 1)Ts < t < nTs , the input signal int = '1' .After processed by filter, the output signal in one symbol width can be obtained as s = '1' . If the interference signal is a negative pulse, whose width is less than T0. Meanwhile, the interval between two interference pulses is great than T0. After processed by filter, the output signal should also be '1' When (n 1)Ts < t < nTs , the input signal int = '0 ' .After processed by filter, the output signal in one symbol width can be obtained as s = '0 ' . If the interference signal is a positive pulse, whose width is less than T0. Meanwhile, the interval between two interference pulses is great than T0. After processed by filter, the output signal should also be '0 ' .

In the video sampling, the dual port RAM is the core component. How to implement it by using FPGA is the key problem. The parameters of dual port RAM are data width and depth of memory. In this simulator, the radar synchronous emission pulse is one bit binary signal, so the data width of RAM is also one bit. The data depth is determined by the maximum range of simulated target and the address changing rate of dual port RAM. When the maximum range of simulated target is S, the required time delay of range gate pulse T can be expressed as
T= 2S c (3)

The principle diagram of input and output signals is shown in Fig 9. The simulation waveforms of anti-interference filter is shown in Fig. 10.

, where c is the velocity of electromagnetic wave in the air. If the preset address of the controlling address generator is m, the relative time delay Td between the range gate pulse and the radar synchronous emission pulse can be expressed as Td = m f (4)

Figure 9. Principle diagram of input and output signals: (a) interference pulse is negative; (b) interference is positive.

When the maximum time delay of range gate pulse equals the relative time delay, the data depth of RAM can be obtained as below in (5). 2S m= c f
Figure 10. Simulation waveforms of anti-interference filter.

(5)

If the maximum range is 320Km and the address changing rate of dual port RAM is 50MHz, the data depth of RAM can be attained as 106668 bit. Therefore, we choose a 128K bit RMA in Cyclone II to meet system requirements. The top level diagram in Quartus II is shown in Fig.8.

From Fig.10, we find the interference pulses can be eliminated effectively, but the phase shift between the input and output signals have been brought out. When we design the whole system, this effect should be concerned. In order to rapid the design period, we use the existing products to implement the IF processing module and RF processing module. The requirements of microwave

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components and the related others can be obtained by market purchase, which are not detailed in this paper. The simulation waveforms of stationary target range at 15Km is shown in Fig.11. For the moving target, relative time delay of target video echo signal is only less than 1s in every 30ms. It cannot be seen in the simulation waveforms.

Some main technical indexes of the airborne radar target simulator is listed in Table.
TABLE II.
Signal forms Output power level IF frequecny acurracy Target range Range error

LIST OF MAIN INDEXES

Three X-band RF signals, output power can be regulated independently. 32 level, 2 dbm/level f0 50 KHZ 10 Km~320 Km < 10 setting range < 30m 0~500 m/s < 10setting speed External Synchronization

Figure 11. Simulation waveforms of stationary target range at 15Km.

Target blind area Target speed Speed error Interface

Fig.12 shows the three different function modules and case appearance of airborne radar target simulator. From left to right are the control and video processing module, the IF Doppler processing module, the RF processing module and case appearance.

(a)

(b)

(c)

(d)

Figure 12. Three function modules and case appearance of airborne radar target simulator: (a) control and video processing module, (b) IF processing module, (c) RF processing module, (d) Case appearance.

Fig. 13 shows an application system by using the airborne radar target simulator.

IV. CONCLUSION This paper brings out the design of airborne radar target simulator capable of simulating the echo of desired target at video, IF and RF levels. Based on the theory of echo signal stimulation and the high performance MCU and FPGA, the design of the control and video process module is accomplished successfully. According to the relationship between target speed and Doppler frequency shift, the design of the IF processing module and RF processing module is implemented by the existing products form the market to shorten the design period. The simulator based on FPGA makes the system reliability and stability is enhanced with design modular, field upgradeable and cost effective. REFERENCES
[1] [2] M. I. Skolnik, Introduction to Radar systems, 3rd ed., McGraw-Hill Companies, Inc. 2002. D. Meena, T. Roy, and L.G.M. Prakasam, Desing of multilevel radar target simulaotr, Radar Conference, 2007 IEEE. pp. 203208, April 2007. D. K. Barton, Radar system analysis and modeling, Artech House Publishers, 2004. M. I. Skolnik, Radar Handbook, 3rd ed., McGraw-Hill Companies, Inc. 2008 S. Kilts, Advanced FPGA Design: Architecture, Implementation, and Optimization, Wiley-IEEE Press, 2007.

[3] [4] Figure 13. Application system by using airborne radar target simulator. [5]

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