Cs2207 DC Manual

LAB MANUAL
CS 2207
DIGITAL LABORATORY (Common to CSE & IT) LIST OF EXPERIMENTS
1. Verification of Boolean theorems using digital logic gates 2. Design and im lementation of com!inational circuits using !asic gates for ar!itrar" functions# code con$erters# etc. 1. Design and im lementation of %&!it !inar" adder ' su!tractor using !asic gates and (SI de$ices 2. Design and im lementation of arit" generator ' chec)er using !asic gates and (SI de$ices *. Design and im lementation of magnitude com arator %. Design and im lementation of a lication using multi le+ers' Demulti le+ers ,. Design and im lementation of Shift registers -. Design and im lementation of S"nchronous and .s"nchronous counters /. Simulation of com!inational circuits using 0ard1are Descri tion 2anguage (V0D2' Verilog 0D2 soft1are re3uired) 4. Simulation of se3uential circuits using 0D2 (V0D2' Verilog 0D2 soft1are re3uired)
2007-08/Even/IV/ECE/EC1258/DE/LM
Page No.
LIST OF EXPERIMENTS
EXP. NO
DATE
NAME OF THE EXPERIMENT
PAGE NO
MARKS
SIGNATURE
INDEX
Page No.
EXPT NO. : D$TE :
ST D! O" LO#IC #$TES
$IM: To study about logic gates and verify their truth tables. $PP$%$T S %E& I%ED: SL No. C M! N"NT '. AN( )AT" 2. . )AT" /. N T )AT" +. NAN( )AT" 2 #0! 1. N . )AT" 6. 23 . )AT" *. NAN( )AT" / #0! -. #C T.A#N". 4#T 5. !ATC6 C .( S!"C#$#CAT# N %T& #C *+,' #C *+/2 ' #C *+,+ ' #C *+,, ' #C *+,2 ' #C *+-6 ' #C *+', ' 3 ' 3 '+
T'EO%!:
Page No.
Circuit that ta7es the logical decision and the 8rocess are called logic gates. "ach gate has one or 9ore in8ut and only one out8ut. .: AN( and N T are basic gates. NAN(: N . and 23 . are 7no;n as universal gates. Basic gates for9 these gates. $ND #$TE: The AN( gate 8erfor9s a logical 9ulti8lication co99only 7no;n as AN( function. The out8ut is high ;hen both the in8uts are high. The out8ut is lo; level ;hen any one of the in8uts is lo;.
O% #$TE: The . gate 8erfor9s a logical addition co99only 7no;n as .
function. The out8ut is high ;hen any one of the in8uts is high. The out8ut is lo; level ;hen both the in8uts are lo;. NOT #$TE: The N T gate is called an inverter. The out8ut is high ;hen the in8ut is lo;. The out8ut is lo; ;hen the in8ut is high. N$ND #$TE: The NAN( gate is a contraction of AN(3N T. The out8ut is high ;hen both in8uts are lo; and any one of the in8ut is lo; .The out8ut is lo; level ;hen both in8uts are high. NO% #$TE:
Page No.
The N . gate is a contraction of
.3N T. The out8ut is high ;hen
both in8uts are lo;. The out8ut is lo; ;hen one or both in8uts are high. X-O% #$TE: The out8ut is high ;hen any one of the in8uts is high. The out8ut is lo; ;hen both the in8uts are lo; and both the in8uts are high. P%OCED %E: <i= Connections are given as 8er circuit diagra9. <ii= <iii=
$ND #$TE: S!M)OL: PIN DI$#%$M:
Logical in8uts are given as 8er circuit diagra9. bserve the out8ut and verify the truth table.
O% #$TE:
Page No.
NOT #$TE: S!M)OL: PIN DI$#%$M:
X-O% #$TE :
Page No.
S!M)OL :
PIN DI$#%$M :
2-INP T N$ND #$TE: S!M)OL: PIN DI$#%$M:
Page No.
3-INP T N$ND #$TE :
NO% #$TE:
Page No.
%ES LT:
EXPT NO. :
D$TE :
DESI#N O" $DDE% $ND S )T%$CTO%
$IM: To design and construct half adder: full adder: half subtractor and full subtractor circuits and verify the truth table using logic gates. $PP$%$T S %E& I%ED: Sl.No. '. 2. /. +. /. +. C M! N"NT AN( )AT" 23 . )AT" N T )AT" . )AT" #C T.A#N". 4#T !ATC6 C .(S S!"C#$#CAT# N %T&. #C *+,' #C *+-6 ' #C *+,+ ' #C *+/2 ' 3 ' 3 2/
Page No. 10
T'EO%!: '$L" $DDE%: A half adder has t;o in8uts for the t;o bits to be added and t;o out8uts one fro9 the su9 > S? and other fro9 the carry > c? into the higher adder 8osition. Above circuit is called as a carry signal fro9 the addition of the less significant bits su9 fro9 the 23 . )ate the carry out fro9 the AN( gate.
" LL $DDE%: A full adder is a co9binational circuit that for9s the arith9etic su9 of in8ut@ it consists of three in8uts and t;o out8uts. A full adder is useful to add three bits at a ti9e but a half adder cannot do so. #n full adder su9 out8ut ;ill be ta7en fro9 23 . )ate: carry out8ut ;ill be ta7en fro9 )ate. '$L" S )T%$CTO%: The half subtractor is constructed using 23 . and AN( )ate. The half subtractor has t;o in8ut and t;o out8uts. The out8uts are difference and borro;. The difference can be a88lied using 23 . )ate: borro; out8ut can be i98le9ented using an AN( )ate and an inverter. " LL S )T%$CTO%: .
Page No. 11
The full subtractor is a co9bination of 23 .: AN(: .: N T )ates. #n a full subtractor the logic circuit should have three in8uts and t;o out8uts. The t;o half subtractor 8ut together gives a full subtractor .The first half subtractor ;ill be C and A B. The out8ut ;ill be difference out8ut of full subtractor. The eA8ression AB asse9bles the borro; out8ut of the half subtractor and the second ter9 is the inverted difference out8ut of first 23 ..
LO#IC DI$#%$M: '$L" $DDE%
T% T' T$)LE: $ 0 0 1 1 ) 0 1 0 1 C$%%! 0 0 0 1 S M 0 1 1 0
Page No. 12
,-Ma- .o/ S M:
,-Ma- .o/ C$%%!:
S M 0 $1) 2 $)1
C$%%! 0 $)
LO#IC DI$#%$M: " LL $DDE% " LL $DDE% SIN# T3O '$L" $DDE%
T% T' T$)LE: $ 0 0 0 ) 0 0 1 C 0 1 0 C$%%! 0 0 0 S M 0 1 1

Page No. 13
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
0 1 0 0 1
,-Ma- .o/ S M:
S M 0 $1)1C 2 $1)C1 2 $)C1 2 $)C ,-Ma- .o/ C$%%!:
C$%%! 0 $) 2 )C 2 $C LO#IC DI$#%$M: '$L" S )T%$CTO%
Page No. 1(
T% T' T$)LE: $ 0 0 1 1 ) 0 1 0 1 )O%%O3 DI""E%ENCE 0 1 0 0 0 1 1 0
,-Ma- .o/ DI""E%ENCE:
DI""E%ENCE 0 $1) 2 $)1 ,-Ma- .o/ )O%%O3:
)O%%O3 0 $1)
Page No. 15
LO#IC DI$#%$M: " LL S )T%$CTO%
" LL S )T%$CTO% SIN# T3O '$L" S )T%$CTO%:
T% T' T$)LE: $ 0 0 0
) 0 0 1
C 0 1 0
)O%%O3 DI""E%ENCE 0 1 1 0 1 1
Page No. 1*
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
1 0 0 0 1
0 1 0 0 1
,-Ma- .o/ D4..e/en5e:
D4..e/en5e 0 $1)1C 2 $1)C1 2 $)1C1 2 $)C
,-Ma- .o/ )o//o6:
)o//o6 0 $1) 2 )C 2 $1C P%OCEED %E: <i= Connections are given as 8er circuit diagra9. <ii= Logical in8uts are given as 8er circuit diagra9.
Page No. 17
<iii=
bserve the out8ut and verify the truth table.
%ES LT:
EXPT NO. :
D$TE :
DESI#N $ND IMPLEMENT$TION O" CODE CONVE%TO% $IM: To design and i98le9ent +3bit <i= Binary to gray code converter <ii= )ray to binary code converter <iii= BC( to eAcess3/ code converter <iv= "Acess3/ to BC( code converter $PP$%$T S %E& I%ED: Sl.No. C M! N"NT '. 23 . )AT" 2. AN( )AT" /. . )AT"
S!"C#$#CAT# N %T&. #C *+-6 ' #C *+,' #C *+/2 '
Page No. 18
+. 1. 6.
N T )AT" #C T.A#N". 4#T !ATC6 C .(S
#C *+,+ 3 3
' ' /1
T'EO%!: The availability of large variety of codes for the sa9e discrete ele9ents of infor9ation results in the use of different codes by different syste9s. A conversion circuit 9ust be inserted bet;een the t;o syste9s if each uses different codes for sa9e infor9ation. Thus: code converter is a circuit that 9a7es the t;o syste9s co98atible even though each uses different binary code. The bit co9bination assigned to binary code to gray code. Since each code uses four bits to re8resent a deci9al digit. There are four in8uts and four out8uts. )ray code is a non3;eighted code. The in8ut variable are designated as B/: B2: B': B, and the out8ut variables are designated as C/: C2: C': Co. fro9 the truth table: co9binational circuit is designed. The Boolean functions are obtained fro9 43Ma8 for each out8ut variable. A code converter is a circuit that 9a7es the t;o syste9s co98atible even though each uses a different binary code. To convert fro9 binary code to "Acess3/ code: the in8ut lines 9ust su88ly the bit co9bination of ele9ents as s8ecified by code and the out8ut lines generate the corres8onding bit co9bination of code. "ach one of the four 9a8s re8resents one of the four out8uts of the circuit as a function of the four in8ut variables. A t;o3level logic diagra9 9ay be obtained directly fro9 the Boolean eA8ressions derived by the 9a8s. These are various other 8ossibilities for a logic diagra9 that i98le9ents this circuit. No; the . gate ;hose out8ut is CB( has been used to i98le9ent 8artially each of three out8uts.
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 1+
LO#IC DI$#%$M: )IN$%! TO #%$! CODE CONVE%TO%
,-Ma- .o/ #3:
#3 0 )3 ,-Ma- .o/ #2:
Page No. 20
,-Ma- .o/ #1:
,-Ma- .o/ #0:
Page No. 21
T% T' T$)LE: 7 )4na/8 4n-9: )3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 )2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 )0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
7 #3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
#/a8 5o;e o9:-9: #2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 #1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 #0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
LO#IC DI$#%$M: #%$! CODE TO )IN$%! CONVE%TO%
Page No. 22
,-Ma- .o/ )3:
)3 0 #3 ,-Ma- .o/ )2:
Page No. 23
,-Ma- .o/ )1:
,-Ma- .o/ )0:

2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 2(
T% T' T$)LE: 7 #3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 #/a8 Co;e #2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 #1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 #0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 7 )3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 )4na/8 Co;e )2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 )0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7
Page No. 25
LO#IC DI$#%$M: )CD TO EXCESS-3 CONVE%TO%
,-Ma- .o/ E3:
E3 0 )3 2 )2 <)0 2 )1=
Page No. 2*
,-Ma- .o/ E2:
,-Ma- .o/ E1:
Page No. 27
,-Ma- .o/ E0:
)3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
)2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
)1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
)0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
#3 0 0 0 0 0 1 1 1 1 1 > > > > > >
#2 0 1 1 1 1 0 0 0 0 1 > > > > > >
#1 1 0 0 1 1 0 0 1 1 0 > > > > > >
#0 1 0 1 0 1 0 1 0 1 0 > > > > > >
Page No. 28
LO#IC DI$#%$M: EXCESS-3 TO )CD CONVE%TO%
Page No. 2+
,-Ma- .o/ $:
$ 0 X1 X2 2 X3 X( X1 ,-Ma- .o/ ):
Page No. 30
,-Ma- .o/ C:
,-Ma- .o/ D:
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 31
T% T' T$)LE: 7 )3 0 0 0 0 0 1 1 1 1 1 E>5e?? @ 3 In-9: )2 0 1 1 1 1 0 0 0 0 1 )1 1 0 0 1 1 0 0 1 1 0 )0 1 0 1 0 1 0 1 0 1 0 7 )CD O9:-9: #3 0 0 0 0 0 0 0 0 1 1 #2 0 0 0 0 1 1 1 1 0 0 #1 0 0 1 1 0 0 1 1 0 0 #0 0 1 0 1 0 1 0 1 0 1 7
P%OCED %E:
Page No. 32
<i= <ii= <iii=
Connections ;ere given as 8er circuit diagra9. Logical in8uts ;ere given as 8er truth table bserve the logical out8ut and verify ;ith the truth tables.
%ES LT:
EXPT NO. : D$TE :
DESI#N O" (-)IT $DDE% $ND S )T%$CTO%
Page No. 33
$IM: To design and i98le9ent +3bit adder and subtractor using #C *+-/. $PP$%$T S %E& I%ED: Sl.No. C M! N"NT S!"C#$#CAT# N %T&. '. #C #C *+-/ ' 2. "23 . )AT" #C *+-6 ' /. N T )AT" #C *+,+ ' /. #C T.A#N". 4#T 3 ' +. !ATC6 C .(S 3 +, T'EO%!: ( )IT )IN$%! $DDE%: A binary adder is a digital circuit that 8roduces the arith9etic su9 of t;o binary nu9bers. #t can be constructed ;ith full adders connected in cascade: ;ith the out8ut carry fro9 each full adder connected to the in8ut carry of neAt full adder in chain. The augends bits of >A? and the addend bits of >B? are designated by subscri8t nu9bers fro9 right to left: ;ith subscri8t , denoting the least significant bits. The carries are connected in chain through the full adder. The in8ut carry to the adder is C, and it ri88les through the full adder to the out8ut carry C+. ( )IT )IN$%! S )T%$CTO%: The circuit for subtracting A3B consists of an adder ;ith inverters: 8laced bet;een each data in8ut >B? and the corres8onding in8ut of full adder. The in8ut carry C, 9ust be eCual to ' ;hen 8erfor9ing subtraction. ( )IT )IN$%! $DDE%/S )T%$CTO%:
Page No. 3(
The addition and subtraction o8eration can be co9bined into one circuit ;ith one co99on binary adder. The 9ode in8ut M controls the o8eration. Dhen ME,: the circuit is adder circuit. Dhen ME': it beco9es subtractor. ( )IT )CD $DDE%: Consider the arith9etic addition of t;o deci9al digits in BC(: together ;ith an in8ut carry fro9 a 8revious stage. Since each in8ut digit does not eAceed 5: the out8ut su9 cannot be greater than '5: the ' in the su9 being an in8ut carry. The out8ut of t;o deci9al digits 9ust be re8resented in BC( and should a88ear in the for9 listed in the colu9ns. ABC( adder that adds 2 BC( digits and 8roduce a su9 digit in BC(. The 2 deci9al digits: together ;ith the in8ut carry: are first added in the to8 + bit adder to 8roduce the binary su9. PIN DI$#%$M "O% IC 7(83:
Page No. 35
LO#IC DI$#%$M: (-)IT )IN$%! $DDE%
Page No. 3*
LO#IC DI$#%$M: (-)IT )IN$%! S )T%$CTO%
Page No. 37
LO#IC DI$#%$M: (-)IT )IN$%! $DDE%/S )T%$CTO%
Page No. 38
T% T' T$)LE:
In-9: Da:a $ In-9: Da:a ) C 0 1 0 0 1 1 1 $;;4:4on S( S3 S2 S1 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 ) 1 1 0 0 0 0 0 S9A:/a5:4on D( D3 D2 D1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1
$( $3 $2 $1 )( )3 )2 )1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1
Page No. 3+
LO#IC DI$#%$M: )CD $DDE%
, M$P
! 0 S( <S3 2 S2=
Page No. (0
T% T' T$)LE:
S( 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 )CD S S3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 M S2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C$%%! C 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
P%OCED %E: <i= <ii= <iii= %ES LT: Connections ;ere given as 8er circuit diagra9. Logical in8uts ;ere given as 8er truth table bserve the logical out8ut and verify ;ith the truth tables.
Page No. (1
EXPT NO. : D$TE : DESI#N $ND IMPLEMENT$TION O" M$#NIT DE COMP$%$TO% $IM: To design and i98le9ent <i= <ii= 2 F bit 9agnitude co98arator using basic gates. - F bit 9agnitude co98arator using #C *+-1.
$PP$%$T S %E& I%ED: Sl.No. '. 2. /. +. 1. 6. *. C M! N"NT AN( )AT" 23 . )AT" . )AT" N T )AT" +3B#T MA)N#TU(" C M!A.AT . #C T.A#N". 4#T !ATC6 C .(S S!"C#$#CAT# N #C *+,#C *+-6 #C *+/2 #C *+,+ #C *+-1 3 3 %T&. 2 ' ' ' 2 ' /,
T'EO%!: The co98arison of t;o nu9bers is an o8erator that deter9ine one nu9ber is greater than: less than <or= eCual to the other nu9ber. A 9agnitude co98arator is a co9binational circuit that co98ares t;o nu9bers A and B and deter9ine their relative 9agnitude. The outco9e of the co98arator is s8ecified by three binary variables that indicate ;hether AGB: AEB <or= AHB.
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. (2
A E A/ A2 A' A, B E B/ B2 B' B, The eCuality of the t;o nu9bers and B is dis8layed in a co9binational circuit designated by the sy9bol <AEB=. This indicates A greater than B: then ins8ect the relative 9agnitude of 8airs of significant digits starting fro9 9ost significant 8osition. A is , and that of B is ,. De have AHB: the seCuential co98arison can be eA8anded as AGB E A/B/' B 2/A2B2' B 2/22A'B'' B 2/222'A,B,' AHB E A/'B/ B 2/A2'B2 B 2/22A''B' B 2/222'A,'B, The sa9e circuit can be used to co98are the relative 9agnitude of t;o BC( digits. Dhere: A E B is eA8anded as: A E B E <A/ B B/= <A2 B B2= <A' B B'= <A, B B,= A/ A2 A' A,
Page No. (3
LO#IC DI$#%$M: 2 )IT M$#NIT DE COMP$%$TO%
Page No. ((
, M$P
Page No. (5
T% T' T$)LE
Page No. (*
$1 $0 )1 )0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
$B) 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0
$0) 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
$C) 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
PIN DI$#%$M "O% IC 7(85:
Page No. (7
LO#IC DI$#%$M: 8 )IT M$#NIT DE COMP$%$TO%
Page No. (8
T% T' T$)LE:
$ 0000 0001 0000 0000 0001 0000 0000 0000 0001
) 0000 0000 0001
$B) 0 1 0
$0) 1 0 0
$C) 0 0 1
P%OCED %E: <i= <ii= Connections are given as 8er circuit diagra9. Logical in8uts are given as 8er circuit diagra9.
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. (+
<iii=
%ES LT:
EXPT NO. : D$TE : 1* )IT ODD/EVEN P$%IT! C'EC,E% /#ENE%$TO% $IM: To design and i98le9ent '6 bit odd0even 8arity chec7er generator using #C *+'-,.
Page No. 50
$PP$%$T S %E& I%ED: Sl.No. '. '. 2. /. C M! N"NT N T )AT" #C T.A#N". 4#T !ATC6 C .(S S!"C#$#CAT# N %T&. #C *+,+ ' #C *+'-, 2 3 ' 3 /,
T'EO%!: A 8arity bit is used for detecting errors during trans9ission of binary infor9ation. A 8arity bit is an eAtra bit included ;ith a binary 9essage to 9a7e the nu9ber is either even or odd. The 9essage including the 8arity bit is trans9itted and then chec7ed at the receiver ends for errors. An error is detected if the chec7ed 8arity bit doesn?t corres8ond to the one trans9itted. The circuit that generates the 8arity bit in the trans9itter is called a >8arity generator? and the circuit that chec7s the 8arity in the receiver is called a >8arity chec7er?. #n even 8arity: the added 8arity bit ;ill 9a7e the total nu9ber is even a9ount. #n odd 8arity: the added 8arity bit ;ill 9a7e the total nu9ber is odd a9ount. The 8arity chec7er circuit chec7s for 8ossible errors in the trans9ission. #f the infor9ation is 8assed in even 8arity: then the bits reCuired 9ust have an even nu9ber of '?s. An error occur during trans9ission: if the received bits have an odd nu9ber of '?s indicating that one bit has changed in value during trans9ission. PIN DI$#%$M "O% IC 7(180:
Page No. 51
" NCTION T$)LE: INP TS N9DAe/ o. '4gE Da:a In-9:? <I0 @ I7= EVEN ODD EVEN ODD X X LO#IC DI$#%$M:
PE 1 1 0 0 1 0
PO 0 0 1 1 1 0
O TP TS FE IO 1 0 0 1 0 1 0 1 1 0 0 1
1* )IT ODD/EVEN P$%IT! C'EC,E%
Page No. 52
T% T' T$)LE:
I7 I* I5 I( I3 I2 I1 I0 I71I*1I51I(1I31I21111 I01 $5:4ve 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1
FE 1 1 0
FO 0 0 1
LO#IC DI$#%$M: 1* )IT ODD/EVEN P$%IT! #ENE%$TO%
Page No. 53
T% T' T$)LE: I7 I* I5 I( I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 I7 I* I5 I( I3 I2 I1 I0 $5:4ve 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 FE 1 0 1 FO 0 1 0
P%OCED %E: <i= <ii= Connections are given as 8er circuit diagra9. Logical in8uts are given as 8er circuit diagra9.
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 5(
<iii=
%ES LT:
EXPT NO. : D$TE :
DESI#N $ND IMPLEMENT$TION O" M LTIPLEXE% $ND DEM LTIPLEXE% $IM:
Page No. 55
To design and i98le9ent 9ulti8leAer and de9ulti8leAer using logic gates and study of #C *+'1, and #C *+'1+. $PP$%$T S %E& I%ED: Sl.No. '. 2. /. 2. /. C M! N"NT / #0! AN( )AT" . )AT" N T )AT" #C T.A#N". 4#T !ATC6 C .(S S!"C#$#CAT# N %T&. #C *+'' 2 #C *+/2 ' #C *+,+ ' 3 ' 3 /2
T'EO%!: M LTIPLEXE%: Multi8leAer 9eans trans9itting a large nu9ber of infor9ation units over a s9aller nu9ber of channels or lines. A digital 9ulti8leAer is a co9binational circuit that selects binary infor9ation fro9 one of 9any in8ut lines and directs it to a single out8ut line. The selection of a 8articular in8ut line is controlled by a set of selection lines. Nor9ally there are 2n in8ut line and n selection lines ;hose bit co9bination deter9ine ;hich in8ut is selected. DEM LTIPLEXE%: The function of (e9ulti8leAer is in contrast to 9ulti8leAer function. #t ta7es infor9ation fro9 one line and distributes it to a given nu9ber of out8ut lines. $or this reason: the de9ulti8leAer is also 7no;n as a data distributor. (ecoder can also be used as de9ulti8leAer. #n the 'J + de9ulti8leAer circuit: the data in8ut line goes to all of the AN( gates. The data select lines enable only one gate at a ti9e and the data on the data in8ut line ;ill 8ass through the selected gate to the associated data out8ut line.
Page No. 5*
)LOC, DI$#%$M "O% (:1 M LTIPLEXE%:
" NCTION T$)LE:
S1 0 0 1 1
S0 0 1 0 1
INP TS ! D0 G D0 S11 S01 D1 G D1 S11 S0 D2 G D2 S1 S01 D3 G D3 S1 S0
! 0 D0 S11 S01 2 D1 S11 S0 2 D2 S1 S01 2 D3 S1 S0 CI%C IT DI$#%$M "O% M LTIPLEXE%:
Page No. 57
T% T' T$)LE: S1 0 0 1 1 S0 0 1 0 1 ! 0 O TP T D0 D1 D2 D3
)LOC, DI$#%$M "O% 1:( DEM LTIPLEXE%:
Page No. 58
" NCTION T$)LE:
S1 0 0 1 1
S0 0 1 0 1
INP T X G D0 0 X S11 S01 X G D1 0 X S11 S0 X G D2 0 X S1 S01 X G D3 0 X S1 S0
! 0 X S11 S01 2 X S11 S0 2 X S1 S01 2 X S1 S0
LO#IC DI$#%$M "O% DEM LTIPLEXE%:
Page No. 5+
T% T' T$)LE: S1 INP T S0 I/P D0 O TP T D1 D2 D3

Page No. *0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 1
PIN DI$#%$M "O% IC 7(150:
PIN DI$#%$M "O% IC 7(15(:
Page No. *1
P%OCED %E: <i= Connections are given as 8er circuit diagra9. <ii= <iii= %ES LT: Logical in8uts are given as 8er circuit diagra9. bserve the out8ut and verify the truth table.
Page No. *2
EXPT NO. : D$TE :
DESI#N $ND IMPLEMENT$TION O" ENCODE% $ND DECODE%
$IM: To design and i98le9ent encoder and decoder using logic gates and study of #C *++1 and #C *+'+*. $PP$%$T S %E& I%ED: Sl.No. '. 2. /. 2. /. C M! N"NT / #0! NAN( )AT" . )AT" N T )AT" #C T.A#N". 4#T !ATC6 C .(S S!"C#$#CAT# N %T&. #C *+', 2 #C *+/2 / #C *+,+ ' 3 ' 3 2*
T'EO%!: ENCODE%: An encoder is a digital circuit that 8erfor9 inverse o8eration of a decoder. An encoder has 2n in8ut lines and n out8ut lines. #n encoder the out8ut lines generates the binary code corres8onding to the in8ut value. #n octal to binary encoder it has eight in8uts: one for each octal digit and three out8ut that generate the corres8onding binary code. #n encoder it is assu9ed that only one in8ut has a value of one at any given ti9e other;ise the circuit is 9eaningless. #t has an a9biguila that ;hen all in8uts are Kero the out8uts are Kero. The Kero out8uts can also be generated ;hen (, E '. DECODE%:
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. *3
A decoder is a 9ulti8le in8ut 9ulti8le out8ut logic circuit ;hich converts coded in8ut into coded out8ut ;here in8ut and out8ut codes are different. The in8ut code generally has fe;er bits than the out8ut code. "ach in8ut code ;ord 8roduces a different out8ut code ;ord i.e there is one to one 9a88ing can be eA8ressed in truth table. #n the bloc7 diagra9 of decoder circuit the encoded infor9ation is 8resent as n in8ut 8roducing 2n 8ossible out8uts. 2n out8ut values are fro9 , through out 2n F '.
PIN DI$#%$M "O% IC 7((5: )CD TO DECIM$L DECODE%:
PIN DI$#%$M "O% IC 7(1(7:
Page No. *(
LO#IC DI$#%$M "O% ENCODE%:
Page No. *5
T% T' T$)LE: !1 1 0 0 0 0 0 0 !2 0 1 0 0 0 0 0 !3 0 0 1 0 0 0 0 INP T !( !5 0 0 0 0 0 0 1 0 0 1 0 0 0 0 !* 0 0 0 0 0 1 0 !7 0 0 0 0 0 0 1 $ 0 0 0 1 1 1 1 O TP T ) C 0 1 1 0 1 1 0 0 0 1 1 0 1 1
LO#IC DI$#%$M "O% DECODE%:
Page No. **
T% T' T$)LE: INP T $ 0 0 0 1 1 O TP T D1 D2 1 1 1 1 0 1 1 0 1 1
E 1 0 0 0 0
) 0 0 1 0 1
D0 1 0 1 1 1
D3 1 1 1 1 0
P%OCED %E: <i= Connections are given as 8er circuit diagra9.

<ii= <iii=
Logical in8uts are given as 8er circuit diagra9. bserve the out8ut and verify the truth table.
%ES LT:
EXPT NO. : D$TE : CONST% CTION $ND VE%I"IC$TION O" ( )IT %IPPLE CO NTE% $ND MOD 10/MOD 12 %IPPLE CO NTE% $IM:
To design and verify + bit ri88le counter 9od ',0 9od '2 ri88le counter. $PP$%$T S %E& I%ED: Sl.No. '. 2. /. +. C M! N"NT L4 $L#! $L ! NAN( )AT" #C T.A#N". 4#T !ATC6 C .(S S!"C#$#CAT# N %T&. #C *+*6 2 #C *+,, ' 3 ' 3 /,
T'EO%!: A counter is a register ca8able of counting nu9ber of cloc7 8ulse arriving at its cloc7 in8ut. Counter re8resents the nu9ber of cloc7 8ulses arrived. A s8ecified seCuence of states a88ears as counter out8ut. This is the 9ain difference bet;een a register and a counter. There are t;o ty8es of counter: synchronous and asynchronous. #n synchronous co99on cloc7 is given to all fli8 flo8 and in asynchronous first fli8 flo8 is cloc7ed by eAternal 8ulse and then each successive fli8 flo8 is cloc7ed by % or % out8ut of 8revious stage. A soon the cloc7 of second stage is triggered by out8ut of first stage. Because of inherent 8ro8agation delay ti9e all fli8 flo8s are not activated at sa9e ti9e ;hich results in asynchronous o8eration. PIN DI$#%$M "O% IC 7(7*:
Page No. *+
LO#IC DI$#%$M "O% ( )IT %IPPLE CO NTE%:
Page No. 70
T% T' T$)LE: CL, 0 1 2 3 ( 5 * 7 8 + 10 &$ 0 1 0 1 0 1 0 1 0 1 0 &) 0 0 1 1 0 0 1 1 0 0 1 &C 0 0 0 0 1 1 1 1 0 0 0 &D 0 0 0 0 0 0 0 0 1 1 1
Page No. 71
11 12 13 1( 15
1 0 1 0 1
1 0 0 1 1
0 1 1 1 1
1 1 1 1 1
LO#IC DI$#%$M "O% MOD - 10 %IPPLE CO NTE%:
T% T' T$)LE: CL, 0 1 2 3 &$ 0 1 0 1 &) 0 0 1 1 &C 0 0 0 0 &D 0 0 0 0

Page No. 72
( 5 * 7 8 + 10
0 1 0 1 0 1 0
0 0 1 1 0 0 0
1 1 1 1 0 0 0
0 0 0 0 1 1 0
LO#IC DI$#%$M "O% MOD - 12 %IPPLE CO NTE%:
T% T' T$)LE: CL, 0 1 2 3 ( 5 * 7 8 + 10 11 12 &$ 0 1 0 1 0 1 0 1 0 1 0 1 0 &) 0 0 1 1 0 0 1 1 0 0 1 1 0 &C 0 0 0 0 1 1 1 1 0 0 0 0 0 &D 0 0 0 0 0 0 0 0 1 1 1 1 0

Page No. 73
P%OCED %E: <i= <ii= <iii= Connections are given as 8er circuit diagra9. Logical in8uts are given as 8er circuit diagra9. bserve the out8ut and verify the truth table.
%ES LT:
Page No. 7(
EXPT NO. : D$TE : DESI#N $ND IMPLEMENT$TION O" 3 )IT S!NC'%ONO S P/DO3N CO NTE% $IM: To design and i98le9ent / bit synchronous u80do;n counter. $PP$%$T S %E& I%ED: Sl.No. '. 2. /. +. 1. 6. *. C M! N"NT L4 $L#! $L ! / #0! AN( )AT" . )AT" 2 . )AT" N T )AT" #C T.A#N". 4#T !ATC6 C .(S S!"C#$#CAT# N %T&. #C *+*6 2 #C *+'' ' #C *+/2 ' #C *+-6 ' #C *+,+ ' 3 ' 3 /1
T'EO%!: A counter is a register ca8able of counting nu9ber of cloc7 8ulse arriving at its cloc7 in8ut. Counter re8resents the nu9ber of cloc7 8ulses arrived. An u80do;n counter is one that is ca8able of 8rogressing in increasing order or decreasing order through a certain seCuence. An u80do;n counter is also called bidirectional counter. Usually u80do;n o8eration of the counter is controlled by u80do;n signal. Dhen this signal is high counter goes through u8 seCuence and ;hen u80do;n signal is lo; counter follo;s reverse seCuence. , M$P
ST$TE DI$#%$M:
Page No. 7*
C'$%$CTE%ISTICS T$)LE: & 0 0 1 1 &:21 0 1 0 1 H 0 1 X X , X X 1 0
LO#IC DI$#%$M:
T% T' T$)LE:
Page No. 77
In-9: P/e?en: S:a:e -/Do6n &$ &) &C 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
Ne>: S:a:e &$21 & )21 &C21 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0
$ H$ 1 X X X X 0 0 0 0 0 0 1 X X X X ,$ X 0 0 0 1 X X X X X X X 0 0 0 1 H) 1 X X 0 1 X X 0 0 1 X X 0 1 X X
) ,) X 0 1 X X 0 1 X X X 0 1 X X 0 1 HC 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X
C ,C X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1
P%OCED %E: <i= Connections are given as 8er circuit diagra9. <ii= <iii= %ES LT: Logical in8uts are given as 8er circuit diagra9. bserve the out8ut and verify the truth table.
EXPT NO. : D$TE : DESI#N $ND IMPLEMENT$TION O" S'I"T %E#ISTE% $IM:
To design and i98le9ent <i= Serial in serial out <ii= Serial in 8arallel out <iii= !arallel in serial out <iv= !arallel in 8arallel out $PP$%$T S %E& I%ED: Sl.No. '. 2. /. +. C M! N"NT ( $L#! $L ! . )AT" #C T.A#N". 4#T !ATC6 C .(S S!"C#$#CAT# N %T&. #C *+*+ 2 #C *+/2 ' 3 ' 3 /1
T'EO%!: A register is ca8able of shifting its binary infor9ation in one or both directions is 7no;n as shift register. The logical configuration of shift register consist of a (3$li8 flo8 cascaded ;ith out8ut of one fli8 flo8 connected to in8ut of neAt fli8 flo8. All fli8 flo8s receive co99on cloc7 8ulses ;hich causes the shift in the out8ut of the fli8 flo8. The si98lest 8ossible shift register is one that uses only fli8 flo8. The out8ut of a given fli8 flo8 is connected to the in8ut of neAt fli8 flo8 of the register. "ach cloc7 8ulse shifts the content of register one bit 8osition to right. PIN DI$#%$M:
Page No. 7+
LO#IC DI$#%$M: SE%I$L IN SE%I$L O T:
T% T' T$)LE:
Page No. 80
Se/4aI 4n CL, 1 2 3 ( 5 * 7 1 0 0 1 X X X
Se/4aI o9:
0 0 0 1 0 0 1
LO#IC DI$#%$M: SE%I$L IN P$%$LLEL O T:
T% T' T$)LE: CL, D$T$ 1 1 2 0 3 0 ( 1 LO#IC DI$#%$M: P$%$LLEL IN SE%I$L O T: &$ 1 0 0 1 O TP T &) &C 0 1 0 0 0 0 1 0 &D 0 0 1 1
Page No. 81
T% T' T$)LE: CL, 0 1 2 3 &3 1 0 0 0 &2 0 0 0 0 &1 0 0 0 0 &0 1 0 0 0 O/P 1 0 0 1
LO#IC DI$#%$M: P$%$LLEL IN P$%$LLEL O T:
T% T' T$)LE: CL, D$ D$T$ INP T D) DC DD &$ O TP T &) &C &D
Page No. 82
1 2
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
P%OCED %E: <i= <ii= <iii= Connections are given as 8er circuit diagra9. Logical in8uts are given as 8er circuit diagra9. bserve the out8ut and verify the truth table.
%ES LT:
PREPARATORY EXERCISE 1. Study of log ! g"t#$
Page No. 83
%. D#$ g& "&d '(l#'#&t"t o& of "dd#)$ "&d $u*t)"!to)$ u$ &g log ! g"t#$
Page No. 8(
+. D#$ g& "&d '(l#'#&t"t o& of !od# !o&,#)t#)$ u$ &g log ! g"t#$
Page No. 85
-. D#$ g& "&d '(l#'#&t"t o& of -.* t * &")y "dd#)/$u*t)"!to) "&d 0CD "dd#) u$ &g IC 1-2+
Page No. 8*
3. D#$ g& "&d '(l#'#&t"t o& of %.* t '"g& tud# !o'(")"to) u$ &g log ! g"t#$4 2.* t '"g& tud# !o'(")"to) u$ &g IC 1-23
Page No. 87
5. D#$ g& "&d '(l#'#&t"t o& of 15.* t odd/#,#& (") ty !6#!7#) g#&#)"to) u$ &g IC 1-128
Page No. 88
1. D#$ g& "&d '(l#'#&t"t o& of 'ult (l#9#) "&d d#'ult (l#9#) u$ &g log ! g"t#$ "&d $tudy of IC 1-138 "&d IC 1-13-
Page No. 8+
2. D#$ g& "&d '(l#'#&t"t o& of #&!od#) "&d d#!od#) u$ &g log ! g"t#$ "&d $tudy of IC 1--3 "&d IC 1-1-1
Page No. +0
:. Co&$t)u!t o& "&d ,#) f !"t o& of -.* t ) ((l# !ou&t#) "&d Mod.18/Mod.1% ) ((l# !ou&t#)
Page No. +1
18. D#$ g& "&d '(l#'#&t"t o& of +.* t $y&!6)o&ou$ u(/do;& !ou&t#)
Page No. +2
11. I'(l#'#&t"t o& of SISO4 SIPO4 PISO "&d PIPO $6 ft )#g $t#)$ u$ &g fl (.flo($
Page No. +3

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LAB MANUAL

DIGITAL LABORATORY (Common to CSE & IT) LIST OF EXPERIMENTS

NAME OF THE EXPERIMENT

EXPT NO. : D$TE :

ST D! O" LO#IC #$TES

O% #$TE: The . gate 8erfor9s a logical addition co99only 7no;n as .

The N . gate is a contraction of

.3N T. The out8ut is high ;hen

NOT #$TE: S!M)OL: PIN DI$#%$M:

2-INP T N$ND #$TE: S!M)OL: PIN DI$#%$M:

3-INP T N$ND #$TE :

DESI#N O" $DDE% $ND S )T%$CTO%

LO#IC DI$#%$M: '$L" $DDE%

T% T' T$)LE: $ 0 0 1 1 ) 0 1 0 1 C$%%! 0 0 0 1 S M 0 1 1 0

,-Ma- .o/ C$%%!:

T% T' T$)LE: $ 0 0 0 ) 0 0 1 C 0 1 0 C$%%! 0 0 0 S M 0 1 1

S M 0 $1)1C 2 $1)C1 2 $)C1 2 $)C ,-Ma- .o/ C$%%!:

C$%%! 0 $) 2 )C 2 $C LO#IC DI$#%$M: '$L" S )T%$CTO%

T% T' T$)LE: $ 0 0 1 1 ) 0 1 0 1 )O%%O3 DI""E%ENCE 0 1 0 0 0 1 1 0

,-Ma- .o/ DI""E%ENCE:

DI""E%ENCE 0 $1) 2 $)1 ,-Ma- .o/ )O%%O3:

LO#IC DI$#%$M: " LL S )T%$CTO%

" LL S )T%$CTO% SIN# T3O '$L" S )T%$CTO%:

,-Ma- .o/ D4..e/en5e:

D4..e/en5e 0 $1)1C 2 $1)C1 2 $)1C1 2 $)C

,-Ma- .o/ )o//o6:

bserve the out8ut and verify the truth table.

S!"C#$#CAT# N %T&. #C *+-6 ' #C *+,' #C *+/2 '

N T )AT" #C T.A#N". 4#T !ATC6 C .(S

LO#IC DI$#%$M: )IN$%! TO #%$! CODE CONVE%TO%

,-Ma- .o/ #3:

#3 0 )3 ,-Ma- .o/ #2:

,-Ma- .o/ #1:

,-Ma- .o/ #0:

T% T' T$)LE: 7 )4na/8 4n-9: )3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 )2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 )0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

#/a8 5o;e o9:-9: #2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 #1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 #0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

LO#IC DI$#%$M: #%$! CODE TO )IN$%! CONVE%TO%

,-Ma- .o/ )3:

)3 0 #3 ,-Ma- .o/ )2:

,-Ma- .o/ )1:

,-Ma- .o/ )0:

LO#IC DI$#%$M: )CD TO EXCESS-3 CONVE%TO%

,-Ma- .o/ E3:

,-Ma- .o/ E2:

,-Ma- .o/ E1:

,-Ma- .o/ E0:

#3 0 0 0 0 0 1 1 1 1 1 > > > > > >

#2 0 1 1 1 1 0 0 0 0 1 > > > > > >

#1 1 0 0 1 1 0 0 1 1 0 > > > > > >

#0 1 0 1 0 1 0 1 0 1 0 > > > > > >

LO#IC DI$#%$M: EXCESS-3 TO )CD CONVE%TO%

T% T' T$)LE: 7 )3 0 0 0 0 0 1 1 1 1 1 E>5e?? @ 3 In-9: )2 0 1 1 1 1 0 0 0 0 1 )1 1 0 0 1 1 0 0 1 1 0 )0 1 0 1 0 1 0 1 0 1 0 7 )CD O9:-9: #3 0 0 0 0 0 0 0 0 1 1 #2 0 0 0 0 1 1 1 1 0 0 #1 0 0 1 1 0 0 1 1 0 0 #0 0 1 0 1 0 1 0 1 0 1 7

<i= <ii= <iii=

EXPT NO. : D$TE :

DESI#N O" (-)IT $DDE% $ND S )T%$CTO%

LO#IC DI$#%$M: (-)IT )IN$%! $DDE%

LO#IC DI$#%$M: (-)IT )IN$%! S )T%$CTO%

LO#IC DI$#%$M: (-)IT )IN$%! $DDE%/S )T%$CTO%

LO#IC DI$#%$M: )CD $DDE%

LO#IC DI$#%$M: 2 )IT M$#NIT DE COMP$%$TO%

PIN DI$#%$M "O% IC 7(85:

LO#IC DI$#%$M: 8 )IT M$#NIT DE COMP$%$TO%

$ 0000 0001 0000 0000 0001 0000 0000 0000 0001

S!"C#$#CAT# N %T&. #C +-6 ' #C +,' #C *+/2 '