Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
A
I
/
I
d
d
2.4/4 NMOS
V
ds
=50 mV
[
%
]
reference
M1 lines on T
2
Id(T
1
) Id(T
2
)
AI
d
/I
d
[%] =
x 200
Id(T
1
) + Id(T
2
)
0.1
1
10
100
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
d
d
o
A
I
/
I
[
%
]
0.1
1
10
100
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
d
d
2.4/4 NMOS
V
ds
=50 mV
o
A
I
/
I
[
%
]
reference
M1 lines on T
2
reference
M1 lines on T
2
Id(T
1
) Id(T
2
)
AI
d
/I
d
[%] =
x 200
Id(T
1
) + Id(T
2
)
Id(T
1
) Id(T
2
)
AI
d
/I
d
[%] =
x 200
Id(T
1
) + Id(T
2
)
183
(open triangle) has been added to show the repeatability of
the measurement (same population). From these figures we
can conclude that there is no statistically significant
influence of metal coverage on random fluctuations. This
implies that -a mechanical stress related- systematic
mismatch (if present), is homogeneous across the wafer.
Figure 4: mismatch fluctuations as a function of variant (table1).
Top: threshold voltage mismatch fluctuations (oAV
t
) and bottom:
relative current factor mismatch fluctuations (oA|/|). 3o error
bars indicate statistical uncertainty. The extra point (open triangle)
for the reference indicates the repeatability of the measurement.
The drain current mismatch median sweeps for the
reference and for the asymmetrically covered pairs with
metal-1 or metal-3 lines are shown in Figure 5. In weak
inversion, possible effects of the metal coverage on drain
current fluctuations are overshadowed by the random
fluctuations and the associated statistical uncertainty. In
strong inversion however, the metal-1 lines cause a
significant drain current offset of 0.6%. There is no
significant influence of the metal-3 lines. These results are
reflected in the current factor mismatch values. The
medians of the relative | mismatch values (A|/|) for the
different NMOS variants (table1) are presented in Figure 6.
For some variants the metal covered (right) transistor T
2
has
a significantly lower current factor | compared to the left
transistor T
1
. In particular, the first metal can cause a |
offset of up to 1.5% (metal-1 lines), but for the third and
fourth metal we must consider the effect not statistically
significant.
[
%
]
I
/
I
A
A
I
/
I
[
%
]
-10
-5
0
5
10
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
d
d
-10
-5
0
5
10
0.00 0.25 0.50 0.75 1.00 1.25
Vgs [V]
-1.0
-0.5
0.0
0.5
1.0
0.50 0.75 1.00 1.25
-1.0
-0.5
0.0
0.5
1.0
0.50 0.75 1.00 1.25
A
I
/
I
[
%
]
reference
M1 lines on T
2
M3 lines on T
2
reference
M1 lines on T
2
M3 lines on T
2
AV
t
= V
t
(T
1
) V
t
(T
2
)
2.4/4 NMOS
V
ds
=50 mV
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
V
t
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
AV
t
= V
t
(T
1
) V
t
(T
2
) AV
t
= V
t
(T
1
) V
t
(T
2
) AV
t
= V
t
(T
1
) V
t
(T
2
)
2.4/4 NMOS
V
ds
=50 mV
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
t
o
A
V
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
t
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
o
A
V
[
m
V
]
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.0
0.2
0.4
0.6
0.8
1.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
o
A
|
/
|
[
%
]
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A
|
/
|
[
%
]
2.4/4 NMOS
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A
|
/
|
[
%
]
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
A
|
/
|
[
%
]
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
A
|
/
|
[
%
]
-0.5
0.0
0.5
1.0
1.5
2.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A|/| [%] =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A
|
/
|
[
%
]
2.4/4 NMOS
184
Figure 7: detail of large (left) and small (right) tiles in metal-1.
The total coverage of the small (0.4x0.4) tiles is about 50% of that
of the large (1.3x1.3) tiles. The light gray areas represent the
transistor poly silicon gate.
These results indicate that local mechanical stress reduces
the mobility of the device that is covered with metal. We
expect that the stress originates from the difference in
thermal expansion between copper and the surrounding
oxide, which takes effect during cooling down after inter-
layer dielectric deposition.
Figure 8: median of threshold voltage mismatch (AV
t
) as a
function of variant. 3o error bars indicate statistical uncertainty.
The extra point (open triangle) for the reference indicates the
repeatability of the measurement.
Results at elevated temperature
To investigate a possible impact of stress reduction at higher
chip operation temperatures, all populations were re-
measured at 125C. In Figure 9 the effect of the metal
coverage on the current factor is compared between 25C
(results from figure 6) and 125C. These results reveal that,
if there is a significant offset at room temperature, the offset
is reduced to a much lower level at 125C. In case of metal-
1 plate coverage, results at 125C even indicate a slightly
higher mobility for T
2
(metal covered) compared to T
1
(uncovered). The higher temperature clearly changes the
mechanical stress difference between both transistors of the
pair.
The influence of the higher temperature on mismatch
fluctuations for NMOS devices is presented in Figure 10
(oAV
t
) and 11 (oA|/|). For all variants including the
reference, the standard deviations of both V
t
mismatch
(figure 10) and relative | mismatch (figure 11) reduce at
elevated temperature. This is in line with results found for
65 nm devices [5].
Figure 9: median of relative current factor mismatch (A|/|) as
a function of variant. Results for T=25 and T=125C are
compared.
Figure 10: threshold voltage mismatch fluctuations as a function of
variant (NMOS). Results for T= 25C and T=125C are compared.
3o error bars indicate statistical uncertainty.
Figure 11: relative current factor mismatch fluctuations as a
function of variant (NMOS). Results for T= 25C and T=125C are
compared. 3o error bars indicate statistical uncertainty.
T=125C
T=25C
AV
t
= V
t
(T
1
) V
t
(T
2
)
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
V
t
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.4/4 NMOS
T=125C
T=25C
AV
t
= V
t
(T
1
) V
t
(T
2
)
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
t
o
A
V
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T=125C
T=25C
T=125C
T=25C
AV
t
= V
t
(T
1
) V
t
(T
2
) AV
t
= V
t
(T
1
) V
t
(T
2
)
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
t
o
A
V
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
t
o
A
V
[
m
V
]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.4/4 NMOS
T=125C
T=25C
A
|
/
|
[
%
]
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
2.4/4 NMOS
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
A
|
/
|
[
%
]
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
A
|
/
|
[
%
]
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
T=125C
T=25C
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
A
|
/
|
[
%
]
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
2.4/4 NMOS
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
AV
t
= V
t
(T
1
) V
t
(T
2
)
A
V
t
[
m
V
]
2.4/4 NMOS
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
V
t
[
m
V
]
AV
t
= V
t
(T
1
) V
t
(T
2
)
A
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
V
t
[
m
V
]
A
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
V
t
[
m
V
]
A
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
V
t
[
m
V
]
AV
t
= V
t
(T
1
) V
t
(T
2
) AV
t
= V
t
(T
1
) V
t
(T
2
)
A
2.4/4 NMOS
T=125C
T=25C
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.0
0.2
0.4
0.6
0.8
1.0
2.4/4 NMOS
T=125C
T=25C
T=125C
T=25C
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.0
0.2
0.4
0.6
0.8
1.0
2.4/4 NMOS
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
A|/| =
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
|(T
1
) |(T
2
)
|(T
1
) + |(T
2
)
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.0
0.2
0.4
0.6
0.8
1.0
2.4/4 NMOS
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.0
0.2
0.4
0.6
0.8
1.0
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
2.4/4 NMOS
o
A
|
/
|
[
%
]
185
For PMOS devices, similar observations as found for
NMOS devices were encountered, albeit substantially
smaller in magnitude. This is illustrated in Figure 12, where
the median of the current factor mismatch is shown as a
function of the different PMOS variants (table1), for
T=25C and T=125C. In all cases the median offset is less
than 0.5%. Also note that, although small, the effect is
opposite to the effect observed for the NMOS devices: in
case of PMOS the strained device (T
2
) has a higher current
factor (higher mobility) than the unstrained device (T
1
).
Note the similarity with the impact of STI stress [1].
Furthermore, the effect is reduced or again even reverses
sign at 125C.
Figure 12: median of relative current factor mismatch (A|/|) as
a function of variant (PMOS). Results for T=25 and T=125C are
compared. Note that the scale is different from figure 9 (NMOS).
Comparable to the NMOS devices, no statistically
significant effects of the metal coverage on the mismatch
fluctuations of the PMOS devices are seen. This is
illustrated in Figure 13 and 14, where respectively the
threshold voltage mismatch fluctuations and the relative
current factor mismatch fluctuations are shown for the
different PMOS variants. In the same graphs the results of
measurements at T=125C can be found: also for the PMOS
devices a slight reduction in fluctuations is seen at higher
temperature.
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
V
t
[
m
V
]
T=125C
T=25C
0.4
0.6
0.8
1.0
1.2
1.4
2.4/4 PMOS
AV
t
= |V
t
(T
1
)| |V
t
(T
2
)|
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
V
t
[
m
V
]
T=125C
T=25C
T=125C
T=25C
0.4
0.6
0.8
1.0
1.2
1.4
2.4/4 PMOS
AV
t
= |V
t
(T
1
)| |V
t
(T
2
)| AV
t
= |V
t
(T
1
)| |V
t
(T
2
)|
Figure 13: threshold voltage mismatch fluctuations (oAV
t
) as a
function of variant (PMOS). Results for T= 25C and T=125C are
compared. 3o error bars indicate statistical uncertainty. The extra
points (triangles) for the reference indicate the repeatability of the
measurements.
2.4/4 PMOS
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
Figure 14: relative current factor mismatch fluctuations (oA|/|)
as a function of variant (PMOS). Results for T= 25C and
T=125C are compared. 3o error bars indicate statistical
uncertainty.
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.10
0.14
0.18
0.22
0.26
0.30
0.34
2.4/4 PMOS
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.10
0.14
0.18
0.22
0.26
0.30
0.34
2.4/4 PMOS
T=125C
T=25C
T=125C
T=25C
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.10
0.14
0.18
0.22
0.26
0.30
0.34
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
o
A
|
/
|
[
%
]
0.10
0.14
0.18
0.22
0.26
0.30
0.34
2.4/4 PMOS
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
A
|
/
|
[
%
]
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
T=125C
T=25C
2.4/4 PMOS
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
A|/| =
,|(T
1
)| ||(T
2
)|
,|(T
1
)| + ||(T
2
)|
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
r
e
f
e
r
e
n
c
e
M
1
p
l
a
t
e
M
2
p
l
a
t
e
M
3
p
l
a
t
e
M
4
p
l
a
t
e
M
1
l
i
n
e
s
M
2
l
i
n
e
s
M
3
l
i
n
e
s
M
4
l
i
n
e
s
M
3
/
M
4
g
r
i
d
s
m
a
l
l
t
i
l
e
s
l
a
r
g
e
t
i
l
e
s
a
u
t
o
m
a
t
i
c
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
A
|
/
|
[
%
]
T=125C
T=25C
T=125C
T=25C
186
Conclusions
We present a comprehensive set of carefully designed
matched pair test structures for studying metal coverage
effects in a 45 nm state-of-the-art CMOS technology with
Cu damascene processing. We report substantial offsets in
drain currents of up to 1.5% for NMOS devices. These
offsets are attributed to mobility differences associated with
mechanical stress. At higher wafer temperatures (125 C)
this stress effect apparently reduces significantly. To the
best of our knowledge this has not been reported before.
For most digital ULSI applications, an offset of a few
percents is generally considered negligible compared to the
total process variability. It is therefore reassuring that this
study confirms that there will be no substantial contribution
to digital circuit variability due to (even arbitrary) placement
of metal routing and CMP tiles. For high precision analogue
and mixed signal applications however, it is (still) highly
recommendable to avoid the use of first and second metal on
top of the matching devices. At least it should be made sure
that metal coverage and dummy tiling is always as
symmetrical as possible on supposedly identical devices.
References
[1] N. Wils, H. Tuinhout and M. Meijer, Characterization of STI
Edge Effects on CMOS Variability; IEEE Transactions on
Semiconductor Manufacturing 2009, vol.22, no.1, pp.59-65
[2] P.G. Drennan et al, Implications of Proximity Effects for
Analog Design; Proceedings IEEE CICC 2006, pp.169-176
[3] H.P. Tuinhout and M. Vertregt, Test structures for
investigation of metal coverage effects on MOSFET matching;
Proc.IEEE ICMTS 1997, pp.179-183
[4] J.A. Croon et al, A comparison of extraction techniques for
threshold voltage mismatch; Proceedings IEEE ICMTS 2002,
pp.235-240
[5] P. Andricciola and H.P. Tuinhout, The temperature
dependence of mismatch in deep-submicron bulk MOSFETs;
IEEE Electron Device Letters 2009, vol.30, no.6, pp.690-692
187