Repeater Insertion for Coupled VLSI Interconnects

raghuamaraneni@gmail.com SURYA RAGHU Dept of Electronics and Communication Engineering, S AR!A"HARA#HI I!S#I#U#E $% #ECH$!$LGY, &HA''A' A(stract Repeaters are often introduced in interconnect to reduce propagation delay. In Ultra deep sub micron (UDSM) technology, interconnect lines are placed very close to each other and often run together for long distance. hese lines therefore e!hibit severe crosstal" behavior due to inductive and capacitive coupling. he line and coupling capacitance# self and mutual inductance should therefore be considered in determining the optimum number of the repeaters for coupled lines. It is $ell defined that a trade off e!ists bet$een the transient po$er dissipation and the minimum propagation delay in repeater insertion. raditionally repeaters are inserted for minimum %o$er Delay %roduct criterion. &ptimi'ing the repeater inserted to achieve minimum %D% although satisfies high speed, lo$(po$er design ob)ectives but not crosstal" constraints. Such designs sometimes lead to severe crosstal". his paper sho$s that repeater insertion reduces not only the propagation delay but also crosstal" levels for coupled lines. Repeaters can be efficiently utili'ed for reduction of propagation delay and crosstal" noise at a trade of marginal increase in po$er dissipation. he %o$er(Delay( *rosstal"( %roduct (%D*%) criterion is introduced as an efficient techni+ue to insert repeater in coupled interconnects. ,ased on %D*% a reduction in crosstal" of about -. times and delay of /.01 is achieved at trade of 23.01 increase in po$er dissipation in comparison to %D%. Keywords: &n(chip inductance, Repeater insertion, %ropagation delay, ransient po$er dissipation, %o$er Delay *rosstal" product. )* Introduction The feature size of integrated circuits has been aggressively reduced in the pursuit of improved speed, power, silicon area and cost characteristics [1]. Semiconductor technologies with feature sizes of several tens of nanometers are currently in development. s per, !nternational Technology "oadmap for Semiconductors[#], the future nanometer scale circuits will contain more than a billion transistors and operate at cloc$ speeds well over 1%&'z. (istributing robust and reliable power and ground) cloc$) data and address) and other control signals through interconnects in such a highspeed, high*comple+ity environment, is a challenging

tas$. The performance of a high*speed chip is highly dependent on interconnects, which connect different macro cells within a ,-S! chip. .ith evergrowing length of interconnects and cloc$ fre/uency on a chip, the effects of interconnects cannot be restricted to "0 models. The importance of on*chip inductance is continuously increasing with faster onchip rise times, wider wires, and the introduction of new materials for low resistance interconnects. !t has become well accepted that interconnect delay dominates gate delay in current deep sub micrometer ,-S! circuits [1]*[2]. .ith the continuous scaling of technology and increased die area, this behavior is e+pected to continue. .ide wires are fre/uently encountered in global and semi*global interconnects in upper metal layers. These wires are low resistive lines that can e+hibit significant inductive effects. (ue to presence of these inductive effects, the new generation ,-S! designers have been forced to model interconnects as distributed R4* transmission lines [1%]*[11]. These R4* transmission line when running parallel to each other have capacitive and inductive coupling, which ma$es the design of interconnects even more important in terms of crosstal$. 3uch of the research efforts till date have been directed towards reducing delay and power dissipation only [1#]*[#%]. 0rosstal$ noise effects have not been given much concern. !n a modern interconnect design, interconnects in an ad4acent metal layers are $ept orthogonal to each other. This is done to reduce crosstal$ as far as

possible. 5ut with growing interconnect density and reduced chip size, even the non*ad4acent interconnects e+hibit significant coupling effects. These coupling effects are significantly dependent on length of interconnects, distance between them, transition time of the input and the pattern of input. 6n*chip inductance induced noise to signal ratio is increasing because of the increased switching speed, reduced separation between interconnects and reduced noise margins of devices. The impact of this noise, such as oscillation, overshoots and undershoots, has made on chip7s performance of concern in design. The effect of crosstal$ induced overshoot and undershoot generated at a noise* site can propagate false switching and create a logic error[12]. The false switching occurs when the magnitude of overshoot or undershoot is beyond the threshold of the gate. The pea$ overshoot and undershoot generated at a noise*site can wear out the thin gate o+ide layer resulting in permanent failure of the chip. This problem will be significant as the feature size of transistor reduces with advancement of technology. 8niform repeater insertion is an effective techni/ue for driving long interconnects. 8niform repeater insertion techni/ue divides the interconnect into e/ual sections and employ e/ual size repeaters to drive each sections [11]. The primary ob4ective of a uniform repeater insertion system is to minimize the time for a signal to propagate through a long interconnect. This paper reveals that inserting repeaters, other than fulfilling its primary goal, reduces crosstal$ levels also, at a trade off marginal increase in power dissipation.

0onventionally, minimum power delay product criterion is used to insert repeaters in long interconnects. new criterion, the 9ower*(elay* 0rosstal$*9roduct :9(09;, is introduced as an efficient criterion, to insert repeaters in the long coupled interconnect. +* E,perimental Set up <or our studies we use an !53* 5urlington %.11=m technology with copper interconnects process [#>]. The power supply :,dd; is 1.>,. !t is assumed that there are several metal layers available for interconnects. ?ach line of the coupled interconnect is #=m wide, %.@A=m thic$ and separated by a spacing of %.#B=m. !t is well accepted that simulations of distributed R4* model of interconnect matches more accurately the actual behavior in comparison to a lumped R4* model. distributed R4* model of interconnect, $nown as the transmission line model, is the most accurate appro+imation of the actual behavior [1]. ?ach transmission line section is therefore modeled by #% distributed lumps. The capacitance and inductance values are obtained using e/uations from [#1]* [#1]. .e primarily study power dissipation, ninety percent propagation delay and crosstal$ overshoot noise for a 1%% 3'z input signal having rise and fall transition times of #ps for an interconnect length of 1%mm. To study the effect of repeater insertion on crosstal$, repeaters are inserted in line only. 8niform repeaters varying in number from 1 to @% are of size .nC1.2=m and .pCD.A=m. 5oth lines are terminated by a capacitive load of >f<. crosstal$ noise effect is measured for line . The number of repeater is varied for three different cases of stimulations to both lines vi'.

:!; !nput to line i.e. , switching from low to high.) !nput to line 5 i.e. ,5 switching from high to low :!!; , at static low and ,5 switching from high to low :!!!; , at static high and ,5 switching from high to low

%ig*) Circuit 'odel and -arameter 'atrices transmission line model is used for the simulation of circuit :<ig. 1;. n e+ample of how parameter matrices are formed for the case of two interconnects is also shown. R5 ,*5 , and 45 are the resistance, capacitance, and inductance per unit length for line 5, and R,, *, , and 4, are the same parameters for line ,. *5, and 45, are the mutual capacitances and inductances, respectively. The interconnect parameters for a length of one metre are shown in <ig. #.

.* -ropagation 'odes for Coupled Distri(uted RLC Lines The 9artial (ifferential ?/uations :9(?; that describe two coupled distributed rlc interconnects are given by [#B]

where 6, transient voltage along an active line :line 5;) 65 transient voltage along victim line :line ;) r resistance per unit length of line and 5) c line*to*ground capacitance :*5 and *,; per unit length) c5, line*to*line capacitance :*5,; per unit length) l self*inductance :45 and 4,; per unit length) l5, mutual inductance between the two conductors :45,; per unit length. dding and subtracting e/uations :1; and :#; gives the following set of decoupled 9(?sE

where 67 C 65 F 6, :9lus 3ode; and 6( C 65 * 6, :3inus 3ode;. There are two modes of propagation in a coupled R4* transmission line i.e. plus and minus modes. The plus and minus modes have physical

interpretations as being the solutions to the coupled line configuration with two different initial conditions. The plus mode, for e+ample, has the interpretation that it is the solution to the voltage of either line when both are e+cited simultaneously. The effective capacitance of the plus mode is, therefore, the line*to*ground capacitance because by definition the potential between the lines is zero. The currents in this plus configuration are in the same direction) therefore, the magnetic flu+ emanating from each line is in the same direction in the orthogonal surface lin$ing each conductor to the ground plane. <or this configuration, the effective flu+ lin$age of each line is increased which produces a higher effective inductance :self*inductance plus the mutual inductance; for the plus mode The minus mode is the solution to the transient response of the active line when the ad4acent line is switching with opposite polarity. 5ecause of the 3iller effect, the mutual capacitance is effectively twice its original value. The minus mode has an effective capacitance e/ual to the line*to*ground capacitance plus t$ice the mutual capacitance. !n addition, the currents in this configuration are e/ual in magnitude and opposite in direction. The magnetic flu+es emanating from each line are in opposing directions. The effective flu+ lin$age of each line is, therefore, reduced which produces an effectively lower inductance. The minus mode has an effective inductance e/ual to the self inductance minus the mutual inductance.

Signal propagates in plus and minus mode alternately after every repeater insertion between line and 5, when the inputs , and ,5 switch in opposite direction :shown in <ig. 1;. ?ffective coupling capacitance 0c5, produces more crosstal$ in minus mode as compared to mutual inductance l5, in plus mode of propagation. .hen the line before termination has minus mode of propagation, it shows higher level of crosstal$ at output whereas when terminated by plus mode it shows lower crosstal$ level. (epending on input switching pattern and number of repeaters it is preferred to ma$e signal propagate in plus mode in last stage.

<or illustration, when , switches from high to low and ,5 from low to high, crosstal$ level is very low for odd number of repeaters as compared to even number of repeaters. <ig. B shows normalized crosstal$

:,pea$G,dd; and propagation delay for repeaters varying in number. !t is observed that even number of repeaters produces higher crosstal$ :in form of pea$s; as compared to odd number of repeaters. .ith increase in even or odd number of repeaters their corresponding level of crosstal$ decreases. 9ropagation (elay initially decreases to a minimum value and thereafter increases with increase in number of repeaters. .hen , is static high or low and ,5 is switching, the effective mutual capacitance and inductance is c5, and l5, only. !n such input conditions, 3inus and 9lus mode of propagation does not ma$e much difference in terms of crosstal$ :<ig.>;. !n such case 9(9 criterion is well suited for determination of optimum number of repeaters re/uired. 5ut for the case when signals applied to both lines are non*static, 9(09 criterion is best suited for determination of optimum number of repeaters for overall minimization of delay, power and crosstal$. s the numbers of repeaters are increased the inductive and capacitive crosstal$ effects starts diminishing since the total capacitive and inductive coupling for each section decreases. /* Results and Discussion This section describes results obtained for designs pertaining to minimum values of delay, crosstal$, 9(9 and 9(09. 0onventional 9(9 constrained designs are as good as 9(09 for the case when one of the coupled lines is at static logic low or high. <or studying worst crosstal$ effects, both lines are stimulated by signals switching in opposite direction, which is /uite realistic scenario in any 8(S3 chip. ?ven if the inputs are

switching in same direction, the presence of each repeater propagates the signal in plus and minus mode alternately. !t is observed that using 9(9 criterion for repeater insertion instead of 9(09 increases overshoot severely by @% times and delay by B.#H. The crosstal$ overshoot is reduced at a trade of marginal increase of 11.#H in power dissipation. Thus 9(09 criterion becomes more efficient design techni/ue for crosstal$ constrained optimization process.

environment. 'owever, for R4* coupled lines the minimum crosstal$ decreases with increasing number of repeaters. criterion, 9ower* (elay* 0rosstal$*9roduct :9(09;, is introduced as an efficient techni/ue to insert repeaters in coupled lines if crosstal$ is considered in the design process. reduction in crosstal$ overshoot of 2A.1>H and delay of B.#H is achieved for marginal increase in power dissipation of 11.#H if the 9(09 criterion is used. 9ower (elay 0rosstal$ product in actual represents energy drained from power supply for driving coupled lines. Severe crosstal$ leads to higher energy drainage, which is not advisable for energy constrained systems. Thus 9(09 criterion suffices the design ob4ectives of low power) low crosstal$ and high speed systems. References [1] I. 3. "abaey, Digital Integrated *ircuits, 5 Design %erspective. ?nglewood 0liffs, JIE 9rentice*'all, 122@. [#] !nternational Technology "oadmap for Semiconductors. Semiconductor !ndustry ssociation. [6nline]. vailableEhttpEGGpublic.itrs.net [1] (. . 9riore, K!nductance on silicon for sub*micron036S ,-S!,L in %roc. I888 Symp. 64SI *ircuits, pp. 1DM1A, 3ay 1221. [B] (. 5. Iarvis, KThe effects of interconnections on highspeed logic circuits,L I888 rans. 8lectron. *omputers, vol. ?0*1%, pp. BD@MBAD, 6ct.12@1.

0* Conclusions "epeater insertion by 9(09 criterion outperforms 9(9 criterion for coupled interconnects in crosstal$ optimized