Mahendra Engineering College Mahendhirapuri Department of ECE EC1 0 !

M"#$%&$%#'((%$ )*+ ",( )&&-"#),"%*(

AIM To learn the architecture, programming and interfacing of microprocessors and microcontrollers. OBJECTIVES To introduce the architecture and programming of 8085 microprocessor. To introduce the interfacing of peripheral devices with 8085 microprocessor. To introduce the architecture and programming of 8086 microprocessor. To introduce the architecture, programming and interfacing of 8051 micro controller. 8085 CPU 9

UNIT I

8085 Architecture Instruction set Addressing modes Timing diagrams Assem l! language programming "ounters Time #ela!s Interrupts $emor! interfacing Interfacing, I%& devices. UNIT II PERIPHERALS INTERFACING 9

Interfacing 'erial I%& (8)51*+ parallel I%& (8)55* ,e! oard and #ispla! controller (8)-.* A#"%#A" interfacing Inter Integrated "ircuits interfacing (I)" 'tandard*+ /us0 1')2)"+1'385+45I/ UNIT III 8086 CPU 9

Intel 8086 Internal Architecture 8086 Addressing modes+ Instruction set+ 8086 Assem l! language 5rogrammingInterrupts. UNIT IV 8051 MICROCONTROLLER 9

8051 $icro controller hardware+ I%& pins, ports and circuits+ 67ternal memor! "ounters and Timers+'erial #ata I%&+ Interrupts+Interfacing to e7ternal memor! and 8)55. UNIT V 8051 PROGRAMMING AND APPLICATIONS 9

8051 instruction set Addressing modes Assem l! language programming I%& port programming +Timer and counter programming 'erial "ommunication Interrupt programming 8051 Interfacing0 8"#, A#", 'ensors, 'tepper $otors, ,e! oard and #A". TOTAL : 45 TEXT BOOKS
1. 1amesh ' 4aon9ar, $icroprocessor Architecture, 5rogramming and application with 8085, 3th 6dition,

5enram International 5u lishing, :ew #elhi, )000. (;nit I, II* ). <ohn ;ffen ec9, The 80786 =amil!, #esign, 5rogramming and Interfacing, Third 6dition. 5earson 6ducation, )00). 2. $ohammed Ali $a>idi and <anice 4illispie $a>idi, The 8051 $icrocontroller and 6m edded '!stems, 5earson 6ducation Asia, :ew #elhi, )002. (;nit I?, ?*

UNIT I INTEL 8085

1.1 INTRODUCTION TO MICROPROCESSOR BASED S/STEM The microprocessor is a semiconductor device (Integrated "ircuit* manufactured ! the ?8'I (?er! 8arge 'cale Integration* techni@ue. It includes the A8;, register arra!s and control circuit on a single chip. To perform a function or useful tas9 we have to form a s!stem ! using microprocessor as a "5; and interfacing memor!, input and output devices to it. A s!stem designed using a microprocessor as its "5; is called a microcomputer. The $icroprocessor ased s!stem (single oard microcomputer* consists of microprocessor as "5;, semiconductor memories li9e 651&$ and 1A$, input device, output device and interfacing devices. The memories, input device, output device and interfacing devices are called peripherals. The popular input devices are 9e! oard and flopp! dis9 and the output devices are printer, 86#%8"# displa!s, "1T monitor, etc.

The a ove loc9 diagram shows the organi>ation of a microprocessor ased s!stem. In this s!stem, the microprocessor is the master and all other peripherals are slaves. The master controls all the peripherals and initiates all operations. The wor9 done ! the processor can e classified into the following three groups. 1. Aor9 done internal to the processor ). Aor9 done e7ternal to the processor 2. &perations initiated ! the slaves or peripherals. The wor9 done internal to the processors are addition, su traction, logical operations, data transfer operations, etc. The wor9 done e7ternal to the processor are reading%writing the memor! and reading%writing the <%& devices or the peripherals. If the peripheral re@uires the attention of the master then it can interrupt the master and initiate an operation.

The microprocessor is the master, which controls all the activities of the s!stem. To perform a specific Bo or tas9, the microprocessor has to e7ecute a program stored in memor!. The program consists of a set of instructions. It issues address and control signals and fetches the instruction and data from memor!. The instruction is e7ecuted one ! one internal to the processor and ased on the result it ta9es appropriate action. /;'6'0 The uses are group of lines that carries data, address or control signals.

The CPU Bus has multiplexed lines, i.e., same line is used to carry different signals. The "5; interface is provided to demultiple7 the multiple7ed lines, to generate chip select signals and additional control signals.

The system bus has separate lines for each signal. All the slaves in the s!stem are connected to the same s!stem us. At an! time instant communication ta9es place etween the master and one of the slaves. All the slaves have tri+ state logic and hence normall! remain in high impedance state. &nl! when the slave is selected it comes to the normal logic.

561I5C61A8 #6?I"6'0 The 651&$ memor! is used to store permanent programs and data. The 1A$ memor! is used to store temporar! programs and data. The input device is used to enter the program, data and to operate the s!stem. The output device is used for e7amining the results. 'ince the speed of I%& devices does not match with the speed of microprocessor, an interface device is provided etween s!stem us and I%& devices. Generally I/ de!ices are slo" de!ices. A+0)*,)1'( %2 M"#$%&$%#'((%$ 3)('+ (4(,'5 1. "omputational%processing speed is high. ). Intelligence has een rought to s!stems. 2. Automation of industrial processes and office administration. 3. 'ince the devices are programma le, there is fle7i ilit! to alter the s!stem ! changing the software alone. 5. 8ess num er of components, compact in si>e and cost less. Also it is more relia le. 6. &peration and maintenance are easier. D"()+0)*,)1'( %2 M"#$%&$%#'((%$ 3)('+ S4(,'5 1. It has limitations on the si>e of data. ). The applications are limited ! the ph!sical address space. 2. The analog signals cannot e processed directl! and digiti>ing the analog signals introduces errors. 3. The speed of e7ecution is slow and so real time applications are not possi le. 5. $ost of the microprocessors does not support floating point operations.

INTEL 8085 ! P"* D")1$)5 6 D'(#$"&,"%*

The I:T68 8085 is a 8+ it microprocessor. It operates on 8+ it data and uses 16+ it address to access the memor!. Aith the help of 16+ it address, 8085 can access )16 D 65526 D 63, memor! locations. It is a 30+pin #I5 chip designed using :$&'. It operates with a power suppl! of E5 volts and 4:#. 8085 generates the cloc9 signal internall! ! dividing the e7ternal supplied cloc9 signal ! two.

INTEL 8085 ARCHITECTURE

The architecture of.8085 is shown in figure given elow. The internal architecture of 8085 includes the A8;, timing and control unit, instruction register and decoder, register arra!, interrupt control and serial I%& control.

&561ATI&:' 561=&1$6# /F 8085 The A8; performs the arithmetic and logical operations. The operations performed ! A8; of 8085 are )++","%*7 (83,$)#,"%*7 "*#$'5'*,7 +'#$'5'*,7 -%1"#)- AND7 OR7 EXCL U8IVE 9OR7 #%5&)$'7 #%5&-'5'*, and -'2, : $"1;, (;"2,. The accumulator and temporar! register are used to hold the data during an arithmetic % logical operation. After an operation the result is stored in the accumulator and the flags are set or reset according to the result of the operation. =8A4 164I'T610 There are five flags in 8085, which are ("1* 2-)1 <8=7 >'$% 2-)1 <?=7 )8@"-")$4 #)$$4 2-)1 <AC=7 &)$",4 2-)1 <P= and #)$$4 2-)1 <C/=. The it positions reserved for these flags in the flag register are shown in figure elow.

After an A8; operation, if the most significant it of the result is 1, then sign flag is set. The >ero flag is set, if the A8; operation results in >ero and it is reset if the result is non+>ero. In an arithmetic operation, when a carr! is generated ! the lower ni le, the au7iliar! carr! flag is set. After an arithmetic or logical operation, if the result has an even num er of 1 Gs the parit! flag is set, other wise it is reset. If an arithmetic operation results in a carr!, the carr! flag is set other wise it is reset. Among the five flags, the A" flag is used internall! for /"# arithmetic and other four flags can e used ! the programmer to chec9 the conditions of the result of an operation. TI$I:4 H "&:T1&8 ;:IT0 The timing and control unit s!nchroni>es all the microprocessor operations with the cloc9 and generates the control signals necessar! for communication etween the microprocessor and peripherals. I:'T1;"TI&: 164I'T61 H #6"&#610 Ahen an instruction is fetched from memor! it is placed in instruction register. Then it is decoded and encoded into various machine c!cles. 164I'T61 A11AF0 Apart from Accumulator (A+register*, there are si7 general+purpose programma le registers /, ", #, 6, C and 8. The! can e used as 8+ it registers or paired to store l6+ it data. The allowed pairs are /+", #+6 and C+8. The temporar! registers A and I are intended for internal use of the processor and it cannot e used ! the programmer. 'TA", 5&I:T61 ('5*0 The stac9 pointer '5, holds the address of the stac9 top. The stac9 is a se@uence of 1A$ memor! locations defined ! the programmer. The stac9 is used to save the content of registers during the e7ecution of a program. 51&41A$ "&;:T61 (5"*0 The program counter (5"* 9eeps trac9 of program e7ecution. To e7ecute a program the starting address of the program is loaded in program counter. The 5" sends out an address to fetch a !te of instruction from memor! and increment its content automaticall!. Cence, when a !te of instruction is fetched, the 5" holds the address of the ne7t !te of the instruction or ne7t instruction.

INSTRUCTION EXECUTION AND DATA FLOA "* 8085 The program instructions are stored in memor!, which is an e7ternal device. To e7ecute a program in 8085, the starting address of the program should e loaded in program counter. The 8085 output the content of program counter in address us and asserts read control signal low. Also, the program counter is incremented. The address and the read control signal ena le the memor! to output the content of memor! location on the data us. :ow the content of data us is the opcode of an instruction. The read control signal is made high ! timing and control unit after a specified time. At the rising edge of read control signals, the opcode is latched into microprocessor internal us and placed in instruction register. The instruction+decoding unit, decodes the instructions and provides information to timing and control unit to ta9e further actions.

INSTRUCTION FORMAT OF 8085

The 8085 have -3 asic instructions and )36 total instructions. The instruction set of 8085 is defined ! the manufacturer Intel "orporation. 6ach instruction of 8085 has 1 !te opcode. Aith 8 it inar! code, we can generate )56 different inar! codes. In this, )36 codes have een used for opcodes.

The si>e of 8085 instructions can e 1 !te, ) !tes or 2 !tes. The 1+ !te instruction has an opcode alone. The ) !tes instruction has an opcode followed ! an eight+ it address or data. The 2 !tes instruction has an opcode followed ! 16 it address or data. Ahile storing the 2 !tes instruction in memor!, the se@uence of storage is, opcode first followed ! low !te of address or data and then high !te of address or data.

ADDRESSING MODES
6ver! instruction of a program has to operate on a data. The method of specif!ing the data to e operated ! the instruction is called #ddressing. The 8085 has the following 5 different t!pes of addressing. 1. Immediate Addressing ). #irect Addressing 2. 1egister Addressing 3. 1egister Indirect Addressing 5. Implied Addressing I55'+"),' A++$'(("*1 In immediate addressing mode, the data is specified in the instruction itself. The data will e apart of the program instruction. All instructions that have JIK in their mnemonics are of Immediate addressing t!pe. $g. $?I /, 26C + $ove the data 26C given in the instruction to / register. D"$'#, A++$'(("*1 In direct addressing mode, the address of the data is specified in the instruction. The data will e in memor!. In this addressing mode, the program instructions and data can e stored in different memor! loc9s. This t!pe of addressing can e identified ! 16+ it address present in the instruction. $g. 8#A 1050C + 8oad the data availa le in memor! location 1050C in accumulator. R'1"(,'$ A++$'(("*1 In register addressing mode, the instruction specifies the name of the register in which the data is availa le. This t!pe of addressing can e identified ! register names (such as JAK, J/K, L * in the instruction. $g. $&? A, / +$ove the content of / register to A register. R'1"(,'$ I*+"$'#, A++$'(("*1 In register indirect addressing mode, the instruction specifies the name of the register in which the address of the data is availa le. Cere the data will e in memor! and the address will e in the register pair. This t!pe of addressing can e identified ! letter J$K present in the instruction. $g. $&? A, $ + The memor! data addressed ! C8 pair is moved to A register. I5&-"'+ A++$'(("*1 In implied addressing mode, the instruction itself specifies the t!pe of operation and location of data to e operated. This t!pe of instruction does not have an! address, register name, immediate data specified along with it. $g. "$A + "omplement the content of accumulator.

INSTRUCTION SET
The 8085 instruction set can e classified into the following five functional headings. G$%8& I 9 DATA TRANSFER INSTRUCTIONS: Includes the instructions that moves ( copies* data etween registers or etween memor! locations and registers. In all data transfer operations the content of source register is not altered. Cence the data transfer is cop!ing operation. 670 i* $&? A,/ ii* 8#A 3600 iii* 8C8# 3)00

G$%8& II 9 ARITHMETIC INSTRUCTIONS: Includes the instructions which performs the addition, su traction, increment or decrement operations. The flag conditions are altered after e7ecution of an instruction in this group. 670 i* A## / ii* ';/ " iii* I:1 # iv* I:M C

G$%8& III 9 LOGICAL INSTRUCTIONS: The instructions which performs the logical operations li9e A:#, &1, 67clusive+&1, complement, compare and rotate instructions are grouped under this heading. The flag conditions are altered after e7ecution of an instruction in this group. 670 i* &1A / ii* M1A A iii* 1A1

G$%8& IV 9 BRANCHING INSTRUCTIONS: The instructions that are used to transfer the program control from one memor! location to another memor! location are grouped under this heading. 670 i* <I 3)00 ii* 1'T iii* "A88 3200

G$%8& V 9 MACHINE CONTROL INSTRUCTIONS: Includes the instructions related to interrupts and the instruction used to halt program e7ecution. 670 i* 'I$ ii* 1I$ iii* C8T

The -3 asic instructions of8085 are listed inTa le+).1. The opcode of each instruction, si>e, machine c!cles, num er of T +state and the total num er of instructions in each t!pe are also shown in ta le in ne7t page. The instructions affecting the status flag are listed in ta le followed.

INTERRUPTS
NEED FOR INTERRUPTS Interrupt is a signal send by an external de!ice to the processor, to the processor to perform a particular tas% or "or%. &ainly in the microprocessor based system the interrupts are used for data transfer bet"een the peripheral and the microprocessor. Ahen a peripheral is read! for data transfer, it interrupts the processor ! sending an appropriate signal to the interrupt pin of the processor. If the processor accepts the interrupt then the processor suspends its current activit! and e7ecutes an interrupt service su routine to complete the data transfer etween the peripheral and processor. After e7ecuting the interrupt service routine the processor resumes its current activit!. This t!pe of data transfer scheme is called interrupt driven data transfer scheme.

T/PES OF INTERRUPTS The interrupts are classified into software interrupts and hardware interrupts.

The soft"are interrupts are program instructions. These instructions are inserted at desired locations in a program. Ahile running a program, lf a software interrupt instruction is encountered, then the processor e7ecutes an interrupt service routine (I'1*. The hard"are interrupts are initiated by an external de!ice by placing an appropriate signal at the interrupt pin of the processor. If the interrupt is accepted, then the processor e7ecutes an interrupt service routine (I'1*.

SOFTAARE INTERRUPTS OF 8085 The software interrupts are program instructions. Ahen the instruction is e7ecuted, the processor e7ecutes an interrupt service routine stored in the vector address of the software interrupt instruction. The software interrupts of 8085 are 1'T 0, 1'T 1, 1'T ), 1'T 2, 1'T 3, 1'T 5, 1'T 6 and 1'T -. The vector addresses of software interrupts are given in ta le elow.

The software interrupt instructions are included at the appropriate (or re@uired* place in the main program. Ahen the processor encounters the software instruction, it pushes the content of 5" (5rogram "ounter* to stac9. Then loads the ?ector address in 5" and starts e7ecuting the Interrupt 'ervice 1outine (I'1* stored in this vector address. At the end of I'1, a return instruction + 16T will e placed. Ahen the 16T instruction is e7ecuted, the processor 5&5 the content of stac9 to 5". Cence the processor control returns to the main program after servicing the interrupt. $xecution of I'( is referred to as ser!icing of interrupt. All software interrupts of 8085 are vectored interrupts. The software interrupts cannot e mas9ed and the! cannot e disa led. T;' (%2,B)$' "*,'$$8&,( )$' RST07 RST17 C RSTD <8 N%(=. HARDAARE INTERRUPTS OF 8085 An e7ternal device, initiates the hardware interrupts of 8&85 ! placing an appropriate signal at the interrupt pin of the processor. The processor 9eeps on chec9ing the interrupt pins at the second T +state of last machine c!cle of ever! instruction. If the processor finds a valid interrupt signal and if the interrupt is unmas9ed and ena led, then the processor accepts the interrupt. The acceptance of the interrupt is ac9nowledged ! sending an I:TA signal to the interrupted device. The processor saves the content of 5" (program "ounter* in stac9 and then loads the vector address of the interrupt in 5". (If the interrupt is non+vectored, then the interrupting device has to suppl! the address of I'1 when it receives I:TA signal*. It starts e7ecuting I'1 in this address. At the end of I'1, a return instruction, 16T will e placed. Ahen the processor e7ecutes the 16T instruction, it 5&5 the content of top of stac9 to 5". Thus the processor control returns to main program after servicing interrupt. T;' ;)$+B)$' "*,'$$8&,( %2 8085 )$' TRAP7 RST D.57 RST 6.57 RST 5.5 )*+ INTR. =urther the interrupts ma! e classified into ?6"T&16# and :&:+?6"T&16# I:T611;5T'. ?6"T&16# I:T611;5T In vectored interrupts, the processor automaticall! ranches to the specific address in response to an interrupt. :&:+?6"T&16# I:T611;5T /ut in non+vectored interrupts the interrupted device should give the address of the interrupt service routine (I'1*. In !ectored interrupts, the manufacturer fixes the address of the I'( to "hich the program control is to be transferred. The !ector addresses of hard"are interrupts are gi!en in table abo!e in pre!ious page.

The T1A5, 1'T -.5, 1'T 6.5 and 1'T 5.5 are vectored interrupts. The I:T1 is a non+vectored interrupt. Cence when a device interrupts through I:T1, it has to suppl! the address of I'1 after receiving interrupt ac9nowledge signal.

The type of signal that has to be placed on the interrupt pin of hardware interrupts of 8085 are defined by INTEL. The T1A5 interrupt is edge and level sensitive. Cence, to initiate T1A5, the interrupt signal has to ma9e a low to high transition and then it has to remain high until the interrupt is recogni>ed. The 1'T -.5 interrupt is edge sensitive (positive edge*. To initiate the 1'T -.5, the interrupt signal has to ma9e a low to high transition an it need not remain high until it is recogni>ed. The 1'T 6.5, 1'T 5.5 and I:T1 are level sensitive interrupts. Cence for these interrupts the interrupting signal should remain high, until it is recogni>ed.

$A',A/86 H :&:+$A',A/86 I:6T11;5T'0 The hardware vectored interrupts are classified into mas able and non!mas able interrupts. T1A5 is non+mas9a le interrupt 1'T -.5, 1'T 6.5 and 1'T 5.5 are mas9a le interrupt.

$as9ing is preventing the interrupt from distur ing the main program. Ahen an interrupt is mas9ed the processor will not accept the interrupt signal. The interrupts can e mas9ed ! moving an appropriate data (or code* to accumulator and then e7ecuting 'I$ instruction. ('I$ + 'et Interrupt $as9*. The status of mas9a le interrupts can e read into accumulator ! e7ecuting 1I$ instruction (1I$ + 1ead Interrupt $as9*. All the hardware interrupts, e7cept T1A5 are disa led, when the processor is resetted. The! can also e disa led ! e7ecuting #l instruction. (#l+#isa le Interrupt*. Ahen an interrupt is disa led, it will not e accepted ! the processor. (i.e., I:T1, 1'T 5.5, 1'T 6.5 and 1'T -.5 are disa led ! #I instruction and upon hardware reset*. To ena le (to allow* the disa led interrupt, the processor has to e7ecute 6l instruction (6l+ 6na le Interrupt*.

INTERRUPT DRIVEN DATA TRANSFER SCHEME The interrupt driven data transfer scheme is the est method of data transfer for effectivel! utili>ing the processor time. In this scheme, the processor first initiates the I%& device for data transfer. After initiating the device, the processor will continue the e7ecution of instructions in the program. Also at the end of an instruction the processor will chec9 for a valid interrupt signal. If there is no interrupt then the processor will continue the e7ecution. Ahen the I%& device is read!, it will interrupt the processor. &n receiving an interrupt signal, the processor will complete the current instruction e7ecution and saves the processor status in stac9. Then the processor calls an interrupt service routine (I'1* to service the interrupted device. At the end of I'1 the processor status is retrieved from stac9 and the processor starts e7ecuting its main program. The se@uence of operations for an interrupt driven data transfer scheme is shown in figure elow.

TIMING DIAGRAM for various machine cycles

The machine c!cles are the asic operations performed ! the processor, while instructions are e7ecuted. The time ta9en for performing each machine c!cle is e7pressed in terms of T+ states. &ne T+state is the time period of one cloc9 c!cle of the microprocessor. The various machine c!cles are 1. ). 2. 3. 5. 6. -. &pcode fetch LLLLL.. $emor! 1ead LLLLL. $emor! Arite LLLLL. I%& 1ead LLLLLLL.. I%& Arite LLLLLLL. Interrupt Ac9nowledge LL /us Idle LLLLLLLL + + + + + + + 3%6T 2T 2T 2T 2T 6 % 1) T )%2T

DELA/ ROUTINE
#ela! routines are su routines used for maintaining the timings of various operations in microprocessor. In control applications, certain e@uipment needs to e )/ ** after a specified time dela!. In some applications, a certain operation has to e repeated after a specified time interval. In such cases, simple time dela! routines can e used to maintain the timings of the operations. #68AF 1&;TI:6 51&"6'' # delay routine is generally "ritten as a subroutine +It need not be a subroutine al"ays. It can be e!en a part of main program,. In delay routine a count +number, is loaded in a register of microprocessor. Then it is decremented by one and the -ero flag is chec%ed to !erify "hether the content of register is -ero or not. This process is continued until the content of register is -ero. .hen it is -ero, the time delay is o!er and the control is transferred to main program to carry out the desired operation. The dela! time is given ! the total time ta9en to e7ecute the dela! routine. It can e computed ! multipl!ing the total num er of T+states re@uired to e7ecute su routine and the time for one T+state of the processor. The total num er of T+states can e computed from the 9nowledge of T+states re@uired for each instruction. The time for one T+state of the processor is given ! the inverse of the internal cloc9 fre@uenc! of the processor. =or e7ample, if the 8085 microprocessor has 5 $C> @uart> cr!stal then, The internal cloc9 fre@uenc! D 5 % ) D ).5 $C> Time for one T+stateD 1 % ).5 7 106 D 0.3Nsec =or small time dela!s (O 0.5 msec* an 8+ it register can e used. =or large time dela!s (O 0.5 'ec* l6+ it register should e used. =or ver! large time dela!s (P 0.5 sec*, a dela! routine can e repeatedl! called in the main program.

The disadvantage in dela! routines is that the processor time is wasted. An alternate solution is to use dedicated timer li9e 8)52%8)53 to produce time dela!s or to maintain timings of various operations. Two e7ample dela! routines are presented in this section with details of timing calculations.

EXAMPLE DELA/ ROUTINE +1 Arite a dela! routine to produce a time dela! of 0.5 msec in 8085 processor+ ased s!stem whose cloc9 source is 6 $C> @uart> cr!stal. S%-8,"%* The dela! re@uired is 0.5 msec, hence an 8+ it register of8085 can e used to store a "ount value and then decrement to >ero. The dela! routine is written as a su routine as shown elow. D'-)4 $%8,"*' $?I #, ) /oop0 #"1 # <:I /oop 16T Q Q Q Q 8oad the count value, ) in #+register. #ecrement the count. If count is >ero go to 1eturn to main program.

The following ta le shows the T+state re@uired for e7ecution of the instructions in the su routine.
Instruction "A88 addr16 $?I #, : #"1 # <:I 8&&5 16T T1'tate re2uired for execution of an instruction 18 3 10 (or* 10 )umber of times the instruction is executed 1 1 : times (:+1* times 1 1 Total T1'tates 18 7 1 D 18 -71D3 7 : D 3: 10 7 (:+1* D 10: + 10 -71D10 7 1 D 10 13: E 2)

T&TA8 T+'TAT6' =&1 #68AF ';/1&;TI:6

C)-#8-),"%* ,% 2"*+ ,;' #%8*, 0)-8'7 N: 67ternal cloc9 fre@uenc! Internal cloc9 fre@uenc! D 6 $h> D 67ternal =re@uenc! % ) D6%) D 2 $h> D 1 % Internal cloc9 fre@uenc! D 1 % 27106 D 0.222N' D 1e@uired time dela! % Time for one T+state D 0.5m' % 0.222N' D 1500.10 R 1500 D 150010

Time period for 1 T+'tate

:o. of T+states re@uired for dela! of 0.5m'

=rom a ove ta le, we 9now thatQ 13: E 2) D 1500 : D (1500 2)* % 13 D 103.85-10 R 10510 D 6.C Therefore by replacing the count value" N by #$% in the above program " a delay of 0.5m&ec can be produced.

PROGRAMMING EXAMPLES: 1. A$",' )* ALP 8("*1 8085 ,% 58-,"&-4 ,B% 893", *853'$( 34 $'&'),'+ )++","%*. $?I A, && $?I ", && $?I /, data34 $?I #, data35 8oop0 A## / <:" ne7t I:1 " :e7t0 #"1 # <:I loop 'TA 3)00C $&? A," 'TA 3)01C Q #ccumulator contents are cleared Q C (egister contents are cleared Q I perand is loaded into B (egister Q II perand is loaded into 6 (egister S S T &ultiplication by repeated addition. S S Q 'toring of results into memory location Q 'toring of carry into next memory location

2.

A$",' )* ALP 2%$ 8085 ,% #%8*, 2$%5 AAH ,% 00H7 B",; ) ,"5' +'-)4 %2 E5( 2%$ ')#; #%8*,. A((85' ,;' '@,'$*)- 2$'F8'*#4 1"0'* ,% ,;' &$%#'((%$ "( EMH>. Internal =re@uenc! in 8085 ie., 1 T+'tate D 67ternal fre@uenc! % ) D )$h> % ) D 1$h>

D 1 % f (internal fre@uenc!* D 1 '

&ain program for counting from ## to 77 $?I ", AAC 8oop0 "A88 #ela! #"1 " <:I 8oop C8T 6elay program for delay of 5ms #ela!0 $?I #, 3AC :e7t0 :&5 :&5 :&5 :&5 #"1 # <:I :e7t 16T

3.

A$",' )* ALP 8("*1 8085 ,% '0)-8),' ,;' '@&$'(("%* CGAEHBE 8et JAK e #ataU1 and J/K e #ataU) Q Q Q Q #ata 34 is stored in register B Copy of 6ata 34 is made in register C #ata 35 is stored in register 6 Copy of 6ata 35 is made in register $

$?I /, #ataU1 $&? ", / $?I #, #ataU) $&? 6,# M1A A Again0 A## / #"1 " <:I Again $&? C,A M1A A 8oop0 A## # #"1 6 <:I 8oop A## C

Q #ccumulator content is cleared V T #5 is calculated by repeated #ddition V Q Calculated #5 !alue is stored in register 8 Q #ccumulator content is cleared V T B5 is calculated by repeated #ddition V Q #59 B5 is determined, by adding result in # and register content 8 (esult is stored in memory location :5778

'TA 3)00C

INTERFACING EXAMPLES:
D$)B ,;' #"$#8", +")1$)5 %2 )* 8085 (4(,'57 ;)0"*1 ) 4 KB EPROM )*+ ,B% 8 KB RAM IC(. T;' (,)$,"*1 )++$'(( %2 ,;' EPROM "( 0000H )*+ ,;), %2 RAM "( 8000H. T;' )++$'(( %2 ,;' +'#%+'$ #"$#8",( (;%8-+ 3' #-')$-4 (;%B*. 'nswer ( 651&$ 1A$+I 1A$+II + + + 3 ,/ (Address lines re@uired is 1) A0 to A11 * 8 ,/ (Address lines re@uired is 12 A0 to A1) * 8 ,/ (Address lines re@uired is 12 A0 to A1) *

$apping of Addresses to $emor! Ics ICs 651& $ 3 ,/ Binary #ddress A15 A13 A12 A1) A11 A10 A. A8 A- A6 A5 A3 A2 A) A1 A0 0 0 . . 0 0 0 . . 0 1 1 . . 1 0 0 . . 0 1 1 . . 1 0 0 . . 0 7 7 . . 7 7 7 . . 7 7 7 . . 7 7 7 . . 7 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 0 . . 1 0 1 . . 1 0 1 . . 1 0 1 . . 1 8ex #ddres s 0000 0001 . . 0=== 3000 3001 . . 5=== 8000 8001 . . .===

1A$+I 8 ,/

1A$+II 8 ,/

P)$, A: 1. S,),' ,;' 28*#,"%* %2 HOLD )*+ HLDA &"*( "* 8085. The C&8# and C8#A pins in 8085 are used in interfacing the 8)5-+#$A controller I" with the processor. A signal is sent ! 8)5- to C&8# pin in 5, to re@uest the 5 to stop its current process and allocate the uses for #$A data transfer. 5 ac9nowledges the re@uest for #$A data transfer ! 8)5-, ! sending a signal in C8#A to 8)5-. E. D"(,"*18"(; I:O 5)&&'+ I:O )*+ 5'5%$4 5)&&'+ I:O. $apping is the process ! which the addresses are allocated to the I%& devices. The two 9inds of mapping are a* $emor! mapped I%& * I%& mapped I%& S.N% 1 ) 2 3 5 6 &emory mapped I/ 4; bit address is given to each I%& device 6ach I/ de!ice is treated li%e a memory location and the! are accessed using instructions related to memor! operations. #ata can e transferred bet"een I/ de!ices and all registers in 5. This scheme is used in s!stem, where memory re2uirement is small. &nl! &emory (ead = .rite machine cycles are in!ol!ed during data transfer with I%& devices. 8arge num er of I%& devices can e connected in this scheme. I:O 5)&&'+ I:O < bit address is given to each I%& device All I%& devices are accessed using only t"o instructions vi>., I: and &;T. #ata can e transferred only bet"een I/ de!ices and accumulator in 5. This scheme is used in s!stem, where complete memory capacity is re2uired. &nl! I/ (ead = .rite machine cycles are in!ol!ed during data transfer with I%& devices. &nl! ma7imum of )56(D)8 * I%& devices can e connected in this scheme.

. E@&-)"* ,;' '@'#8,"%* %2 ,;' "*(,$8#,"%* CMA "*(,$8#,"%* "* 8085. "$A instruction is used to perform 1Ks complement of the contents of Accumulator in 8085.

4. A;), "( ,;' 28*#,"%* &'$2%$5'+ 34 SIM )*+ RIM "*(,$8#,"%*. 'I& Instruction0 The 'I$ instruction is used to mas9 the hardware interrupts 1'T-.5, 1'T6.5 and 1'T5.5. It is also used to send data through '&# line. (I& Instruction0 The 1I$ instruction is used to chec9 whether an interrupt (1'T-.5, 1'T6.5 and 1'T5.5* is mas9ed or not. It is also used to read data from 'I# line.

5.

A;), B"-- 3' ,;' %8,#%5'7 "* '@'#8,"%* %2 "*(,$8#,"%*( LXI H74600H )*+ LHLD 4600HI Ahen 8MI C,3600 is e7ecuted, the num er 3600 will e loaded to C8 register pair. Ahen 8C8# 3600 is e7ecuted, the contents of memor! location 3600C will e transferred to C8 register pair.
6.

E@&-)"* ,;' #%*#'&, %2 +'58-,"&-'@"*1 AD09D -"*'( "* 8085I #emultiple7ing is the process of separating the low !te address A0+- and 8+ it data #0+from A#0+- lines of 8085, using a latch and Address latch ena le (A86* signal. #0+-

AD0-7

8085
ALE

74LS373 Latch
EN

A0+-

Ahen low !te address (A0+- * comes out of A#0+- lines, the processor asserts CI4C in the A86 pin, ena ling the latch to separate the low !te address.

D. C%5&)$' S4(,'5 38( )*+ CPU 38(. /us is a set of conducting wires in a microprocessor ased s!stem, which helps to carr! various information li9e #ATA, A##16'' and other "&:T1&8 /us Internal 67ternal '!stem /us It will not e directl! connected to "5; There will e separate data, address H control uses "5; /us It will e directl! connected to "5; The data and address ma! e multiplexed

"5; us

'!stem /us

8.

S,),' ,;' ("1*"2"#)*#' %2 X1 )*+ XE &"*( %2 8085. The cloc9 signal is supplied to the microprocessor 8085 through the pins M1 and M). Wuart> X1 "r!stal
P

! connecting @uart> cr!stal

5 X2

808

9. A;), "( P$%#'((%$ <5)#;"*'= #4#-'I L"(, ,;' 0)$"%8( 5)#;"*' #4#-'( B",; ",( T9(,),'(. The machine c!cles are the asic operations performed ! the processor, while instructions are e7ecuted. The time ta9en for performing each machine c!cle is e7pressed in terms of T+ states. The various machine c!cles are 1. ). 2. 3. 5. 6. -. &pcode fetch LLLLL.. $emor! 1ead LLLLL. $emor! Arite LLLLL. I%& 1ead LLLLLLL.. I%& Arite LLLLLLL. Interrupt Ac9nowledge LL /us Idle LLLLLLLL + + + + + + + 3%6T 2T 2T 2T 2T 6 % 1) T )%2T

10. L"(, ,;' 0)$"%8( )++$'(("*1 5%+'( "* 8085 B",; ,B% '@)5&-'( "* ')#;. Addressing is the method of specif!ing the location of data in an instruction. The different t!pes of addressing modes in 8085 are a, 6irect0 The data is stored in memor! and 16 it address of data in memor! location is specified in the instruction. 6g.0 8#A 3500, 8C8# 3)00 b, Immediate0 The re@uired data for processing is given ne7t to the &pcode, in the instruction itself. 6g.0 $?I A, 55 "5I 63, A#I 0A c, (egister0 The data is placed in a register and the register name is given in the instruction to access the data. 6g.0 $&? A,/ A## /, ';/ " d, (egister Indirect0 The data is stored in memor! and the 16+ it address of the data location in memor! is placed in a register pair. This register pair holding the 16+ it address is given in the instruction to access the data. 6g.0 8MI, C 3)50 $&? A, $ e, Implied0 The data location H the operation to e performed is given in the instruction itself. 6g.0 "$A, 1A1, M"C4

11. D'2"*' (,)#J )*+ (,)#J &%"*,'$. 'tac%0 A small portion of the 1A$ memor! is declared as stac9 and it is used for temporar! storage of the register contents, using instructions li9e 5;'C and 5&5. The contents are stored and retrieved in 8I=& (8ast In =irst &ut* form. 'tac% Pointer0 It is a 16+ it memor! pointing register, having the last address of the stac9 in 1A$.

1E. C%5&)$' CALL )*+ JMP "*(,$8#,"%*(. C#// Instruction0 67ecution of a "A88 instruction will transfer the program control from e7isting program to another program. ie., 'u program specified ! the 16+ it address in "A88 instruction will e e7ecuted. The called program should have 16T return instruction as its last instruction. Time ta9en for its e7ecution is . % 18 T $ain XXXXXXXXX XXXXXXXXX XXXXXXXXX "A88 addr16 XXXXXXXXX XXXXXXXXX XXXXXXXXX )*+ Instruction 67ecution of a <$5 instruction will transfer the program control from one location to another location within the same program. Time ta9en for its e7ecution is - % 10 T $ain XXXXXXXXX XXXXXXXXX XXXXXXXXX <$5 addr16 XXXXXXXXX XXXXXXXXX addr160XXXXXXXXX XXXXXXXXX addr160 XXXXXXXXX XXXXXXXXX XXXXXXXXX XXXXXXXXX XXXXXXXXX XXXXXXXXX 16T

1 . A;), "( )* "*,'$$8&, )*+ -"(, ,;' 0)$"%8( "*,'$$8&,( "* 8085. Interrupt0 Interrupt is a signal send ! an e7ternal device to the processor (or special instruction e7ecuted in a program*, to stop the e7ecution of the current process in the microprocessor and perform a particular tas9 (ie., data transfer* to the called device. ?arious CA1#AA16 interrupts are T1A5, 1'T-.5, 1'T6.5, 1'T5.5, I:T1 (5 :os* ?arious '&=TAA16 interrupts are 1'T0, 1'T1, 1'T) LL 1'T- (8 :os*

14. E@&-)"* ,;' 28*#,"%* %2 IN )*+ OUT "*(,$8#,"%*(. 67ecution of an I: instruction will transfer one byte of data from an Input de!ice to #ccumulator of microprocessor. 67ecution of an &;T instruction will transfer one byte of data from #ccumulator of microprocessor to an utput de!ice. 15. A$",' )* ALP 2%$ ,"5' +'-)4 8("*1 ) $'1"(,'$ &)"$ )0)"-)3-' "* 8085. $ain XXXXXXXXX XXXXXXXXX XXXXXXXXX "A88 6elay XXXXXXXXX XXXXXXXXX 6elay0 8MI #, data16 loop0 :&5 :&5 :&5 #"M # <:I loop 16T

The register pair used is 6$. The total time dela! made is as follows. &ne T+state D 1 % =internal T states (in e7ecution of one loop* D 3T E 3T E 3T E 3T E -T D )2T Total T1states > 5?T x data4; (stored in #6 register pair*

16. A$",'

)* )(('53-4 -)*18)1' &$%1$)5 ,% (,%$' ,;' #%*,'*,( %2 ,;' 2-)1 $'1"(,'$ "* 5'5%$4 -%#),"%* E000H. 5;'C 5'A 5&5 # $&? A, 6 'TA )000C + + + + 'tores the contents of #ccumulator = *lag register in 'tac% (estores the stored contents of stac% to 6$ register pair &o!e the contents of $ register to #ccumulator Contents of #ccumulator is no" stored to memory location 57778

1D. E@&-)"* ,;' I*(,$8#,"%* 2%$5), %2 8085. The 8085 have -3 asic instructions. The si>e of 8085 instructions can e 1 !te, ) !tes or 2 !tes. 1 /!te instruction has &pcode alone. ) /!tes instructions have 1 !te &pcode followed ! 8 it data. 2 /!tes instruction have 1 !te &pcode followed ! 16 it data.

18. D$)B )*+ -)3'- ,;' 2-)1( "* 2-)1 $'1"(,'$ %2 8085.