6

501*)

NTDVCR06

TECHNICAL TRAINING MANUAL

VIDEO CASSETTE RECORDER

M-653
ELECTRICAL

TOSHIBA AMERICA CONSUMER PRODUCTS, INC. NATIONAL SERVICE DIVISION TRAINING DEPARTMENT 1420-B TOSHIBA DRIVE LEBANON, TENNESSEE 37087 PHONE: (615) 449-2360 FAX: (615) 444-7520 www.toshiba.com/tacp

1997

CONTENTS
1. POWER SUPPLY CIRCUIT ................................................... 1-1 1-1. Outline ............................................................................. 1-1 1-2. Circuit Operation .............................................................. 1-1 1-2-1. Input Filter Circuit .................................................... 1-1 1-2-2. Primary Side Rectifier and Smoothing Circuit ......... 1-1 1-2-3. Switching Circuit ..................................................... 1-2 1-2-4. Current Limiter Circuit ............................................. 1-2 1-2-5. Snubber Circuit ....................................................... 1-2 1-2-6. Voltage Control Circuit ............................................ 1-3 1-2-7. Secondary Rectifier Circuit ..................................... 1-3 1-2-8. ON/OFF 9V Circuit .................................................. 1-4 1-2-9. EVER 5V ................................................................. 1-4 1-2-10. ON/OFF 5V Circuit ................................................ 1-4 2. KEY DISPLAY CIRCUIT ........................................................ 2-1 2-1. Microcontroller Unit .......................................................... 2-1 2-2. Display Unit ...................................................................... 2-2 2-3. Key Matrix Unit ................................................................. 2-2 2-4. Infrared-Red Receiver Unit .............................................. 2-2 2-5. Interface Unit .................................................................... 2-2 2-6. Resonator Circuitry .......................................................... 2-2 2-7. Reset Circuitry ................................................................. 2-2 3. SERVO CIRCUIT ................................................................... 3-1 3-1. Cylinder Servo Circuit ...................................................... 3-1 3-1-1. Cylinder Rotation Detection Signal (FG/PG) ........... 3-1 3-1-2. SW Pulse Generation Circuit .................................. 3-1 3-1-3. Phase Detection Control (APC) and Speed Detection Control (AFC) .............................. 3-2 3-1-4. Cylinder Control Output Circuit ............................... 3-2 3-1-5. fH Correction Circuit ................................................ 3-2 3-1-6. Pseudo V Output Circuit .......................................... 3-2 3-1-7. Motor Drive System ................................................ 3-2 3-2. Capstan Servo Circuit ...................................................... 3-3 3-2-1. FG Pulse Generation/FG Amplifier/ FG Schmidt Circuit .................................................. 3-3 3-2-2. CTL Signal Recording ............................................. 3-3 3-2-3. Phase Detection Control (APC) and Speed Detection Control (AFC) .............................. 3-3 3-2-4. Capstan Control Output Circuit ............................... 3-3 3-2-5. SP/LP/SLP Mode and Video System Detection ...... 3-4 3-2-6. Edit Recording ........................................................ 3-4 3-3. CAM Logic ....................................................................... 3-4 3-4. Viss Function ................................................................... 3-5 3-4-1. Operation of Analog Amplifier in lC501 (TMP90CN72EDF) .................................................. 3-5 4. LOGIC CIRCUIT .................................................................... 4-1 4-1. System Control ................................................................ 4-1 5. PIF CHANNEL SECTION CIRCUIT ...................................... 5-1 5-1. Outline ............................................................................. 5-1 5-2. Antenna Input Output Circuit ............................................ 5-2 7-1. Hi-Fi Audio Circuit ............................................................ 7-1 7-1-1. Outline of Hi-Fi Audio Circuit ................................... 7-1 7-1-2. EE Mode ................................................................. 7-1 7-1-3. Recording Circuit .................................................... 7-2 7-1-4. Playback Circuit ...................................................... 7-3 7-1-5. Dropout Correction Circuit ....................................... 7-3 7-2. Conventional Audio Circuit ............................................... 7-4 7-2-1. EE Mode ................................................................. 7-4 7-2-2. Record Circuit ......................................................... 7-4 7-2-3. Playback Circuit ...................................................... 7-4 5-3. Tuner, Channel Selection Circuit ...................................... 5-2 5-3-1. Channel Selecting Operations ................................. 5-2 5-3-2. Frequency Synthesizer Circuit ................................ 5-3 5-4. PIF Circuit ........................................................................ 5-3 5-4-1. PLL Complete Sync Detection System ................... 5-3 5-5. MTS (Multi-channel TV Sound) Detector .......................... 5-4 5-5-1. Outline .................................................................... 5-4 5-5-2. Operation ................................................................ 5-4 6. VIDEO CIRCUIT .................................................................... 6-1 6-1. Outline ............................................................................. 6-1 6-1-1. Background ............................................................. 6-1 6-2. Signal Flow ...................................................................... 6-1 6-2-1. EE Mode ................................................................. 6-1 6-2-2. Y Signal Record Path .............................................. 6-1 6-2-3. Color Signal Record Path ........................................ 6-2 6-2-4. Y Signal Playback Path ........................................... 6-3 6-2-5. Color Signal Playback Path ..................................... 6-4 6-3. Control Signal for Head Signal Amplifier .......................... 6-4 7. AUDIO CIRCUIT .................................................................... 7-1

1. POWER SUPPLY CIRCUIT

1-1. Outline
The power supply circuits adopts a switching power supply circuit of RCC self-excited type. Main key components include a 10 pins transformer and a switching transistors (BUL26XI/ 2SC4907), the secondary side has three rectifier circuits and output lines for KDB supply. In addition, it is stabilized by a series of regulator which are enough power to be supplied to each circuit. The block diagram is shown in Fig. 1-1-1. Voltage in Main Fuse Main Filter Rectifier Smoothing

Bridge diode

Snubber Circuit

Switch Mode Transformer

Rectifier Smoothing

Output Supply Voltage

Switching Transistor

Control Circuit

Rectifier Smoothing

Feedback Loop Fig. 1-1-1

1-2. Circuit Operation

1-2-1. Input Filter Circuit The input filter circuit consists of four capacitors and a line filter (T801) as shown in Fig. 1-2-1, and the noise input/output from the AC cord is suppressed.

1-2-2. Primary Side Rectifier and Smoothing Circuit The primary side rectifier and smoothing circuit rectify the output from the input filter circuit with diodes D802 D805, and supply DC voltage approximate 320V to the switching circuit after smoothing with the capacitor C805.

F801 C802 C801 T801 C804 C803

D804 D805

D802

Approx. 320V

D803 + C805

Fig. 1-2-1

Fig. 1-2-2

11

1-2-3. Switching Circuit The switching circuit is configured as shown in Fig. 12-3. When AC power turns on, the start-up current flows to the base of Q801 through R802, and Q801 turns ON. And then the collector current flows to Q801 through the winding LP of T802. The electromotive force generated in the LN of T802 by the current flow in the winding LP flows the drive current on the base of Q801 through D807 and R804, thereby the positive feedback is applied to Q801 and Q801 turns ON quickly. The collector current soon saturates and becomes constant. At this time, the electromotive force of the winding LN disappears and the counter electromotive force generates, and then Q801 turns OFF after the base of Q801 becomes reverse bias through R804 and C807. This operation is repeated.

1-2-5. Snubber Circuit The snubber circuit is shown in Fig. 1-2-4. The A portion of the waveform is suppressed as shown in Fig. 1-2-5. The A portion is suppressed by D806 turning ON and charging to C806, and it discharges from C806 passing through R803. L801 and C812 are for absorbing the switching noise of D806.

T802 DC in C806 R803

L801
T802 DC in R802

C812

D806

Q801
LP R804 Q801 Q803 Q802 D807 LN R810 Primary GND C809 R809 R808 C807

Fig. 1-2-4

A
C808 Feedback

Fig. 1-2-3

Q801 Collector voltage

1-2-4. Current Limiter Circuit The current limiter circuit protects Q801 by detecting the emitter current of Q801 by R810, adding it to the base of Q803, and limiting operation by decreasing base voltage of Q801, when the power plug is inserted to an AC outlet.

Fig. 1-2-5

12

1-2-6. Voltage Control Circuit The voltage control circuit is shown in Fig. 1-2-6. It stabilizes the secondary side output 5.6V. Assuming that 5.6V output increases, also the voltage increases since the voltage divided into R821 and R822 is applied to the base of Q825, and then diode of Q804 turns ON and the transistor of Q804 turns ON since VBE of Q825 becomes higher. And IC flows through R806 and turns ON Q802.
DC in

Q801 turns OFF, and the output voltage which is increased by cutting the output is reduced since the base current of Q801 is cut off when Q802 turns ON. C808, C810, R807, and R808 are for the phase correction.

T802 D822 5.6V + Q801 R804 Q802 R810 R808 Q825 C808 R807 R824 14V C828 + D831 R822 C810 Q804 R821 D807 R806 R823 C823

Fig. 1-2-6 1-2-7. Secondary Rectifier Circuit The secondary side rectification and smoothing circuits are provided and each supplies a DC voltage of 4.6V, EVER 37V, 26V (Vkk), & EVER 14V respectively. Another rectifier circuits also produce DC voltage by rectifying with diodes and smoothing with capacitors.

T802

RF825 F (+) D825 + C825 F() RF828 EVER + 37V D827 + C827

RF826

C822 26VKK D826 + C826

Fig. 1-2-7

13

1-2-8. ON/OFF 9V Circuit The ON/OFF 9V circuit is shown in Fig. 1-2-8. It turns ON with LOW when the power ON/OFF signal from the microcomputer is supplied to Q842. When the POWER ON/OFF signal is HIGH, the 9V voltage is not output since Q842 turns ON and Q841 turns OFF due to the base of Q841 is 0V.

1-2-10. ON/OFF 5V Circuit The ON/OFF 5V circuit is shown in Fig. 1-2-10. The base bias is applied to Q843 when the ON/OFF 9V started up, and then the ON/OFF 5V is output.

DC 14V Q841 R842 R841

ON/OFF 9V

DC 5.6V Q843 R844

ON/OFF 5V

37V D841 C842 + D842

D843

ON/OFF 9V

Q842 POWER ON/OFF SIGNAL

C844

+ D844

Fig. 1-2-10 Fig. 1-2-8

1-2-9. EVER 5V The EVER 5V is shown in Fig. 1-2-9. The base bias is applied to Q844 from EVER 14V and then the output EVER 5V.

5.6V

Q844 EVER 5V

R845 EVER 14V D845

Fig. 1-2-9

14

2. KEY DISPLAY CIRCUIT

The basic functional units of the Key Display Circuit (thereafter shall be called KDB) comprise of a microcomputer, display unit, key matrix unit, infrared receiver unit and interface unit. Other supportive circuitries are resonator circuitry and reset circuitry.

The KDB circuit reads key input data from tact-switches on the VCR and the KDB microcomputer (also referenced as display microcomputer) serially transfers these data to the Main microcomputer (which is also known as servo/logic microcomputer). Input data sent from the remote controller is received by the remote sensor and directly processed by the Main microcomputer. The fluorescent display tube is employed to display information on time, timer recording, channel selection, etc.

Universal VFD

TMP47C416F-H877 Display Microcomputer (4k MASK)

SIO

TMP90CS74DF-6621 Main Microcomputer (60k MASK)

IIC

EEPROM ST24C02B1 Tuner TMLH2X006A MTS PC1852 Hi-Fi IC TA1246F

A/D CONVERSION
pin (12) KEYIN 4 CH UP REC pin (11) KEYIN 3 CH DOWN POWER EJECT TEST 2 Simultaneous approved key pin (10) KEYIN 2 STOP pin (9) KEYIN 1 REW PLAY FF TEST 1 Key Matrix

PWM

IR Receiver

Fig. 2-1-1 Block diagram

2-1. Microcomputer
TMP47C416F is a CMOS 4-bit single chip microcomputer. It has a ROM size of 4k x 8bit and RAM area of 256 x 4bit. It comes with 44 pins and in plastic flat package (QFP).

The microcomputer itself contains CPU core, ROM, RAM, input/output ports, vacuum fluorescent tube driver circuit (24 bit), 4-bit A/D conversion input (4 channel) and serial interface with 8-bit buffer. It is running at a speed of 8 MHz, which means it has an instruction execution time of 1.0 s. Its supply voltage can be anything between 4.5 V to 5.5V.

Table 2-1-1 Display microcomputer

MICROCOMPUTER TMP47C416F-H877 ROM 4096 x 8 bit RAM 256 x 4 bit PACKAGE QFP44

21

2-2. Display Unit

The display tube (here onwards will also be known as VFD for Vacuum Fluorescent Display) employs a dynamic drive system which sequentially lights up each digit by using grid pulse and segment pulse signals sent from the display microcomputer. The VFD is a vacuum fluorescent tube and of triode type. Its operation is based on negative power supply. The filament voltages F (+) and F (-) are supplied by the power circuit to drive the fluorescent display.

2-6. Resonator Circuitry

Although the display microcomputer is capable of operating in dual clock mode, only high-frequency oscillation circuit is implemented in the VCR application. The system clock is obtained from the high-frequency clock and is generated by the 8 MHz ceramic resonator (XX 01).

2-7. Reset Circuitry

When a logic low signal is sent (via pin 55 of Main microcomputer IC501) to the RC circuit, an active low reset pulse is generated and applied to the display microcomputer. Once the logic signal goes high, the reset operation is released and the internal state is initialized. The display microcomputer then starts executing its instruction stored in the ROM area.

2-3. Key Matrix Unit

The display microcomputer has 4 channels of 4-bit A/D conversion input (KEYIN1, KEYIN2, KEYIN3 and KEYIN4) and these are formed into key matrix to be used for VCR key inputs. The display microcomputer then scans in operating key and for each read in key, it is compared and decoded data is sent to main system via serial transmission.

2-4. Infrared Receiver Unit

The infrared receiver includes a photodiode which detects infrared radiation from remote controller with a carrier frequency of 38 kHz. The demodulated infrared signal received is then decoded by the servo microcomputer and when the remote control code is identified, the function associated is processed.

2-5. Interface Unit

Two microcomputers are used in the VCR and data communications between them (Main and KDB microcomputers) are carried out through serial transmission. Serial data input from Main microcomputer to KDB microcomputer and serial data out from KDB microcomputer to Main microcomputer are pins SIO. M_D and SIO. D_M respectively. These data are transferred according to the serial clock (SIO. CLOCK) and strobe (SIO. STROBE) pins.

ICX01 KDB microcomputer

IC501 MAIN microcomputer

SIO.STROBE SIO.M_D SIO.D_M SIO.CLOCK

23 24 25 26

54 96 97 95

Fig. 2-5-1 KDB-MAIN microcomputers interface

22

3. SERVO CIRCUIT
The servo circuit controls the cylinder motor and the capstan motor. Control systems performing a central role and used in a conventional servo IC are incorporated in a single servo-microcomputer. The motor controls are processed via software programmed into its on-chip 40K ROM. The one chip microcomputer (IC501, TMP90CN72EDF-6621) used in the system control has a role to switch the mechanism and electronic circuits to operation modes and to monitor the operation status of the mechanism in each mode. Since these operations must be made in synchronization with the cylinder motor and the capstan motor in many cases, the operations are closely related to the servo ICs. The servo microcomputer integrates the servo control functions and the system control functions into a chip and the operations can be processed with software inside the chip and it features as follows. Higher control accuracy flexibly applicable to transient response. Automatic adjustments for various circuits. Reduction of external circuit components. Each circuit configuration in terms of function will be given in Table 3-1-1. Table 3-1-1 Configuration of servo circuit

3-1. Cylinder Servo Circuit

3-1-1. Cylinder Rotation Detection Signal (FG/PG) In a conventional system, a rotation speed detection signal (FG pulse) and a rotation phase detection signal (PG pulse) are separately detected. But in the newly developed cylinder motor, the rotation phase detection signal is superimposed on the rotation speed detection signal, thereby detecting both the speed and phase in one line. A hall element (Z662) detects variations of magnetism varied by rotation of the magnets mounted at outside of the cylinder motor rotor. This variation is translated into an amplified voltage and waveform shaped by an amplifier inside the cylinder driver IC (IC503, TB6515AP). The processed signal (pulses) is fed back via pin 1 of the driver IC. As can be seen from Fig. 3-1-2, the rotation detection signal consists of 1REF + 8FG pulses per one rotation, and the REF is used to detect the rotation phase and 8FG rotation speed. The sampling frequency in the speed system is: 30Hz x 8FG = 240Hz When the servo is locked (30Hz). 3-1-2. SW Pulse Generation Circuit The cyilnder rotation detection signal enters pin 47 of IC501, servo microcomputer. Inside IC501, the REF signal is detected and the SW pulse is created at a position delayed by the PG-adjusted data from rising edge of next FG. PG-adjusted data is obtained through PG adjustment where C-sync from pin 70 of IC501 is used as reference signal. The video SW pulse is necessary for all VCR, and HiFi SW is needed for reading of HiFi track. The relation of the SW pulses is shown in Fig. 3-1-2.

FUNCTION Cylinder Servo

CIRCUIT FG/PG input PWM control output Motor power supply FG waveform shaping CLT pulse waveform shaping PWM control output Motor power supply Reference voltage generation Auto tracking signal detection

Capstan Servo

Direction of rotation SA

Other

nly (O

(Head assembly) Fig. 3-1-1 shows the head mounting locations on the cylinder. As can be seen from the illustration, two video heads are mounted on the cylinder. Moreover, Hi-Fi audio heads are mounted in addition to the video heads and the phase is 60 from the video head center.

60

i HiF mo

CH1

CH2

ls) de
SB Rotor REF phase

Fig. 3-1-1 Head assembly (Top view)

31

Video signal P920

C.SYNC IC501 pin70

REF 1

REF

PG/FG Pulse IC503 pin1 or IC501 pin47 VIDEO SW Pulse P506 pin3 or IC501 pin89 HiFi SW Pulse IC501 pin91

1REV PG DELAY CH2 Video SW Pulse SB 6.5H SA CH1

Video SW Pulse CH2

SB

Fig. 3-1-2 SW pulse timing chart 3-1-3. Phase Detection Control (APC) and Speed Detection Control (AFC) Both the phase and speed detection are carried out inside the servo microcomputer IC501. In the phase detection, the REF signal entering into pin 47 is compared with the reference signal in their phases. In the record mode, a V sync signal extracted from the video signal and divided into a half is used as the reference signal. In the playback mode, an internal reference signal (30Hz) developed from the microcomputer clock (16 MHz) is used as the reference signal. This is the only difference in the record and playback modes in the cylinder servo. In the speed detection, speed variations are detected at a sampling rate of 8FGs (240Hz) per one rotation. 3-1-4. Cylinder Control Output Circuit Resultant voltage from the phase detection and the speed detection passes through comb filters, AFC and APC mixing filter, DC correction filter and outputs as a PWM (Pulse Width Modulation) square pulse of about 42 kHz at pin 100 of IC501. The signal is output at about 50% duty under the servo locked stably. The PWM output passes through a PWM carrier (About 42 kHz), smoothing filter (R519, C529, R520, C530) and enters pin 11 of IC503. The voltage is compared with a reference signal inside the IC and used to control the motor. That is, when the PWM output of H period is long, the motor is accelerated and decelerated when short. In the stop status, the output develops L. 3-1-5. fH Correction Circuit Since a tape runs rapidly under the cue/review mode, it is necessary to adjust rotation speed of the cylinder corresponding to the tape speed to maintain the relative speed between the cylinder and the tape. IC501 automatically adjusts the cylinder speed according to the tape speed under cue/review mode to make the fH correction. 3-1-6. Pseudo V Output Circuit To prevent V sync disturbance on the screen under special playback modes, a pseudo V signal is superimposed on the video signal. In this case, a phase control signal for these signals is output as a 3 state value signal at pin 76 of IC501, servo microcomputer. This signal is in synchronization with the SW pulse of the video heads and H output for the pseudo V insertion period. In a superimposing period, the signal shows L level. These signals are always sent to the video circuit and control the video signals. 3-1-7. Motor Drive System In a conventional cylinder motor, three hall elements detect phases of the rotator magnets and a coil to be powered is determined by identifying input status of three hall elements. In the motor employed this time, voltages are applied to three phase coils as a synchronous motor at a starting period, and when the motor is started once, a single hall sensor detects the varying magnetic field due to the motion of the cylinder rotor. A drive switching signal is thus developed and the phase switching is carried out by a counter present inside the IC. Moreover, PG/FG signals are developed inside the IC by using the signal detected by the hall element, thus working as conventional type pattern FG and PG coils.

32

3-2. Capstan Servo Circuit

3-2-1. FG Pulse Generation/FG Amplifier/FG Schmidt Circuit The FG pulse is a signal always obtained from the capstan motor as a speed feedback signal for the capstan. The FG pulse is obtained by detecting magnetism developed outside the rotor using reluctance elements. That is, FGA and FGB separated by 90 in phase are obtained. From this 2 phase shifted FG, a reverse rotation of the motor can be detected. They are also used in the intermittent slow operation, repeating the start and stop. The FGA pulse is used for the speed detection of the capstan, auto braking in the slow mode, and the tape remain detection. The FGA first enters the servo circuit through pin 6 of P502 and amplified in the amplifier of pins 40-42 of IC50l, waveform shaped inside IC50l, and used as a speed feedback signal. On the other hand, the FGB pulse enters the servo circuit through pin 4 of P502, amplified in the amplifier at pins 42-44 of IC501, and waveform shaped inside IC501. The FGB is used for detecting auto braking in the slow mode. The braking control is carried out by detecting phases of the FGA and FGB pulses inside IC501. The number of FG pulse is 360 per one rotation of the motor, and the frequency is about 1079 Hz in SP mode, 360 Hz in SLP mode when the servo is locked under normal playback mode and record mode. 3-2-2. CTL Signal Recording In the record mode, a 30 Hz CTL signal is created from a composite sync signal entering pin 70 of IC501 main microcomputer and a REC CTL signal is developed at pin 33. The duty of CTL signal is 60% in the H period. This signal flows into the CTL head and recorded on the CTL track of the video tape in a saturated level. The phase of the CTL signal recording (amount of ACE Head position shift) is set to: 25.36ms from CH1 (the rising edge of SW pulse) in SP mode. 21.42ms from CH1 (the falling edge of SW pulse) in SLP mode.

3-2-3. Phase Detection Control (APC) and Speed Detection Control (AFC) The phase detection and speed detection are carried out inside the servo microcomputer IC501. In the record phase detection, a 30 Hz signal obtained by dividing the FG signal entering pin 41 (amplified/waveform shaped inside IC501) is compared with a phase of the REF signal synchronized with 30Hz signal (obtained by dividing the V sync extracted from the video signal). On the other hand, in playback phase detection, a CTL signal entering pin 33 is amplified/waveform shaped inside IC501, and then compared with a phase of the reference signal obtained by tracking-delaying the REF signal. For speed detection, the FG signal entering pin 41 of IC501 is amplified/waveform shaped inside IC501 and then compared in the speed detection circuit. In the capstan which differs in that the target speed varies considerably depending on operation modes and the wide dynamic range, speed detection and phase detection are carried out by dividing the FG and CTL in the search mode. 3-2-4. Capstan Control Output Circuit Resultant outputs in the phase detection and speed detection enter the microcomputer, pass through comb filters, AFC+APC mixing filter, DC correction filter and correct in gain. Thus processed signal is used as a PWM (Pulse Width Modulated) rectangular waveform signal at pin 99 of IC501. With the servo stably locked, the output pin 99 develops the PWM output at a duty of 50%. The PWM output passes through a smoothing filter circuit (R514, C523, R515, C524) and enters the capstan unit through pin 9 of P502 with the reference signal at pin 5 of P502, and compared inside the drive IC, thus controlling the motor. When the H period is long at the PWM output terminal, the control is carried out to increase the motor speed and when the H period is short the motor speed is decreased. In the STOP mode, the output shows a L output. Forward or reverse rotation of the capstan motor is controlled by transferring a CAP F/R signal developed at pin 53 of IC501 to the drive IC through pin 7 of P502. That is, when pin 7 of P502 is L, the capstan motor rotates in clockwise direction and H in counterclockwise direction.

33

3-2-5. SP/LP/SLP Mode and Video System Detection SP/LP/SLP mode playback is possible with NTSC (3.58/4.43) system. The current playback tape speed is displayed through VFD (Vacuum Fluorescent Display) on the front panel or superimpose OSD on the screen. In playback, SP/LP/SLP mode is identified by number of capstan FG pulses within one CTL cycle. The corresponding I2C data to/from the video IC is output through pins 67/72 (common) while the I2C clock is through pin 88 of IC501. 3-2-6. Edit Recording Edit recording without picture disturbance at pictures jointed is carried out by performing a train of operations. That is, the capstan motor is reverse rotated by a specific amount as soon as the REC pause button is pressed, process in the servo microcomputer is set to the edit mode as soon as the pause is released, and then the recording is started again after making a phase matching with the CTL signal at the previously recorded part. In edit recording, the microcomputer counts the FG pulse number and controls so that the same number of FG pulse is obtained in rewinding the tape and matching the phase, thereby minimizing the overlap writing.

3-3. CAM Logic

The mechanical position of the tape motion and threading mechanism is given by the cam gear through signal lines CAM A, CAM B and CAM C. When the loading motor rotates the cam gear, the mechanical contacts are mode in CAM A, CAM B and CAM C. The combination of these three sensors (ON/OFF signal) provide the microcomputer with the current status of the mecha-deck.

Table 3-3-1
CAM C CAM B CAM A POSITION H L L I MODE SLOT IN, SLOT OUT, POWER OFF LOADING, UNLOADING REVIEW PLAY, REC, STILL, CUE, STOP (Drum ON), REC PAUSE, SLOW STOP (Drum OFF) FF, REW

H L

L H

H H

II III

IV

L L

L L

H L

V VI

CAM A

CAM B

CAM C

CAM Pos.

II

III

IV

VI

Fig. 3-3-1 Cam position chart

34

3-4. Viss Function

3-4-1. Operation of Analog Amplifier in lC501 (TMP90CS74DF-6621) IC501 (TMP90CS74DF-6621) is a newly developed control microcomputer and contains control signal amplifiers, schmidt circuit, control re-trigger function in intermittent slow playback, 2 phase capstan FG amplifier, etc.
RTG MM P.CTL LOGIC 46

Playback Mode Fig. 3-4-1 shows analog amplifiers and peripheral circuit in IC501 (TMP90CS74DF Series). Each capstan FG enters pins 41, 43 of IC501, passes through an inverted amplifier, inverted schmidt, and enters the servo as a speed feedback signal.

CTL OUT C517 0.47 R507 1M PDP C516 0.47 R506 1M

PDM

39

PDM

PDP
SWSHORT CTL AMP2 CTL AMP0 CTL AMP1 PHSPDUP

38

10k

10k

37
PLAY AMP

CNFB R504 220k

R503 470 + C513 47 6.3V C515 150pF

36 CAMP1 R505 680k 35 CAMP0 C BIAS IN 34

10k

SW BIAS
REC PATTERN GENERATOR

SW PLAY 33 SW REC DQ 1-5 5 REC AMP 5bit D/A CONV. AGND1 44 AVCC1 + AVCC1 CTL BIAS AMP 32

33k

R/P R502 CTL 820 R501 4.7k

W701A 2 CTL I/O 3 GND C511 2200pF 1 CTL BIAS CTL HEAD

C BIAS +

C512 47 F16V

CFGB AMP C521 C520 100p 1 50V + R510 1.8k C522 47 6.3V + FROM CAPSTAN MOTOR 4 FGB 6 FGA

R511 56k 43 CFGB IN

AGND1 C-FG LOGIC

CFG BIAS AMP 42 R513 1K 41 + CFGA IN

R509 56k 40

+ R508 C518 1.8k 1 50V C519 100p

P502 5 CAP REF

CFGA AMP

Fig. 3-4-1 Analog amplifiers and peripheral circuit in IC501

35

One end of the control head (pin 1 of W701) is biased at a specific level by pin 32 of IC501. The CTL signal from pin 2 of W701 enters pin 33 of IC501 and amplified a built-in OP-Amp. The amplifier output developed at pin 35 of IC501 (0 output terminal) and the gain is determined by a resistor connected between pin 35 of IC501 (0 output terminal) and pin 37 of IC501 (negative feedback terminal). The amplifier gain is peak-detected inside the microcomputer and the schmidt operation is started at a position of 50% peak. The peak detection is controlled by detecting a peak of the amplifier output and by varying voltage applied to capacitors C516, C517 at PDP terminal (pin 38 of IC501) and PDM terminal (pin 39 of IC501). Amount of leakage of the capacitors at PDP terminal and PDM terminal is determined by R506 and R507. Furthermore, AMP0, AMP1, AMP2 and SW SHORT switches are provided inside the microcomputer to switch the CTL amplifier gain according to a mode used. Since the CTL signal is used in a wide dynamic range over the SLP playback and FF/REW, if the FF/REW operation is carried out with the gain set in the playback mode, a waveform distortion will occur and the duty of CTL will vary. To prevent this, above switches inside the microcomputer are used to change the gain. In this case, the amplifier output develops at the amplifier 1 output terminal (pin 36 of IC501) and the amplifier gain is determined by a resistor R504 connected between the amplifier 1 output terminal (pin 36 of IC501) and the negative feedback terminal (pin 37 of IC501). The reproduced signal is sent to the logic circuit inside the IC, processed in the schmidt circuit, and the waveform shaped output develops at the CTL output terminal (pin 46 of IC501). This signal is fed to the capstan phase control circuit and the CTL duty cycle detection circuit inside the microcomputer.

36

4. LOGIC CIRCUIT
4-1. System Control
In the VCR, complex mechanism, video, audio, servo circuits, etc. must be operated in specified timings matched each other. The system control circuit performs entire controls for the VCR. An automatic stop function is also provided to protect important tape if a trouble occurs on the complex mechanism and the electrical circuits.

For this purpose, status of each part of the mechanism is always monitored with various sensor switches, and the microcomputer controls collectively the unit so that the best condition is kept. Moreover, the microcomputer controls signal switchings for each circuit according to the mechanism status.

Main microcomputer Loading motor control (Voltage, direction) Remote control Remote

Loading motor drive

Loading motor

Cassette-out/REC-inhibition Detection of cassette-out position & broken safety tab Mode sensor (Detecting of mechanical mode position)

Cassette-in SW REC-inhibition

VCR CH H M S Start sensor Tape start sensor ICX01 DISPLAY MICROCOMPUTER End sensor Tape end sensor Take up KEY DATA MODE DATA Abnormal reel rotation FF/REW speed control Abnormal reel rotation FF/REW speed control Tape

Cam SW

Tape end LED

T reel sensor S reel sensor

Supply

Key matrix

Front button input

SERIAL TRANSMISSION

Current control Capstan motor control (Speed direction) Capstan motor drive

M Capstan motor

Reset signal Reset circuit active POWER FAILURE POWER OFF ON ABNORMAL

FG.A pulse FG.B pulse CTL pulse (Linear time counter) REC control

FG A FG B Control

AUDIO VIDEO

I2C BUS

Cylinder motor control POWER ON/OFF REC mute TV/VTR

Cylinder motor drive

Cylinder motor

PG/FG pulse

PG/FG

Fig. 4-1-1 System control block diagram

41

5. PIF CHANNEL SECTION CIRCUIT

5-1. Outline
This circuit selects a desired broadcasting wave among ground wave TV signals sent from antennas, develops stabilized video and audio signals, and sends them to the video and audio circuits. The output signals from the video and audio signals are converted into a signal for channel 3 or 4 so that it can be received by a conventional TV set.

A PLL complete sync detection system is employed as the video detection system to improve waveform distortion characteristics and picture quality characteristics such as DG, DP, etc. Configuration (1) Antenna input/output circuits (2) Tuner, channel selection circuits (3) PIF/SIF circuits Above three circuits are integrated into a 3-IN-1 tuner (TMLH2X006A)

3 IN 1 TUNER
ANT IN
ANT IN

ANT OUT
RF OUT

H007 TMLH2X006A AUDIIO IN 4.5MHz OSC CH SW 1 2 RF AUDIO IN

S001 CH SW

SPLITER

RF

SW

LPF

RF MODULATOR HA11560FP SAW RESONATOR

MB (5V) 3 CONTROL VIDEO IN 4 5 TV/VCR RF VIDEO IN

PLL PC44818D MIX/OSC AJ605A HPF TUNING RF AMP RF AMP RF AMP TUNING

PB (5V) 6 TU (32V) 7 S.CLOCK S.DATA 8 9 10

ON/OFF 5V EVER 37V SCL I SDA I

BPF

TUNING

TUNING

IF AMP

ADDRESS

LPF

TUNING

TUNING

N.C. 11

IF OUT

12 ON/OFF 9V AUDIO OUT

+B (9V) 13 IF TUNE PIF/SIF LA7577N TRAP IF AMP VIDEO CIRCUIT FM DET 4.5MHz BPF GND 15 AFT 16 Q001 SW AFT AUDIO OUT 14

AFT

N.C 17 VIDEO OUT 18 TUNER VIDEO OUT

Fig. 5-1-1 Block diagram of 3-IN-1 tuner

51

5-2. Antenna Input Output Circuit

The antenna input/output circuit consists of a spliter, RF modulator and an antenna switch circuit. The spliter, antenna switch circuit, and the RF modulator are integrated into one unit. The spliter distributes a TV signal from the antenna to built-in tuner and the antenna switch. (Input impedance is 75W , distribution loss is about 4 dB in VHF band and about 5 dB in UHF band.) The antenna switch selects either one of the outputs from the RF modulator and the spliter output according to a selection of the TV/VCR switch on remote controller. The antenna switch output develops the spliter output when the TV is selected or the RF modulator output when the video is selected. The antenna output terminal is connected to the input terminal of the TV receiver. As the RF modulator output can be switched to channel 3 or channel 4, switching to a vacant channel does not cause beat noises on the screen. The output level of the RF modulator is about 66 dB (V) (peak value at 75W terminated).
Video signal ANT output Audio signal

5-3. Tuner, Channel Selection Circuit

The channel selection circuit controls the tuner so that it can tune in a desired broadcasting to receive it. This unit employs a frequency synthesizer (FS) system to obtain more stabilized receive frequency and less variation of picture quality. 5-3-1. Channel Selecting Operations The main microcomputer performs following operations. (1) Develops an audio mute pulse (A-Mute) and sets a channel. (2) Obtains a broadcasting frequency corresponding to the channel number. (3) Updates the channel display. (4) Calculates an estimated broadcasting frequency and the band data according to the channel number. (5) That is, the computer varies frequency data and reads the AFT data every time to search the broadcasting frequency. When the frequency is found, the computer locks the frequency data. (6) Changes the audio mute output to high when the channel selected is no signal.

ANT input

DEVIATION

RF MODULATOR Antenna 8W TUNER IF Signal

Fig. 5-2-1
Tuner section

INPUT SYNC. CIRCUIT RF/AGC AMP CIRCUIT TUNING CIRCUIT BETWEEN STAGES VT output

PLL section STANDARD OSCILLATION 4MHz PRESCALLER CIRCUIT LOW PASS FILTER

IF output

MIX.CIRCUIT

PLL CIRCUIT

Data Clock

LOCAL OSCILLATION CIRCUIT VT input BAND SW

Fig. 5-3-1

52

5-3-2. Frequency Synthesizer Circuit When a specified voltage is applied to the tuning voltage terminal (VT) of the ET tuner (Fig. 5-3-1), the ET tuner tunes in a desired frequency, thereby receiving the broadcasting station. In a channel selection circuit using the frequency synthesizing system, the tuning frequency of the ET tuner is picked up as a signal from the local oscillator and the signal is processed in a frequency divider operating at a division ratio corresponding to the receive channel. The local oscillator signal processed (counted down) in the divider and another divided signal of a fixed reference signal generator which has a very precision accuracy are compared in their phases, and the tuning voltage is varied according to the phase difference to keep the receive frequency at a constant value. (This closed loop is called a PLL loop.) Accordingly, TV broadcastings can be received with very accurate and stabilized condition. The tuner used in this unit has the PLL circuit (Phase Locked Loop). The local oscillator in the tuner block is connected to the PLL block through a PC board pattern. The tuning voltage VT is also connected to the PLL circuit through a PC board pattern, thus constituting the PLL circuit. A band data of 4 bits and division data which determine a receive frequency (Main counter data + XXXX counter data: 15 bit) are transferred to the PLL circuit through the I2C bus lines. The minimum resolution by the division data is 62.5 kHz.

The sync carrier for the sync detection is developed by a tank circuit tuning in the limiter and P carrier. On the other hand, in the PLL complete sync detection system, processing method to develop the sync carrier is different. That is, it uses a VCO (Voltage Controlled Oscillator) output inside the IC. The VCO works as a part of PLL with a APC DET (phase comparator) so that it is locked to the P carrier from the tuner. The PLL loop filter is set to about 100 kHz to reduce phase modulated components caused at rising of a waveform, thus reducing the waveform distortion by more than that in the quasi sync detection system.
Quasi sync. detection IF input IF AMP LIMITER

DET

Video output

PLL sync. detection IF input IF AMP DET Video output

APC DET

VCO

5-4. PIF Circuit

The TV signal sent from the antenna circuit enters the tuner. The tuner develops IF signals corresponding to the channel selected. The IF signals pass SAW filters, enter an IF detector IC and video and audio signals are detected. 5-4-1. PLL Complete Sync Detection System Description on the PLL complete sync detection system will be given by referring to a quasi sync detection system. In the quasi sync detection system, an IF signal output from a tuner enters a sync detector in passing through a SAW filter and an IF amplifier as shown in Fig. 5-4-1.

Fig. 5-4-1 In a conventional quasi sync detection system, there is a defect which makes black vertical stripes thicken. Moreover, the PLL sync system is superior to the quasi sync detection system in DG (Differential Gain), DP (Differential Phase), cross color, sound beats, etc.

New type

White

Black Conventional Time

Fig. 5-4-2

53

5-5. MTS (Multi-channel TV Sound) Decoder

5-5-1. Outline The MTS decoder demodulates MTS composite signals demodulated in the Tuner module (H001) and sendsstereo sound outputs L and R, and SAP signals to the audio circuit. The MTS module consists of a MTS decoder IC PC1852 controlled via I2C bus and associated circuits. The PC1852 contains a stereo demodulation circuit, SAP (Second Audio Program demodulation circuit), dbx circuit, matrix circuit, etc. The MTS composite signal to be entered into the MTS module has frequency spectrums as shown in Fig. 5-51. (1) L-R and SAP signals are encoded with dbx-TV NR (Noise Reduction). (2) L-R signal is a carrier suppressed double sidebands AM signal. (3) SAP is a FM signal with frequency of deviation of 10 kHz from center of 5fH. (4) TELEMETRY signal is not demodulated.
Peak deviation (KHz) 50 AM-DSB-SC

5-5-2. Operation (1) L+R (MAIN) The MTS composite signal enters MPX IN terminal pin 7 and the SAP and TELEMETRY signals are suppressed in passing through a STEREO LPF. Next, the pilot signal is canceled. Finally, the L-R signal and the SAP signals are eliminated in passing through the MAIN LPF, frequency response is adjusted to a flat response in passing through an emphasis circuit, and then fed to a matrix circuit. (2) L-R (SUB) The L-R signal passes the same circuits as the L+R signal passes up to the pilot cancellation stage. Since the L-R signal is a carrier suppressed double sideband AM signal, it lacks carrier signal. So the carrier signal must be restored. This restoration is conducted using the pilot signal. Thus developed carrier signal (quasi sine wave) is used to demodulate the L-R signal. The demodulated L-R signal enters the SUB LPF and residual high frequency components are removed in passing through the SUB LPF. Then the L-R signal enters the dbx-TV block through the NR-SW circuit. (3) SAP The SAP is a FM signal with the center frequency of 5fH. First, only the SAP signal is extracted using a SAP BPF. Then, the SAP is frequency detected. Finally, high frequency components are removed from the SAP signal in passing through the SAP LPF, the frequency response is adjusted to flat, and then the SAP signal is sent to the dbx-TV block through the NR-SW circuit.

PILOT

25 L +R

5 0 fH

L R dbx-TV NR 2fH 3fH

SAP TELEMETRY dbx-TV NR FM 3KHz FM 10KHz f 4fH 5fH 6fH 6.5fH fH 15.734KHz

Fig. 5-5-1

(4) Mode identification The mode identification is carried out by detecting amplitude of the pilot signal. The SAP identification is carried out by detecting 5f H carrier and noises components around 20 kHz in a stage following the FM detector. When stereo signals or the SAP signal are detected, the information is updated in the contents of the read register. (See Table 5-5-2.) (5) Mode selection The write register of subaddress 06H controls the output terminals, pins 25 to 27 according to broadcast signals and signals from the SAP SET SW to select the output signals. (See Table 5-5-1 and 3.)

54

5-5-3. I2C BUS Commands (1) Subaddress list Table 5-5-1 Write register (Command list)
SUBADDRESS MSB D7 00H 0 D6 During noise detection Stereo/SAP output stop 0: SAP OFF 1: Stereo, SAP OFF 01H 0 fH monitor ON/OFF 0: OFF 1: ON 02H 0 Pilot canceler ON/OFF 0: ON 1: OFF 03H 04H 05H 0 0 0 0 0 5 fH monitor ON/OFF 0: OFF 1: ON 06H 0 0 Normal track Normal track SAP1/SAP2 Stereo/SAP switch
Note

LSB D5 D4 D3 Input level setting D2 D1 D0

Stereo VCO setting

Filter setting

Low-band separation setting High-band separation setting SAP VCO setting

Forced monaural 0: OFF 1: ON

Mute

output select: 1 output select: 2 0: Internal SAP 1: External SAP 0: SAP 1: Monaural

switch 0: Stereo 1: SAP

0: SAP1 1: SAP2

0: ON 1: OFF

Note Output when SAP1 or SAP2 is selected is as follows:

Lot pin (L-channel output) SAP1 SAP2 Monaural (L + R) SAP SAP Rot pin (R-channel output)

Table 5-5-2 Read register

MSB D7 D6 D5 D4 D3 D2 D1 LSB D0

Broadcast status Power-on reset Stereo pilot SAP signal

Receive status Noise detection Stereo broadcast SAP broadcast reception reception

1: Detect

0: Not available 0: Not available 0: Not available 0: Not available 0: Not available 1: Available 1: Available 1: Available 1: Available 1: Available 1 1

55

5-5-4. Mode Matrix (1) L-, R-channel output (LOT, ROT pins) matrix Table 5-5-3 Mute OFF (Write register, subaddress 06H, bit D0 = 1)
BROADCAST MODE Forced monaural ON/OFF WRITE REGISTER Stereo SAP1 /SAP /SAP2 Stereo /SAP output stop Subaddress 06H Bit: D1 Monaural Stereo 0 Bit: D2 Bit: D3 Subaddress 00H Bit: D6 0 1 1 Monaural+SAP 0 0 1 0 0 1 1 0 1 1 Stereo+SAP 0 0 0 1 1 0 0 1 1 0 1 1 L+R 1 1 0 0 0 L+R SAP L+R 1 1 1 1 0 0 1 0 0 1 L L L+R SAP L+R 1 1 1 1 L+R R R 0 1 1 1 1 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 1 L+R SAP L+R 0 0 1 1 0 0 1 0 0 1 L+R L+R SAP L+R 0 1 0 1 0 0 1 L L+R L+R R Bit: D6 Bit: D5 0 1 1 0 0 0 Bit: D3 0 1 1 0 1 0 0 0 1 0 0 0 0 1 Bit: D2 0 0 0 Bit: D4 0 0 1 OUTPUT L-ch signal R-ch READ REGISTER Broadcast status SAP Reception status Stereo SAP Noise detection

signal Stereo pilot

switch switch

output output (LOT) (ROT)

signal broadcast broadcast reception reception

Remarks: 1. Shaded areas represent weak electrical field. 2. : Dont care

56

(2) Normal output (NOT pin) matrix Table 5-5-4 Mute OFF (Write register, subaddress 06H, bit D0 = 1)
BROADCAST MODE Normal track Output selection 2 Normal track Output selection 1 WRITE REGISTER Forced monaural ON/OFF Subaddress: 06H Bit: D4 Monaural Stereo Monaural+SAP 0 Bit: D5 0 Bit: D1 0 Bit: D2 0 1 1 1 1 Stereo+SAP 0 0 0 0 1 1 1 1 Bit: D3 L+R L+R L+R SAP L+R External SAP* L+R L+R SAP L+R External SAP* L+R Stereo/SAP switch SAP1/SAP2 switch OUTPUT Normal output (NOT pin)

Remark Caution

: Dont care * : SAP signal input from ESA pin. All normal outputs with weak electrical field are L+R.

57

5-5-5. Block Diagram of MTS Decoder IC (PC1852)

4.7 F

1K 0.1 F 22 F

1 C GND

SCL

SDA

GND 1F

L signal output

R signal output

Normal output 1F

1F 6 5 4 3 2 17 16 15 14 28 27 26 25 24

1/2 Vcc

12C Bus Interface

Matrix Selector

Matrix Selector

Matrix Selector

Stereo Demodulation Block

Offset Absorption

Stereo/SAP Switch SAP Demodulation Block dbx Noise Reduction Block

D/A D/A

Input Attenuator

Filter Adjustment

7 2.2 F

10 0.1 F

11

12

13 1F

18

19 3k 3.3 F 1F

22

21

20 23 5.1k 10 F

0.047 F 0.47 F Composite signal input 60k

0.1 F

9V External SAP

16.6k

1F

Fig. 5-5-2 Block diagram of MTS decoder IC (PC1852)

58

6. VIDEO CIRCUIT
6-1. Introduction
6-1-1. Background The concept is to reduce component count without any compromise in the product quality. To achieve this in video circuitrys, major video functional blocks such as DOC, CCD delay line, OSD insert, are all packed into the video IC (TA1251F). Furthermore, it also has built-in linear audio circuit to process conventional audio. This TA1251F is designed exclusively for use with the NTSC color television system. It uses parallel control to switch each mode and characterisctics. No I2C bus architecture is employed. Fig. 6-1-1 shows a block diagram for video system configuration.
Video OUT Video Line IN OSD Video IN TMLH2X006A 3 in 1 Tuner RF ANT IN RF ANT OUT

6-2. Signal Flow

6-2-1. EE Mode The CVBS signal comes from video line input (phono jack). The chosen video is input to video processing IC201 TA1251F pin 53. The video signal at pin 53 is switched inside IC201 according to the input select line (pin 6). The level of the video signal is controlled by the AGC circuit and outputs at pin 49. 6-2-2. Y Signal Record Path The video signal that enter pin 53 of IC201 passes through an AGC amplifier and then through main LPF to separate the Y signal from the color. The Y signal passed through the DPE, non-linear emphasis inside IC201 is then emphasized by the main emphasis circuit at pin 55 and 56. The level of the emphasized record Y signal is controlled through white clip/dark clip circuits before being FM modulated. The modulated signal will pass through a FM equalizer before mixing with record color and outputs at pin 62. (Refer to Fig. 6-2-1.)

TA1251F

Drum Interface

Drum CGWA6NM

Fig. 6-1-1
L207 C252 C238

REC FM OUT

R214 R213

R210 Video Line IN C234

C232 Video OUT OSD Video IN C-Sync OUT

62

56

C237

55

53

51

AGC 50 FIL

49

47

44

AGC DET FM MOD RE-FM EQ FM AGC MAIN EMPH AGC PV/PH/ OSD FB clamp MAIN LPF

Clamp Sync sep

DPE

YNR DOC NL EMPH

Clamp

IC201 TA1251F
Fig. 6-2-1 Y signal record path

61

6-2-3. Color Signal Record Path The color signal is separated from the input video signal by a band pass filter inside IC201. The separated color signal (C signal) passes through the ACC circuit, burst emphasis circuit inside IC201 and then down converted to 625 kHz in the main converter circuit. Refer to Fig. 6-2-2.

R210 REC FM OUT Video Line IN C234

C232 Video OUT OSD Video IN C-Sync OUT

62

53

51

50

AGC FIL

49

47

44

AGC DET

REC-Y FM

AGC

PV/PH/ OSD

Clamp

Sync sep

FB clamp

MAIN LPF

REC-C LPF Burst EMPH REC C Lev

Sub BPF

MAIN CONV

ACC AMP

MAIN BPF

C-ACC DET

AGC DET

IC201 TA1251F
23 C214 22 C212

Fig. 6-2-2 Color signal record path

62

6-2-4. Y Signal Playback Path The playback Y signal entered at pin 63 of IC201 will pass through a FM AGC amplifier, playback FM equalizer, a color trap, double limiter circuit, FM demodulator and output at pin 55. The demodulated Y signal at pin 55 goes through the main de-emphasis (external circuit) and returns to pin 58 of IC201. Then the Y signal will be amplified, pass through the main LPF, nonlinear de-emphasis circuit, YNR and output at pin 41. The playback, Y signal enter Y-comb/DOC circuit through pin 43 and 1H delayed signal is developed by a CCD circuit through pin 39 of IC201. After the Ycomb circuit, the Y signal will pass through ANR and mixes with PBC. The mixed signal passes through a quasi H and V sync signal insertion circuit and amplified before output at pin 49 of IC201. Refer to Fig. 6-2-3.

(1) 1H CCD and Y-comb filter In Playback mode, each video head scans its magnetic track, and also picks up some FM signal from an adjacent track. This cross-talk of FM signal also contains other line frequency related noise components, and all these noise have to be reduced. The basis of the noise reduction scheme is to shift the recorded FM signal by 7.8 kHz or 1/2fh so that each adjacent magnetic track has a half line frequency shift with respect to its neighbor. Because of this, when Playback, the cross-talk FM signal will have 180 degrees phase different as compared with the original signal after passing through the 1H delay circuit. Therefore, FM cross-talk can be eliminated by adding the two signals. At the same time, other line frequency related noise is also reduced by this process due to the fact that noise is uncorrelated between original and delayed signal. This feature is incorporated inside the IC201 and can monitor at pin 39, pin 37, and pin 43.

PB FM IN

C242 DeEmphasis 63 55 58

C254 C225

59

40

39 5V

C Trap

Sub LPF

PB AMP

1H Delay 37 Q208

PB FM AGC

FM DeMod

FB Clamp R223 C227

PB FM EQ

Double Limiter

MAIN LPF

YNR DOC

GCA 43

NL Deemph PBY ANR PV/PH/ OSD 49 V-out

PBC

Clamp

IC201 TA1251F
Fig. 6-2-3 Y signal playback path

63

6-2-5. Color Signal Playback Path The FM signal enters pin 64 of IC201 for color processing. In IC201, the C signal passes through another LPF, a Pre-ACC amplifier, burst de-emphasis circuit and converted into the 3.58 MHz band signal. The converted C signal will pass through a trap, SubBPF and output at pin 26 to IC201. The signal enters the C-comb filter at pin 28 and output at pin 30 of IC201. The color signal reenters at pin 24 of IC201 and passes through the main BPF, ACC amp and through capacitor C208 at pin 17 and pin 15 of IC201. The signal then, mixes with PBY and output at pin 49. Refer to Fig. 6-2-4.

6-3. Control Signal for Head Signal Amplifier

The REC FM Y is sent out through pin 2 of PV01 to head amplifier for recording. The composite sync signal output from pin 44 of IC201 goes into pin 4 of PV01. The video SW appears at pin 5 of PV01 to select the required heads for operation

PB FM IN

C243 Vcc 64 C-Comb output C-Comb 30 Q207

PB-C LPF

R222 Ch. ACC 28 C215 Y/C Timing B-Deemph Main CONV Trap Sub LPF 26

PV/PH/ OSD

PBY Clamp PBC

ACC AMP

Main BPF

ACC DET Color Input after C-comb

49 Video OUT

15 C208

17 PBC

22 C212

24

Fig. 6-2-4 Color signal playback path

64

7. AUDIO CIRCUIT
7-1. Hi-Fi Audio Circuit
The Hi-Fi audio circuit exists on the Main Board. 7-1-1. Outline of Hi-Fi Audio Circuit In this Hi-Fi audio process IC (TA1246F), the input switch, output switch, noise reduction circuit, FM modulation/demodulation circuit, and the mute circuit are combined in one chip. (The conventional audio circuit is eliminated from TA8863 which has been used on the current Hi-Fi VCR.) In this IC, each mode and characteristic can be switched by I2C-bus from the main microcomputer. Table 7-1-1 shows the operation and function on this IC. The Hi-Fi audio circuit consists of the FM modulation/ demodulation circuit which performs record and playback of audio signal with FM modulation, the noise reduction circuit, the input/output switching circuit, and etc. In the record mode, the audio signal entered from the line input is recorded with the conventional and Hi-Fi audio. The Hi-Fi audio can be recorded and played back in stereo mode, and the conventional audio is recorded and played back in monaural mode.

7-1-2. EE Mode (1) Audio input/output switching circuit The line input entered from the P920 is input to the input switching circuit of IC920, and selects the signal to be recorded by the data of I2C-bus. This recording signal is supplied to the Hi-Fi recording circuit, and a part of the signal is supplied to the monitor switching circuit as EE system signal. In the monitor switching circuit, the output signal is selected from the EE audio signal and the conventional audio signal. The output signal of this monitor switching circuit is supplied to the output switching circuit, and it is output from pin 11 and 13 after selection of L ch, R ch or stereo mode. (2) Audio mute circuit The mute circuit is provided in the IC920 inside to suppress noises generated by the power ON/OFF and mode switching. When output from pin 10 of IC920 is Hi, pin 12 and 14 are grounded, and then the line output signal is muted.

Table 7-1-1 Operations and functions of Hi-Fi audio process IC

LOCATION No. IC920 IC NAME TA1246F OPERATION Input Switching FUNCTION L+R MIX output for Conventional Audio

Output Switching

Output Switching Circuit Mute Switching Circuit Noise Reduction Circuit (NR Emphasis, Built-in NRLPF) Emphasis Circuit Audio Clip Circuit FM Modulation/Demodulation Circuit AGC Circuit BPF Dropout Detection Audio Tracking Circuit Noise Correction Circuit

Noise Reduction

FM Modulation/ Demodulation

71

IC920 TA1246F
From R ch input switching circuit Conventional Audio From R ch monitor switching circuit

31
Conventional Audio Circuit

35

N.A Input Switching Circuit

L ch Monitor Switching Circuit

L ch Output Switching Circuit

11 12
Line Output L ch (IC501) Audio Mute : Hi

EE
Line

47

L ch Input Switching Circuit

L ch Recording Circuit

Mute Switch

10

Fig. 7-1-1 Signal flow in I/O and mute circuits (L ch) (R ch has the same circuit components) 7-1-3. Recording Circuit In the record mode, the audio signal selected by the input switching circuit is input to the Hi-Fi audio recording circuit. In Hi-Fi audio recording circuit, the signal is applied to VCO passing through PNR circuit and 20kHz LPF. Also, the LPF output signal is fed back to the PNR circuit passing through the peak detection circuit, and controls the amplifier gain and the characteristics of the PNR circuit. The audio signal to be entered the VCO is compressed by a square root ration passing through the above PNR circuit and peak detection circuit. The audio signal applied to VCO is modulated with frequency. FM carrier frequency is L ch 1.3MHz and R ch 1.7MHz. As the carriers and the frequency deviation have been adjusted in fabricating the ICs, no adjustment will be necessary. The audio signal modulated with FM is added to FM signal of the opposite channel after passing through the FM LPF, and it is output from pin 22, and then sent to the pre-amplifier in the cylinder.

IC920 TA1246F
To Audio Monitor Switching Circuit 9 Input Switching Circuit Emphasis element Peak Detection Circuit 8 7 6 PNR Circuit 20kHz L.P.F. VCO FM L.P.F. 22 Audio FM Modulation Signal Smoothing Capacitor FM Signal of Opposite Channel

Waighting Element

Fig. 7-1-2 REC signal flow in Hi-Fi audio circuit (L ch) (R ch has the same circuit components)

72

7-1-4. Playback Circuit The playback audio FM signal to be output from the pre-amplifier in the cylinder is input to pin 25 of IC920, and input to the AGC amplifier. The playback audio FM signal amplified by the AGC amplifier is input to the BPFs (Band Pass Filters) of 1.3MHz and 1.7MHz, and then it is demodulated by the phase sync circuit consisting of each VCO and the phase detection circuit. The demodulated audio signal is input to the 20kHz LPF after switching noises are corrected by the switching noise correction circuit. The signals except the audio band are eliminated by the 20kHz LPF, and the amplifier gain and the characteristics by the PNR circuit are adjusted, and then the audio signal is sent to the monitor switching circuit after applying de-emphasis. Also, the output of the 20kHz LPF is input to the peak detection circuit, and the peak detection is performed after being weighted. The audio signal which the peak detection is performed is added to the PNR circuit with the inverse characteristics against the recording characteristics, and the amplifier gain of the PNR circuit is adjusted. In result, the audio signal to be input to the monitor switching circuit by the PNR circuit and the peak detection circuit has the characteristic expanded in the square power. This expansion characteristic has the inverse characteristic against the compression characteristic for recording, and it returns back to original signal level though process of the record and playback.

7-1-5. Dropout Correction Circuit The playback audio FM signal to be input from pin 25 of IC920 is amplified by the AGC amplifier, and input to BPF. The gain of the AGC amplifier is adjusted by using this BPF output. Also, the BPF output of this 1.7MHz is used for the dropout detection. The dropout detection signal outputs the timing noise correction pulse specified in IC inside, and noises are corrected. Also, when the dropout exceeding the time specified with the external time constant is detected, the Hi-Fi audio signal is muted by operating the mute circuit of IC920 inside, and the conventional audio output condition is set forcibly. The following shows the cases in which the forced normal switching will start to operate: (1) When playing back a tape where Hi-Fi is not recorded. (2) When the tracking adjustment is not correct.

IC920 TA1246F
BPF NTSC: 1.7M Output Switching Circuit Monitor Switching Circuit 9 Switching Noise Correction Circuit 20kHz LPF PNR Smoothing Capacitor Peak Detection Circuit 8 7 6 Weighting Element 11 Line Output L ch

Playback FM Signal Input

25 AGC AMP Phase Detection Circuit

BPF NTSC: 1.3M

Emphasis Element

VCO

Fig. 7-1-3 Playback signal flow in Hi-Fi audio circuit (L ch) (R ch has the same circuit components)

73

7-2. Conventional Audio Circuit

The conventional audio circuit is contained in IC201 TA1251F. 7-2-1. EE Mode The line input signal entered from P920 is input to the input switching circuit of IC920 inside, and supplied to the Hi-Fi recording circuit, also supplied to the conventional audio input switching circuit at the same time. Now, the signal of L ch + R ch is output from pin 35 of IC920 as a conventional audio signal. The conventional audio signal to be output from pin 35 of IC920 is input to pin 2 of IC201, and it is output from pin 76 of IC201 passing through the line amplifier with the ALC circuit. This signal is supplied to pin 31 of IC920, and applied to the monitor switching circuit, and then output from pin 11 and 13 of IC920. After that, it is output as the same as Hi-Fi audio (EE mode). 7-2-2. Record Circuit In the record mode, as the EE mode circuit works in the same way, so this section describes about the circuit for record only. (1) Recording circuit The conventional audio signal to be output from pin 76 of IC201 is supplied to pin 78 of IC201, and applied to the audio head after amplifying in the record amplifier. The high band peaking circuit is constructed by using C716, C717, R719, R720 (long play mode), and L702. The peaking frequency is approximate 28kHz in SP mode, and approximate 10kHz in long play mode. In this system, the supply of record signal and the reproduction of playback signal are performed by the same surface of the audio head. (2) Erase oscillator circuit The erase oscillator circuit consists of Q731, Q732, R731 to R736, C732 to C737, T731, L731, and pin 90 of IC501 operates as the switch. In the record mode, Q732 turns ON from REC-H of IC501 and the erase oscillator operates.

7-2-3. Playback Circuit The playback signal obtained from the audio head is input to pin 68 of IC201, and enters a playback equalizer amplifier with a descending characteristic over a low band and middle band. The signal is output from pin 73 of IC201 after amplifying in this amplifier, and input to pin 74 of IC 201, and then it is output from pin 76 of IC201 passing through the line amplifier. After that, it is output as the same in case of the EE mode.

74