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Single-Cycle Processors: Datapath & Control

Arvind Computer Science & Artificial Intelligence Lab M.I.T. Based on the material prepared by Arvind and Krste Asanovic

Instruction Set Architecture (ISA) versus Implementation

ISA is the hardware/software interface
Defines set of programmer visible state Defines instruction format (bit encoding) and instruction semantics Examples: MIPS, x86, IBM 360, JVM

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Many possible implementations of one ISA

360 implementations: model 30 (c. 1964), z900 (c. 2001) x86 implementations: 8086 (c. 1978), 80186, 286, 386, 486, Pentium, Pentium Pro, Pentium-4 (c. 2000), AMD Athlon, Transmeta Crusoe, SoftPC MIPS implementations: R2000, R4000, R10000, ... JVM: HotSpot, PicoJava, ARM Jazelle, ...

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Processor Performance
Time Program = Instructions Program * Cycles Instruction * Time Cycle

Instructions per program depends on source code, compiler technology, and ISA Cycles per instructions (CPI) depends upon the ISA and the microarchitecture Time per cycle depends upon the microarchitecture and the base technology Microarchitecture this lecture Microcoded Single-cycle unpipelined Pipelined
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CPI >1 1 1

cycle time short long short

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Microarchitecture:
status lines

Implementation of an ISA control points

Controller

Data path

Structure: How components are connected. Static Behavior: How data moves between components Dynamic
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Hardware Elements
Combinational circuits
Mux, Demux, Decoder, ALU, ...
Sel A0 A1 An-1
lg(n)

OpSelect
- Add, Sub, ... - And, Or, Xor, Not, ... - GT, LT, EQ, Zero, ...

Sel A

lg(n)

Decoder

Demux

. . .

Mux

. . .

O0 O1 On1

A
lg(n)

. . .

O0 O1 On-1

ALU
B

Result Comp?

Synchronous state elements

Flipflop, Register, Register file, SRAM, DRAM D En Clk ff Q Clk En D Q
En Clk

register
D0 D1 D2

...

Dn-1

ff
Q0

ff
Q1

ff ...
Q2

ff
Qn-1

...

Edge-triggered: Data is sampled at the rising edge

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Register Files
Clock WE ReadSel1 ReadSel2 WriteSel WriteData ws clk
5 rs1 rs2 ws wd we

Register file 2R+1W

rd1 rd2

ReadData1 ReadData2

wd
32

rs1
5

register 0 we register 1 register 31

32 32

32

rd1

rs2
32 5

No timing issues in reading a selected register Register files with a large number of ports are difficult to design
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Intels Itanium, GPR File has 128 registers with 8 read ports and 4 write ports!!!

32

rd2

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A Simple Memory Model

WriteEnable Clock Address WriteData

MAGIC RAM

ReadData

Reads and writes are always completed in one cycle a Read can be done any time (i.e. combinational) a Write is performed at the rising clock edge if it is enabled the write address and data must be stable at the clock edge Later in the course we will present a more realistic model of memory
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Implementing MIPS:
Single-cycle per instruction datapath & control logic

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The MIPS ISA

Processor State
32 32-bit GPRs, R0 always contains a 0 32 single precision FPRs, may also be viewed as 16 double precision FPRs FP status register, used for FP compares & exceptions PC, the program counter some other special registers 8-bit byte, 16-bit half word 32-bit word for integers 32-bit word for single precision floating point 64-bit word for double precision floating point data addressing modes- immediate & indexed branch addressing modes- PC relative & register indirect Byte addressable memory- big endian mode

Data types

Load/Store style instruction set

All instructions are 32 bits

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Instruction Execution
Execution of an instruction involves
1. 2. 3. 4. 5. instruction fetch decode and register fetch ALU operation memory operation (optional) write back

and the computation of the address of the next instruction

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Datapath: Reg-Reg ALU Instructions

RegWrite 0x4
Add clk

inst<25:21> inst<20:16> PC
clk

addr

inst

inst<15:11>

Inst. Memory
inst<5:0>

we rs1 rs2 rd1 ws wd rd2

ALU

GPRs

ALU

Control

OpCode

6 0
31 26 25 September 26, 2005

5 rs

5 rt
21 20 16 15

5 rd
11

5 0
5

6 func
0

RegWrite Timing?
rd (rs) func (rt)

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Datapath: Reg-Imm ALU Instructions

RegWrite 0x4
Add clk

inst<25:21> PC
clk

addr

inst

inst<20:16>

Inst. Memory

we rs1 rs2 rd1 ws wd rd2

ALU

GPRs
Imm Ext

inst<15:0> inst<31:26>

ALU Control

OpCode

ExtSel

6 opcode
31 26 25 September 26, 2005

5 rs
2120

5 rt
16 15

16 immediate
0

rt (rs) op immediate

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Conflicts in Merging Datapath

RegWrite 0x4
Add clk

inst<25:21> PC
clk

addr

inst

Inst. Memory

inst<20:16> inst<15:11> inst<15:0> inst<31:26> inst<5:0>

we rs1 rs2 rd1 ws wd rd2

Introduce muxes
ALU

GPRs
Imm Ext

ALU Control

OpCode

ExtSel

6 0 opcode
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5 rs rs

5 rt rt

5 rd

5 0 immediate

6 func

rd (rs) func (rt) rt (rs) op immediate

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Datapath for ALU Instructions

RegWrite 0x4
Add clk

PC
clk

addr

<25:21> <20:16> inst <15:11> <15:0> <31:26>, <5:0>

Inst. Memory

we rs1 rs2 rd1 ws wd rd2

ALU

GPRs
Imm Ext

ALU Control

OpCode

6 0 opcode
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5 rs rs

5 rt rt

5 rd

RegDst rt / rd

ExtSel

OpSel

5 0

6 func

BSrc Reg / Imm

rd (rs) func (rt) rt (rs) op immediate

immediate

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Datapath for Memory Instructions

Should program and data memory be separate? Harvard style: separate (Aiken and Mark 1 influence) - read-only program memory - read/write data memory at some level the two memories have to be the same Princeton style: the same (von Neumanns influence) - A Load or Store instruction requires accessing the memory more than once during its execution

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Load/Store Instructions:Harvard Datapath

RegWrite 0x4
Add clk

MemWrite WBSrc ALU / Mem

clk

base PC
clk

addr

inst

we rs1 rs2 rd1 ws wd rd2

ALU

we addr z

Inst. Memory

GPRs
Imm Ext

disp

Data Memory
wdata ALU Control

rdata

OpCode RegDst

ExtSel

OpSel

BSrc

6 opcode
31 26 25

5 rs

5 rt
21 20 16 15

16 displacement
0

addressing mode (rs) + displacement

rs is the base register rt is the destination of a Load or the source for a Store
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MIPS Control Instructions

Conditional (on GPR) PC-relative branch
6 opcode 6 opcode 5 rs 5 rs 5 16 offset 16 BEQZ, BNEZ

Unconditional register-indirect jumps

5 JR, JALR

Unconditional absolute jumps

6 opcode 26 target J, JAL

PC-relative branches add offset4 to PC+4 to calculate the target address (offset is in words): 128 KB range Absolute jumps append target4 to PC<31:28> to calculate the target address: 256 MB range jump-&-link stores PC+4 into the link register (R31) All Control Transfers are delayed by 1 instruction
we will worry about the branch delay slot later
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Conditional Branches (BEQZ, BNEZ)

PCSrc br RegWrite MemWrite WBSrc

pc+4
0x4 Add Add clk

PC
clk

addr

inst

Inst. Memory

we rs1 rs2 rd1 ws wd rd2

clk

ALU z

we addr

GPRs
Imm Ext

Data Memory
wdata

rdata

ALU Control

OpCode RegDst September 26, 2005

ExtSel

OpSel

BSrc

zero?

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Register-Indirect Jumps (JR)

PCSrc br rind pc+4
0x4 Add Add clk

RegWrite

MemWrite

WBSrc

PC
clk

addr

inst

Inst. Memory

we rs1 rs2 rd1 ws wd rd2

clk

ALU z

we addr

GPRs
Imm Ext

Data Memory
wdata

rdata

ALU Control

OpCode RegDst September 26, 2005

ExtSel

OpSel

BSrc

zero?

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Register-Indirect Jump-&-Link (JALR)

PCSrc br rind pc+4
0x4 Add Add clk

RegWrite

MemWrite

WBSrc

PC
clk

addr

inst

31

Inst. Memory

we rs1 rs2 rd1 ws wd rd2

clk

ALU z

we addr

GPRs
Imm Ext

Data Memory
wdata

rdata

ALU Control

OpCode RegDst September 26, 2005

ExtSel

OpSel

BSrc

zero?

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Absolute Jumps (J, JAL)

PCSrc br rind jabs pc+4
0x4 Add Add clk

RegWrite

MemWrite

WBSrc

PC
clk

addr

inst

31

Inst. Memory

we rs1 rs2 rd1 ws wd rd2

clk

ALU z

we addr

GPRs
Imm Ext

Data Memory
wdata

rdata

ALU Control

OpCode RegDst September 26, 2005

ExtSel

OpSel

BSrc

zero?

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Harvard-Style Datapath for MIPS

PCSrc br rind jabs pc+4
0x4 Add Add clk

RegWrite

MemWrite

WBSrc

PC
clk

addr

inst

31

Inst. Memory

we rs1 rs2 rd1 ws wd rd2

clk

ALU z

we addr

GPRs
Imm Ext

Data Memory
wdata

rdata

ALU Control

OpCode RegDst September 26, 2005

ExtSel

OpSel

BSrc

zero?

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Five-minute break to stretch your legs

Single-Cycle Hardwired Control:

Harvard architecture We will assume clock period is sufficiently long for all of the following steps to be completed:
1. 2. 3. 4. 5. instruction fetch decode and register fetch ALU operation data fetch if required register write-back setup time tC > tIFetch + tRFetch + tALU+ tDMem+ tRWB

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At the rising edge of the following clock, the PC, the register file and the memory are updated
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Hardwired Control is pure Combinational Logic

ExtSel BSrc op code zero? OpSel

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combinational logic

MemWrite WBSrc RegDst RegWrite PCSrc

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ALU Control & Immediate Extension

Inst<5:0> (Func) Inst<31:26> (Opcode) + 0? ALUop

OpSel ( Func, Op, +, 0? )

Decode Map
ExtSel ( sExt16, uExt16, High16)
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Hardwired Control Table

Opcode ALU ALUi ALUiu LW SW BEQZz=0 BEQZz=1 J JAL JR JALR ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc

* sExt16 uExt16 sExt16 sExt16 sExt16 sExt16 * * * *

Reg Imm Imm Imm Imm * * * * * *

Func Op Op + + 0? 0? * * * *

no no no no yes no no no no no no

yes yes yes yes no no no no yes no yes

ALU ALU ALU Mem * * * * PC * PC

rd rt rt rt * * * * R31 * R31

pc+4 pc+4 pc+4 pc+4 pc+4 br pc+4 jabs jabs rind rind

BSrc = Reg / Imm RegDst = rt / rd / R31

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WBSrc = ALU / Mem / PC PCSrc = pc+4 / br / rind / jabs

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Pipelined MIPS
To pipeline MIPS: First build MIPS without pipelining with CPI=1 Next, add pipeline registers to reduce cycle time while maintaining CPI=1

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Pipelined Datapath
0x4 Add we rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext

PC

addr rdata

IR

ALU

we addr

Inst. Memory

Data Memory
wdata

rdata

write fetch decode & Reg-fetch execute memory -back phase phase phase phase phase Clock period can be reduced by dividing the execution of an instruction into multiple cycles tC > max {tIM, tRF, tALU, tDM, tRW} ( = tDM probably) However, CPI will increase unless instructions are pipelined
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An Ideal Pipeline
stage 1 stage 2 stage 3 stage 4

All objects go through the same stages No sharing of resources between any two stages Propagation delay through all pipeline stages is equal The scheduling of an object entering the pipeline is not affected by the objects in other stages These conditions generally hold for industrial assembly lines. But can an instruction pipeline satisfy the last condition?
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How to divide the datapath into stages

Suppose memory is significantly slower than other stages. In particular, suppose
tIM tDM tALU tRF tRW = = = = = 10 units 10 units 5 units 1 unit 1 unit

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Since the slowest stage determines the clock, it may be possible to combine some stages without any loss of performance

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Alternative Pipelining
0x4 Add we rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext

PC

addr rdata

IR

ALU

we addr

Inst. Memory

Data Memory
wdata

rdata

fetch phase

decode & Reg-fetch phase

execute phase

memory phase = = tt + tRW DM DM DM

write -back phase

tC > max {tIM , tRF , tALU , tDM ,, tt } } RW RW C IM RF+t ALU, t DM+t RW}

increase the critical path by 10%

Write-back stage takes much less time than other stages. Suppose we combined it with the memory phase
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Maximum Speedup by Pipelining

Assumptions 1. tIM = tDM = 10, tALU = 5, tRF = tRW= 1 4-stage pipeline 2. tIM =tDM = tALU = tRF = tRW = 5 4-stage pipeline 3. tIM =tDM = tALU = tRF = tRW = 5 5-stage pipeline Unpipelined Pipelined Speedup

tC

tC

27

10

2.7

25

10

2.5

25

5.0

It is possible to achieve higher speedup with more stages in the pipeline.

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Thank you !