Soft Turn-o Feature

Products with Feature: ACPL-333J, ACPL-330J, ACPL-332J, ACPL-331J, HCPL-316J

Application Note 5315

Introduction
Avagos gate optocoupler Soft turn-o feature is used to increase the reliability of an application during shortcircuit or over-current periods. This feature works after the DESAT protection is activated, which provides protection for transistor switches (IGBT/MOSFET) against short-circuit and over-current events. The desaturation protection circuit is illustrated in Figure 1. With the Soft turn-o feature, the gate voltage will be reduced slowly in order to reduce IGBT current. This is a two stage turn-o system. It will slowly discharge the IGBT gate to prevent a fast change in drain current. The Soft IGBT turn-o method will avoid an over-voltage spike across the IGBT caused by lead and wire inductances. How does desaturation protection and Soft shut-down work? This is illustrated in Figure 2.
HCPL-316J
V E 16

V LED2+ 15 DESAT 14 V CC2 13 V C 12 VOUT 11 V EE 10 V EE

9

100 pF

100

D DESAT

Rg

Figure 1. Desaturation Protection using the HCPL-316J

t DESAT (FAULT) t DESAT (10%)

7V V DESAT

t DESAT (LOW)

50%

t DESAT (90%) V OUT 90%

B
FAULT

10%

50% (2.5 V)

t RESET (FAULT) RESET 50%

Figure 2. Desaturation, Gate Output Voltage VOUT, FAULT and RESET Waveforms During Short-circuit or Overcurrent
Note: tDESAT(90%) is the DESAT Sense to 90% VOUT time delay tRESET(FAULT) is the RESET to High Level FAULT signal time delay

i. Fault Detection:
IGBT collector-emitter voltage, VCESAT is monitored through the DESAT pin 14. The IGBT is turned o if the voltage threshold (typically 6.5 V to 7 V) is reached (Point A). An approximation of the DMOS Rds(on) can be obtained by VOUT/IOL = 2.5/2.3 = 1.09 W (Page 9 of the HCPL-316J datasheet, Low Level Output Current). Hence the 1x DMOS Rds(on) is 50 x 1.09 = 54.5 W. The time constant can be approximated using Cg(Rg + 54.5). Using the same calculation method for the ACPL-332J, Rds(on) = 2.5/1.5 = 1.7 W. Hence the 1xDMOS Rds(on) is 50x1.7 = 85 W. Two characterization graphs reecting the inuence of Rg and Cg to the DESAT sense to 10% time are shown in Figure 4 and Figure 5. Both graphs can be found on page 13 in the ACPL-332J datasheet

ii. Soft Turn-o:

This is a two stage process. In the rst stage, a weak pull-down device in the output drive stage will turn on to softly turn o the IGBT. This device slowly discharges the IGBT. This turn o delay time of the gate optocoupler is labeled as DESAT sense to 10% VOUT delay, tDESAT(10%), in Figure 2. During soft turn-o, the internal 1xDMOS transistor is turned on (Figure 3b). During the slow turn o, the large output pull-down device, which is the second stage (Point B) remains o until the output gate voltage falls below VEE + 2 V, at which time the large pull-down device, 50x DMOS transistor, clamps the IGBT gate to VEE. The 50x represents a DMOS device 50 times larger than a 1x device (gure 3a). This tDESAT(10%) time is dependent on the gate resistor Rg, gate capacitance Cg, output supply voltage VCC2, and DMOS Rds(on) value. In the HCPL-316J datasheet, tDESAT(10%) is typically 2 ms for Rg = 10 W and Cg = 10 nF.

iii. Fault Output and O State:

After the DESAT sense to Low-level FAULT signal delay time, tDESAT(FAULT), the FAULT signal goes low (Point C). The fault detect circuitry is disabled to prevent false fault signals. The driver outputs will remain low (IGBT o ) until the following two conditions are met: The DESAT detection is low AND there is a RESET signal (HCPL-316J) or a RESET by the next INPUT PWM high signal is sent (ACPL-331J, ACPL-332J), ACPL-332J) or an internal automatic fault RESET after a xed-mute time of typically 26 ms (ACPL-330J, ACPL-333J).
250 A V E (16)

V IN+ (1) V IN - (2) V CC1 (3) GND (4) DELAY

FAULT

+ LED 7V

DESAT (14)

UVLO

+ 12 V

V CC2 (13) V C (12)

FAULT (6)

Q R S RESET (5) FAULT 1x 50 x

V OUT (11) V EE (9,10)

Figure 3a. Behavioral Circuit Schematic

250 A

V E (16)

+ LED 7V

DESAT (14)

UVLO

+ 12 V

V CC2 (13) V C (12)

O O

FAULT

O O O O I

V OUT (11)

O O

I
1x

50 x

ON

V EE (9,10)

OFF

Figure 3b. Normal Operation

250 A V E (16)

+ LED 7V

DESAT (14)

UVLO

+ 12 V

V CC2 (13) V C (12)

I I
FAULT

V OUT (11)

I I

I I

O
1x

50 x

OFF

V EE (9,10)

ON

Figure 3c. Soft-shutdown Operation

0.012 -------V cc2 =15 V _____Vcc2 =30 V 0.008 4.0 TDESAT10% - DESAT Sense to 10% Vo Delay - us

TDESAT10% - DESAT Sense to 10% Vo Delay - ms

------- Vcc2 =15 V _____Vcc2 =30 V

3.0

2.0

0.004

1.0

0.000

10

20

30

40

50

0.0 10 20 30 LOAD RESISTANCE - ohm 40 50

LOAD CAPACITANCE - nF

Figure 4. Normal Operation

Figure 5. Soft-shutdown Operation

Soft-turn o Function with External Current Buer Drive:

To increase the IGBT gate drive current, a non-inverting current buer, Figure 5, can be used. Inverting types are not compatible with the desaturation fault protection circuitry and should be avoided. To preserve the slow IGBT turn-o feature during a fault condition, a 10 nF capacitor should be connected from the buer input to VEE and a 10 resistor inserted between the output and the common NPN/PNP base. For this soft-shutdown circuit topology, it is assumed that the load capacitor should be greater than the 10 nF used. In this circuit, after a desaturation fault is detected, the weak pull-down device 1xDMOS transistor will pull the external RC circuit before the current buer (R=10 , C=10 nF). Refer back to Section ii, soft turn-o for details. The circuit topology in Figure 6 is also applicable for other Avago DESAT featured gate optocoupler drivers, like the ACPL-332J, ACPL-331J, ACPL-333J and ACPL-330J. The MJD44H11/MJD45H11 transistor pair is appropriate for currents up to 8 A maximum. The D44VH10/D45VH10 transistor pair is appro priate for currents up to 15 A maximum.
HCPL-316J VE 16 15 14 13 12 11 10 9 15 V -5 V 10 10 nF MJD44H11 or D44VH10 4.5 2.5 MJD45H11 or D45VH10 100 pF

VLED2+ DESAT VCC2 VC VOUT VEE VEE

Figure 6. Current Buer for Increased Drive Current

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2005-2010 Avago Technologies. All rights reserved. AV02-0073EN - July 21, 2010