SIMULATION

EXPERIMENTS

EXPERIMENT : 1

D / A CONVERTOR with R /2R

AIM: To construct a 8 bit digital to analog converter using R 2R ladder type. THEORY: A DAC accepts an n bit input word b1, b2, , bn in binary and produces an analog signal that is proportional to the input. In this type of DAC, reference voltage is applied to one switch and the other switches are grounded. It is easier to build and number of bits can be expanded by adding more R 2R sections. The circuit slows down due to stray capacitance. OBSERVATION:
Decimal Equivalent of binary number Input J4 J3 J2 J1 Output voltage Vo(volts) Theoretical Output voltage Vo(volts) practical

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 -0.625 -1.250 -1.875 -2.500 -3.125 -3.750 -4.375 -5.000 -5.625 -6.250 -6.875 -7.500 -8.125 -8.875 -9.375

13 0 V3 5V 0 Key = A 9 R5 10k Key = B 10 R4 10k Key = C Key = D 11 12 R3 R2 10k 10k J1 J2 J3 J4 R1 10k 0 V1 12 V 1

4

XMM1

U1 R8 6 R7 4 5k 5k
3 2 6

0 10k 5k

R10 8

R9

0
CIRCUIT DIAGRAM:

741 2 V2 12 V 0

FORMULA USED:

Vo= -R1 (

OUTPUT: J1=1, J2=1, J3=1, J4=1

RESULT: Thus R 2R ladder type digital to analog converter is designed and implemented using PSPICE.

A / D CONVERTOR
AIM: To design and implement an analog to digital converter using PSPICE. THEORY: An electronic integrated circuit whichtransforms a signal from analog (continuous) to digital (discrete) form. Analog signals are directly measurable quantities. Digital signals only have two states. For digital computer, we refer to binary states, 0 and 1. ADC are used virtually everywhere where an analog signal has to be processed, stored, or transported in digital form. Some examples of ADC usage are digital volt meters, cell phone, thermocouples, and digital oscilloscope. Microcontrollers commonly use 8, 10, 12, or 16 bit ADCs, our micro controller uses an 8 or 10 bit ADC.

OBSERVATION:

Sl.No

Analog I/P Vin

C3

C2

C1

D1

D0

1 2 3 4

0 to v/4 V/4 to V/2 V/2 to 3V/4 3V/4 to V

0 0 0 1

0 0 1 1

0 1 1 1

0 0 1 1

0 1 0 1

VCC 5V VCC U1B

4

X1 5 U1C 7400N 7400N

11

U2A U1A 1
1

2.5 V 3 7400N X2

D0

R5 10k
2

LM324N 4 6 2 7 U1D 7400N LM324N

8 R4 10k
5 7 6 4

2.5 V

D1

U2B

X3 2.5 V C3 X4 2.5 V C2

9
11

R1 100k 50 % Key=A 10 R2 10k

CIRCUIT DIAGRAM:

R3 10k 11
4 10 8 9

U2C X5

11

LM324N

2.5 V C1

RESULT: Thus a analog to digital converter circuit is designed and implemented using PSPICE.

EXPERIMENT : 2

ANALOG MULTIPLIER
AIM:

To design and implement a Analog Multiplierr using PSPICE.

THEORY:

A basic amplier is an active circuit in which the output voltage is proportional to the product of the two input signals. The terminals V+ and V- are supply terminals for the IC where dual supply is to be connected. The X and Y are the two input terminals where the the two inputs V1 and V2 are connected.

CIRCUIT DIAGRAM:
A1
Y X

XMM1

V1 4V

1 V/V 0 V V2 2V

XMM2 A2
Y X

V3 2 Vrms 100 Hz 0 V4 1 V/V 0 V

4 Vrms 100 Hz 0

XMM3 A3
Y X

V5 2 Vrms 100 Hz 0 1 V/V 0 V V6 4V

RESULT:

Thus a Analog Multiplier is designed and implemented using PSPICE.

EXPERIMENT : 3

CMOS Inverter, NAND and NOR using PSPICE

AIM:

To design and implement CMOS inverter, NAND and NOR using PSPICE.
THEORY: CMOS Inverter (or) CMOS NOT:

CMOS is widely used in digital ICs because of their high speed, low power dissipation and it can be operated at high voltages resulting in improved noise immunity. The inverter consists of two MOSFETs. The source of p-channel device is connected to +VDD and that of n-channel device is connected to ground. The gates of two devices are connected as common input. CIRCUIT DIAGRAM:
VDD 5V

Q2 X1 BST100 J1 2.5 V

Key = A Q1

2N7000

TRUTH TABLE:

INPUT (J1) 0 1

OUTPUT (X1) 1 0

CMOS NAND: It consists of two p-channel MOSFETs connected in parallel and two n- channel MOSFETs connected in series. P-channel MOSFET is ON when gate is negative and Nchannel MOSFET is ON when gate is positive.Thus when both input is low and when either of input is low, the output is high. CIRCUIT DIAGRAM:
VDD 5V J1 V2 5V Q2 Key = A BST100

J2 V1 5V Q1 Key = B BST100 X1 2.5 V

Q4

Q3

2N7000

2N7000

TRUTH TABLE:

INPUT J1 0 0 1 1 J2 0 1 0 1

OUTPUT X1 1 1 1 0

CMOS NOR: (iii) CMOS NOR It consists of two p-channel MOSFETs connected in series and two n-channel MOSFETs connected in parallel. P-channel MOSFET is ON when gate is negative and N-channel MOSFET is ON when gate is positive. Thus when both inputs are high and when either of input is high, the output is low. When both the inputs are low, the output is high. CIRCUIT DIAGRAM:
VDD 5V J1 Q1 V1 5V Key = A BST100 BST100 Q2 X1 2.5 V

Q3

2N7000

J2 V2 5V

Q4

Key = B

2N7000

TRUTH TABLE:

INPUT J1 0 0 1 1 J2 0 1 0 1

OUTPUT X1 1 0 0 0

MODEL GRAPH: CMOS Inverter (or) CMOS NOT:

CMOS NAND:

CMOS NAND:

RESULT:

Thus CMOS inverter, NAND and NOR is designed and implemented using PSPICE.

EXPERIMENT : 4

ACTIVE FILTERS BUTTERWORTH 2nd ORDER LPF (MAGNITUDE & PHASE RESPONSE)
AIM: To design and implement the second order butterworth Low pass filter using PSPICE.

THEORY: A low-pass filter is an electronic filter that passes low-frequency signals but attenuates (reduces the amplitude of) signals with frequencies higher than the cutoff frequency. The actual amount of attenuation for each frequency varies from filter to filter. It is sometimes called a high-cut filter, or treble cut filter when used in audio applications. A low-pass filter is the opposite of a high-pass filter.
CIRCUIT DIAGRAM:

R5 15k

R4 15.8k

V2 12 V

7 3

U1
6

R2 33k V3 5 Vrms 100MHz 0

R1 33k

2 4

741 V1 12 V

C1 4.7nF

C2 4.7nF

MODEL GRAPH:

OUTPUT:

RESULT: Thus Low pass filter is designed and implemented using PSPICE

BUTTERWORTH 2nd ORDER HPF (MAGNITUDE & PHASE RESPONSE)

AIM: To design and implement the second order butterworth High pass filter using PSPICE.

THEORY: A high-pass filter (HPF) is an electronic filter that passes high-frequency signals but attenuates (reduces the amplitude of) signals with frequencies lower than the cutoff frequency. The actual amount of attenuation for each frequency varies from filter to filter. A high-pass filter is usually modeled as a linear time-invariant system. It is sometimes called a low-cut filter or bass-cut filter. High-pass filters have many uses, such as blocking DC from circuitry sensitive to non-zero average voltages or RF devices.

CIRCUIT DIAGRAM:
R5 15k R4 15.8k

V2 12 V

7 3

U1
6

C1 4.7nF

C2
2

V3 5 Vrms 100MHz 0

4.7nF R2 33k R1 33k

741 V1 12 V

MODEL GRAPH:

OUTPUT:

RESULT: Thus High pass filter is designed and implemented using PSPICE.

EXPERIMENT : 5

DIFFERENTIAL AMPLIFIER
AIM:

To design and implement the differential amplifier using PSPICE.

THEORY:

A differential amplifier amplifies the difference between two voltages V1 and V2. The output of the differential amplifier is dependent on the difference between two signals and the common mode signal since it finds the difference between two inputs it can be used as a subtractor. The differential amplifier amplifies the difference between the two input voltage signals.Hence it is also called difference amplifier. In an ideal amplifer, the output voltage Vo is proportional to the difference between the two input signals. Hence we can write, Vo = Ad(V1 V2) Where Ad referes to differential gain, which amplifies the difference between two input signals. Vo=Ad/Vd Ad=Vo/Vd Generally the differntial amplifier is expressed in its decibel (db) valu as, Ad=20 log10(Ad) in db An average level of the two input signals is called common mode signal denoted as Vc. Vc=( V1 + V2)/2 The gain with which it amplifies the common mode signal to produce the output is called common modesignal to produce the output is common mode gain of the differential amplifier denoted as Ac. Vo=AcVc Ac =Vo/Vc Therefore the total output of any differential amplifier can be expressed as, Vo= Ad Vd+ AcVc Higher the value of C.M.R.R, better the performance of the differential amplifier. To improve C.M.R.R we have to increase differential mode gain and decrease common mode gain

V2 10 V

XSC1

Ext Trig +

_ +

XFG1 R1 10k

R2 10k

Q1 R3 1k BC548BP

Q2 R4 1k BC548BP

R5 8.2k
COMMON MODE:

V1 10 V

0 V2 10 V 4
A +

XSC1

Ext Trig +

XFG1 R1 10k 3 0 Q1 9 1k BC548BP 1 R3 5

R2 10k 2 Q2 6 BC548BP R4 1k 0

DIFFERENTIAL MODE:

R5 8.2k 7 V1 10 V 0

OUTPUT: COMMON MODE:

DIFFERENTIAL MODE:

RESULT: Thus a differential amplifier is designed and implemented using PSPICE.

EXPERIMENT : 6

ASTABLE, MONOSTABLE AND BISTABLE MULTIVIBRATOR - TRANSISTOR BIAS

ASTABLE MULTIVIBRATOR:
AIM:

To plot the transient response of voltages at collector terminals of the two transistors Q1 and Q2. Initial node voltages at collector and base are zero.
THEORY:

It has two quasi stable states. The transition between the two states occurs automatically due to charging and discharging of the capacitors and not due to any external trigger. Thus none of the transistor is allowed to remain in ON or OFF state.
CIRCUIT DIAGRAM:

MODEL GRAPH:

OUTPUT:

Result:

Thus astable multivibrator is designed and implemented using PSPICE.

MONOSTABLE MULTIVIBRATOR
AIM: To design and implement a Monostable multivibrator using PSPICE THEORY:

Monostable multivibrator has two states (i) quasistable state and (ii) stable state. When a trigger input is given to the monostable multivibrator, it switches between two states. It has resistor coupling with one transistor. The other transistor has capacitive coupling. The capacitor is used to increase the speed of switching. The resistor R2 is used to provide negative voltage to the base so that Q1 is OFF and Q2 is ON. Thus an output square wave is obtained from monostable multivibrator.

CIRCUIT DIAGRAM:

MODEL GRAPH:

OUTPUT:

RESULT:

Thus monostable multivibrator is designed and implemented using PSPICE.

BI-STABLE MULTIVIBRATOR
AIM:

To design and implement a bistable multivibrator using PSPICE

THEORY:

The bistable multivibrator has two stable states. The multivibrator can exist indefinitely in either of the twostable states. It requires an external trigger pulse to change from one stable state to another. The circuit remains in one stable state until an external trigger pulse is applied. The bistable multivibrator is used for the performance of many digital operations such as counting and storing of binary information. The multivibrator also finds an applications in generation and pulse type waveform.
CIRCUIT DIAGRAM:
VCC 5V VCC XSC1 R3 2.2k 1 C1 1nF R1 J2 0 Key = A J1 Q2 4 BC547A R5 68k 5 R7 470 C3 47uF R6 68k BC547A 68k 6 C2 1nF R2 68k Q1 R4 2.2k
A + _ + B _ Ext Trig + _

2 0

Key = A

MODEL GRAPH:

OUTPUT:

RESULT:

Thus bistable multivibrator is designed and implemented using PSPICE.