Power Integrity Simulation for High Speed Board using CST PCBS

In high speed design, power integrity (also known as power supply integrity) is an important topic to be discussed alongside signal integrity. The objective of power integrity is to produce a clean signal for the high-speed driver by supplying a good source. A good source needs to fulfill two criteria: 1) meet the DC power requirement and 2) reduce the power fluctuation caused by the AC current switch. This article will discuss the power integrity simulation workflow using CST PCB STUDIO (CST PCBS). The demo board consists of 6 layers with the typical S-P-S-S-G-S layer stackup, where S = signal, P = plane and G = ground.

DC Power Integrity (IR-Drop)

DC power integrity, also known as IR-Drop, is a static power integrity which includes voltage power supply and current for each driver (I/O device). The IR-Drop simulation in CST PCBS is based on the static formulation of the Partial Element equivalent Circuit (PEEC) method, which requires only a small computational effort since the generated equivalent network is purely resistive. The IR-Drop simulation is typically performed early in the design flow as it can be performed quickly even for a large board. The 1.8 volt power plane is used in this article for the demonstration. There are two I/O devices connected to the 1.8 V power plane: the U7 component (the graphic processors) and the U8 component (the DDR2 RAM). In order to get the correct DC voltage drop across the power plane, it is recommended to follow the correct electrical specification each of the component. The pieces of information required are: 1) the output voltage of the DC-DC voltage converter for the power supply (most of the time the value is readable from the power plane labelling) and 2) the total current consumption of the high speed driver (I/O device) connected to the particular power plane. In this example we have 16 pins of the U8 component with total current 190 mA and 7 pins of U7 component with total current 350mA. Figure 1 shows the 1.8 V power plane and the connected components, and Figure 2 shows the information for the IR-Drop simulation setup.

Figure 1: The 1.8v power plane net (white outlined) and the connected devices, U3 (power supply), U7 and U8 (I/O devices).

Power Integrity Simulation for High Speed Board using CST PCBS 2014 CST AG - http://www.cst.com

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Figure 2: The IR-Drop input dialog with the voltage of power supply and the current amplitude of I/O devices.

The voltage distribution across the 1.8 volt power plane is depicted in the figure 3. Given the maximum allowed voltage fluctuation 0.1 V, the total noise margins will be 0.2 volt. With the typical DC noise margins around 20%, the two drivers attached to the 1.8 V power plane can still meet the electrical requirement of the I/O devices.

Figure 3: Voltage distribution at 1.8 volt power plane.

AC Power Integrity

The AC power integrity simulation requires more computational effort than the DC power integrity analysis, since the mounted device placement and the PDN (Power Delivery Network) components such capacitors and VRM are now included. The main consideration of this analysis is the high current density at the via and the power plane, especially at the region of the VRM near to the high speed driver. Since high current will produce a high inductance, and inductance increases together with the

Power Integrity Simulation for High Speed Board using CST PCBS 2014 CST AG - http://www.cst.com

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frequency, the goal of doing the AC power integrity simulation is to minimize the PDN impedance, which will help to avoid voltage fluctuation under the switching condition.

Figure 4: Power Delivery Network (PDN).

Minimizing the PDN impedance can be easily obtained by calculating the target impedance. The target impedance formulation is shown in the equation depicted in Figure 5.

Figure 5: Target impedance formulation used as a reference for minimizing the PDN impedance.

For a 1.8 V voltage with 0.2 volt total noise margins and 20% DC noise margins, the AC noise margins is now left with 80%, which is 0.16 volt of AC noise margins. Assuming 540 mA of the AC current, the target impedance for power plane of 0.29 ohm is now defined as a goal of the PDN impedance to meet maximum allowed voltage fluctuation under the switching condition.

The PDN impedance is defined by examining each driver pin in turn. Figure 6 shows the bare board PDN impedance (green curve) looking into the U8 pin A1. This typically has a V-shaped curve which starts capacitive at low frequency and turns inductive at high frequency. The second peak around 683 MHz shows the resonance of the power plane. In order to minimize the PDN impedance, decoupling capacitors are added between the power and GND plane. The capacitors will add the C parasitic to the board and therefore will shift the resonances. The red curve on the same Figure 6 represents the populated board with several capacitors mounted between power and GND plane. The previous resonance at 683 MHz is now shifted down to a lower frequency. Due to the short circuit behaviour of the capacitor at high frequency (i.e. inductive behaviour of capacitor from the parasitic L), the PDN impedance at higher frequency will not change and increasing the value of the decoupling capacitors will only deliver a small improvement. Therefore, improving the PDN impedance at high frequency is a more tedious task requiring more simulation iterations, analyzing the plane impedance, improving the component mounting placement to reduce the inductance and choosing decoupling capacitors with low parasitic inductance.

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Figure 6: PDN impedance curve for bare and populated boards.

The spatial impedance plot for the bare and the populated board is shown in Figure 7. The plane impedance of the bare board in Figure 7a shows additional higher impedance value as the impedance seen from the power pin U8 A1. This is mainly due to the resonance of the plane and can be shifted away by mounting the decoupling capacitor at the resonance region, which is shown in Figure 7b.

Figure 7: PDN impedance spatial plot between bare- and populated board at 683MHz.

Transient Power Integrity

As a final verification of the power integrity analysis, the transient behavior of the power supply voltage will be shown. The transient current will be pulled by the driver in order to drive the switching signal. Each of the 16 pins of U8 and the 7 pins of U7 is connected to its corresponding IBIS power supply pin, and "1010" bit sequences to model the transient current switching are input for each of the IBIS control pin. Additional voltage probes are placed at each power supply connection to monitor the transient voltage during the IBIS switch. The results from the voltage probes are depicted in Figure 8. For better visualization, only the results related to two pins of U7 and U8 are shown.

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Figure 8: Transient current switching and the voltage probe results.

Figure 8 illustrates the voltage probe result of the transient simulation. For better understanding, the transient current switch is also plotted, which can be seen from the upper picture in Figure 8. The red curve represents the result from U7 component, and the green curve represents the result from the U8 component. It is clearly shown that each time the driver current switched, a voltage noise was seen at the driver power supply. The higher switching the current and faster switching the driver, the greater the voltage noise produced, which makes it necessary to further reduce the PDN impedance.

Conclusion

In this article the power integrity workflow of a high speed board is presented. Power integrity analysis is performed in both DC and AC. Optimizing the PDN impedance in the frequency domain is one of the major goals in order to minimize the voltage power supply noise. The transient simulation provides a useful demonstration of how important is to minimize the PDN impedance in order to ensure a low voltage noise under the switching condition.

Power Integrity Simulation for High Speed Board using CST PCBS 2014 CST AG - http://www.cst.com

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