CS152 Computer Architecture and Engineering Lecture 5: Cost and Design Feb. 5, 1998 J. Wawrzynek (http.cs.berkeley.

edu/~johnw) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/

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Review: Performance and Technology Trends

1000
Supercomputers Mainframes

100 Performance

10
Minicomputers Microprocessors

0.1 1965 1970 1975 1980 1985 Year 1990 1995 2000

Technology Power: 1.2 x 1.2 x 1.2 = 1.7 x / year

Feature Size: shrinks 10% / yr. => Switching speed improves 1.2 / yr. Density: improves 1.2x / yr. Die Area: 1.2x / yr.

RISC lesson is to keep the ISA as simple as possible:

Shorter design cycle => fully exploit the advancing technology (~3yr) Advanced branch prediction and pipeline techniques Bigger and more sophisticated on-chip caches
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Review: Technology, Logic Design and Delay CMOSTechnology Trends

Complementary: PMOS and NMOS transitors CMOS inverter and CMOS logic gates

Delay Modeling and Gate Characterization

Delay = Internal Delay + (Load Dependent Delay x Output Load)

Clocking Methodology and Timing Considerations

Simplest clocking methodology - All storage elements use the SAME clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time

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Integrated Circuit Costs

wafer cost Die cost = dies per wafer die yield

wafer area ( wafer diam 2) 2 wafer diam Dies per wafer = Test dies Die area 2 Die area die area

Die yield =

wafer yield defects per unit area die area 1 +

Die Cost is goes roughly with the cube of the area.

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Die Yield
Raw Dices Per Wafer

wafer diameter
6/15cm 8/20cm 10/25cm die yield

die area (mm2) 100 144 196 139 90 62 265 177 124 431 290 206

256 44 90 153

324 32 68 116

400 23 52 90

23% 19% 16% 12% 11% 10% typical CMOS process: =2, wafer yield=90%, defect density=2/cm2, 4 test sites/wafer Good Dices Per Wafer 31 16 9 5 59 32 19 11 96 53 32 20

6/15cm 8/20cm 10/25cm

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typical cost of an 8, 4 metal layers, 0.5um CMOS wafer: ~$2000

Real World Examples

Chip
386DX 486DX2

Metal Line Wafer Defect Area Dies/ Yield Die Cost layers width cost /cm2 mm2 wafer
2 0.90 $900 1.0 1.0 1.3 1.0 1.2 1.6 1.5 43 81 121 196 234 256 296 360 181 115 66 53 48 40 71% 54% 28% 27% 19% 13% 9% $4 $12 $53 $73 $149 $272 $417 3 0.80 $1200 3 0.80 $1300 3 0.70 $1500 3 0.80 $1500

PowerPC 601 4 0.80 $1700 HP PA 7100 DEC Alpha Pentium

SuperSPARC 3 0.70 $1700

From "Estimating IC Manufacturing Costs, by Linley Gwennap, Microprocessor Report, August 2, 1993, p. 15

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Other Costs
IC cost = Die cost + Testing cost + Packaging cost Final test yield

Packaging Cost: depends on pins, heat dissipation

Chip
386DX 486DX2 PowerPC 601 HP PA 7100 DEC Alpha SuperSPARC Pentium
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Die cost $4 $12 $53 $73 $149 $272 $417

Package pins type 132 QFP 168 PGA 304 QFP 504 PGA 431 PGA 293 PGA 273 PGA

cost $1 $11 $3 $35 $30 $20 $19

Test & Assembly $4 $12 $21 $16 $23 $34 $37

Total
$9 $35 $77 $124 $202 $326 $473
Spring 1998 UCB

System Cost: -1995-96 Workstation System Cabinet Subsystem Sheet metal, plastic Power supply, fans Cables, nuts, bolts (Subtotal) Processor DRAM (64MB) Video system I/O system Printed Circuit board (Subtotal) Keyboard, mouse Monitor Hard disk (1 GB) Tape drive (DAT) (Subtotal) % of total cost 1% 2% 1% (4%) 6% 36% 14% 3% 1% (60%) 1% 22% 7% 6% (36%)
Spring 1998 UCB

Motherboard

I/O Devices

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COST v. PRICE

Q: What % of company income on Research and Development (R&D)?

list price +5080% Average Discount

(WSPC)

(3345%)

avg. selling price +25100% Gross Margin +33% Direct Costs Component Cost Input: chips, displays, ...
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gross margin direct costs component cost Commision: channel profit, volume discounts,

(3314%) (810%) (2531%)

direct costs component cost Overhead: R&D, rent, marketing, profits, ...

component cost Making it: labor, scrap, returns, ...

Spring 1998 UCB

The Design Process

"To Design Is To Represent" Design Begins With Requirements
Functional Capabilities: what it will do Performance Characteristics: Speed, Power, Area, Cost, . . .

And yields a description/representation of an object.

The process of going from the requirements to a description of the object it implements is design. Design activity yields a formal description/representation of an object The concept is captured in one or more representation languages

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Design Process (cont.)

Design Leads to Implementation

-- Design understood in terms of components and how they have been assembled -- Top Down decomposition of complex functions (behaviors) into more primitive functions Datapath ALU Regs Nand Gate

CPU Control Shifter

-- bottom-up composition of primitive building blocks into more complex assemblies

Design is a "creative process," not a simple method

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Design Refinement
Informal System Requirement Initial Specification Intermediate Specification refinement increasing level of detail Final Architectural Description

Intermediate Specification of Implementation

Final Internal Specification Physical Implementation

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Design as Search
Problem A Strategy 1 Strategy 2

SubProb 1

SubProb2

SubProb3

BB1

BB2

BB3

BBn

Design involves educated guesses and verification

-- Given the goals, how should these be prioritized? -- Given alternative design pieces, which should be selected? -- Given design space of components & assemblies, which part will yield the best solution? Feasible (good) choices vs. Optimal choices
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Problem: Design a fast ALU for the MIPS ISA Requirements? Must support the Arithmetic / Logic operations Tradeoffs of cost and speed based on frequency of occurrence, hardware budget

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MIPS ALU requirements Add, AddU, Sub, SubU, AddI, AddIU

=> 2s complement adder/sub with overflow detection

And, Or, AndI, OrI, Xor, Xori, Nor

=> Logical AND, logical OR, XOR, nor

SLTI, SLTIU (set less than)

=> 2s complement adder with inverter, check sign bit of result

ALU from from CS 150 / P&H book chapter 4 supports these ops

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MIPS arithmetic instruction format

31 R-type: I-Type:
Type ADDI

25 Rs Rs
funct xx xx xx xx xx xx xx xx

20 Rt Rt
Type ADD

15 Rd

5 funct Immed 16

op op
op 10

op 00

funct 40 41 42 43 44 45 46 47

Type

op 00 00

funct 50 51 52 53

ADDIU 11 SLTI SLTIU ANDI ORI XORI LUI 12 13 14 15 16 17

ADDU 00 SUB 00

SLT

00

SUBU 00 AND OR XOR NOR 00 00 00 00

SLTU 00

Signed arith generate overflow, no carry

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Design Trick: divide & conquer Break the problem into simpler problems, solve them and glue together the solution Example: assume the immediates have been taken care of before the ALU
10 operations (4 bits)
00 01 02 03 04 05 06 07 12 13
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add addU sub subU and or xor nor slt sltU

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Refined Requirements
(1) Functional Specification inputs: 2 x 32-bit operands A, B, 4-bit mode outputs: 32-bit result S, 1-bit carry, 1 bit overflow operations: add, addu, sub, subu, and, or, xor, nor, slt, sltU (2) Block Diagram (powerview symbol, VHDL entity) 32 A c ovf B 32 4 m

ALU
S 32

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Behavioral Representation: VHDL

Entity ALU is generic (c_delay: integer := 20 ns; S_delay: integer := 20 ns); port ( signal A, B: in signal m: in signal S: out signal c: out signal ovf: out end ALU; vlbit_vector (0 to 31); vlbit_vector (0 to 3); vlbit_vector (0 to 31); vlbit; vlbit)

...
S <= A + B;

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Design Decisions
ALU bit slice

7-to-2 C/L PLD Gates

7 3-to-2 C/L CL0 CL6 mux

Simple bit-slice
big combinational problem many little combinational problems partition into 2-step problem

Bit slice with carry look-ahead ...

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Refined Diagram: bit-slice ALU

A 32 B 32

a31 b31 ALU0 m co s31 cin

b0 ALU0 m co cin s0

a0

4 M

Ovflw 32 S

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7-to-2 Combinational Logic start turning the crank . . .

Function 0 Inputs M0 M1 M2 M3 A B Cin add 0 0 0 0 0 0 0 Outputs S Cout 0 0 K-Map

127
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Seven plus a MUX ? Design trick 2: take pieces you know (or can imagine) and try to put them together Design trick 3: solve part of the problem and extend
CarryIn A

S-select and

or

Result

Mux

1-bit Full Adder

add

CarryOut
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Additional operations A - B = A + ( B)
form two complement by invert and add one S-select CarryIn invert and
A

or

Result

Mux

1-bit Full Adder

add

CarryOut

Set-less-than? left as an exercise

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Revised Diagram LSB and MSB need to do a little extra

A 32 B 32

a31 b31

a0

b0

4 M C/L to produce select, comp, c-in

ALU0 co cin s31

ALU0 co cin s0

Ovflw S

32

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Overflow
Decimal 0 1 2 3 4 5 6 7 Binary 0000 0001 0010 0011 0100 0101 0110 0111 Decimal 0 -1 -2 -3 -4 -5 -6 -7 -8 2s Complement 0000 1111 1110 1101 1100 1011 1010 1001 1000

Examples: 7 + 3 = 10 but ...

0

-4 - 5 = -9
1 0 + 0 1 1 1 0 0 1 1 1 1

but ...
1 1 1 0 7 3 6 + 1 1 0 1 0 1 0 1 1 0 1 1 4 5 7

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Overflow Detection
Overflow: the result is too large (or too small) to represent properly
Example: - 8 < = 4-bit binary number <= 7

When adding operands with different signs, overflow cannot occur! Overflow occurs when adding:
2 positive numbers and the sum is negative 2 negative numbers and the sum is positive

On your own: Prove you can detect overflow by:

Carry into MSB Carry out of MSB
0 1 0 + 0 1
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1 1 0 0

1 1 1 1 1 1 0 7 3 6

0 1 1 0 1 0 1 1 0 1 1 4 5 7

1 0

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Overflow Detection Logic Carry into MSB Carry out of MSB

For a N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
CarryIn0 A0 B0 A1 B1 A2 B2 A3 B3 1-bit Result0 ALU CarryIn1 CarryOut0 1-bit Result1 ALU CarryIn2 CarryOut1 1-bit ALU CarryIn3 1-bit ALU CarryOut3
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X 0 0 1 1

Y 0 1 0 1

X XOR Y 0 1 1 0

Result2 Overflow Result3

More Revised Diagram LSB and MSB need to do a little extra

A signed-arith and cin xor co a31 b31 ALU0 co cin s31 a0 b0 4 M C/L to produce select, comp, c-in 32 B 32

ALU0 co cin s0

Ovflw S

32

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