Dr.Y.Narasimha Murthy., Ph.D yayavaram@yahoo.

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UNIT II : SEQUENTIAL CIRCUIT DESIGN Introduction: The various stages involved in the design of sequential circuits include, the

derivation of state tables, state table reduction , state assignment , and derivation of flip-flop input equations. The state table is derived by determining the relationship between the input and output sequences or sometimes can be derived directly from the state graph also. After deriving the

state table ,it is reduced to a minimum number of states. First, duplicate rows are eliminated by row matching method and, then using an implication table. If the reduced table has m states (2n1 < m 2n), n flip-flops are required. Assign a unique combination of flip-flop states to correspond to each state in the reduced table. Form the transition table by substituting the assigned flip-flop states for each state in the reduced state table. The resulting transition table specifies the next states of the flip-flops, and the output in terms of the present states of the flip-flops and the input. Plot next-state maps and input maps for each flip-flop and derive the flip-flop input equations. (Depending on the type of gates to be used, either determine the sum-of-products form from the 1s on the map or the product-of-sums form from the 0s on the map.) Derive the output functions. Realize the flip-flop input equations and the output equations using the available logic gates. Check the design by signal tracing, computer simulation, or laboratory testing. Design of Iterative Circuits : An iterative circuit consists of a number of identical cells interconnected in a regular manner. Certain arithmetic operations, like binary addition are implemented with an iterative circuit because the same operation is performed on each pair of input bits. The regular structure of an iterative circuit makes it easier to fabricate in integrated circuit form than circuits with less regular structures. The simplest form of an iterative circuit consists of a linear array of combinational cells with signals between cells traveling in only one direction.Each cell is a combinational circuit with one or more primary inputs (xi) and possibly one or more primary outputs (zi). In addition, each cell

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has one or more secondary inputs (ai) and one or more secondary outputs (ai +1). The ai signals carry information about the state of one cell to the next cell as shown in the figure (i) below.

The primary inputs to the cells (x1, x2, . . . , xn) are applied in parallel i.e , they are all applied at the same time. The ai signals then propagate along the line of cells. Because the circuit is combinational, the time required for the circuit to reach a steady state condition is determined only by the delay times of the gates in the cells. As soon as steady state is reached, the outputs may be read. Thus, the iterative circuit can function as a parallel-input, parallel-output device, in contrast with the sequential circuit in which the input and output are serial. One can think of the iterative circuit as receiving its inputs as a sequence in space in contrast with the sequential circuit which receives its inputs as a sequence in time. The parallel adder of is an example of an iterative circuit that has four identical cells. The serial adder uses the same full adder cell as the parallel adder, but it receives its inputs serially and stores the carry in a flip-flop instead of propagating it from cell to cell. An Example - Design of a Comparator : A comparator circuit compares two n-bit binary numbers and determines whether they are equal or which one is larger if they are not equal. As ,it is not practically possible to design a 2n input combinational circuit for n larger than 4 or 5 , so the iterative approach is used.Let the two binary numbers to be compared be X = x1x2x3 . . . .. . xn and Y = y1y2 . . . yn

here x1 is the most significant and comparison is made from left to right. The iterative circuit is as shown in below diagram. The Comparison proceeds from left to right. The first cell compares x1 and y1 and passes on the result of the comparison to the next cell, the second cell compares x2 and y2, etc. Finally, xn and yn are compared by the last cell, and the output circuit produces signals to indicate if X = Y , X > Y, or X < Y.

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Let us consider the design of a typical cell for the comparator. To the left of cell i, three conditions are possible .They are X = Y so far (x1 x2 . . . xi1 = y1y2 . . . yi1), X > Y , and X < Y so far. Let us indicate these three input conditions as states S0, S1, and S2, respectively. The table (i) shows the output state at the right of the cell (Si+1) in terms of the xiyi inputs and the input state at the left of the cell (Si). If the numbers are equal to the left of cell i and xi = yi, the numbers are still equal including cell i, so Si+1 = S0.However, if Si = S0 and xi yi = 10, then x1x2 . . . xi > y1y2 . . . yi and Si+1 = S1. If X > Y to the left of cell i, then regardless of the values of xi and yi, x1x2 . . . xi > y1y2 . . . yi and Si+1 = S1. Similarly, if X < Y to the left of cell i, then X < Y including the inputs to cell i, and Si+1 = S2.

The logic for a typical cell is derived from the state table. Because there are three states, two inter cell signals are required. The state assignment aibi = 00 for S0, 01 for S1, and 10 for S2. Substituting this assignment into the state table gives the table (ii) below. Figure (ii) below shows the Karnaugh maps, next-state equations, and the realization of a typical cell using NAND gates. Inverters are to be included in the cell because only ai and bi and not their complements are transmitted between cells.

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The a1b1 inputs to the left end cell must be 00 because it is assumed that the numbers are equal (all 0) to the left of the most significant bit. The equations for the first cell can then be simplified if needed. a2 = a1 + x1y1b1 = x1y1 b2 = b1 + x1y1 a1 = x1y1

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For the output circuit, let Z1 = 1 if X < Y, Z2 = 1 if X = Y, Z3 = 1 if X > Y. Figure below shows the output maps, equations, and circuit.

This is the design example of an iterative circuit which compares two binary numbers. Design of Sequential Circuits Using ROMs Code Converter : A sequential circuit can easily be designed using a ROM (read-only memory) and flip-flops. If we consider any general model of a Mealy sequential circuit , the combinational part of the
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sequential circuit is realized using a ROM. The ROM is used to realize the output functions (Z1, Z2, . . . , Zn) and the next-state functions (Q+1 , Q+2 , . . . , Q+k ). The state of the circuit can then be stored in a register of D flip-flops and fed back to the input of the ROM. Thus, a Mealy sequential circuit with m inputs, n outputs, and k state variables can be realized using k D flipflops and a ROM with m + k inputs (2m+k words) and n + k outputs. The Moore sequential circuit can also be realized in a similar manner. The next-state and output combinational

subcircuits of the Moore circuit can be realized using two ROMs. Alternatively, a single ROM can be used to realize both the next state and output functions. Generally in sequential circuit design , D flip-flops are preferred to J-K flip-flops because use of two-input flip-flops would require increasing the number of outputs from the ROM. Let us consider the design of a code converter using ROM and D flip-flops. The state table code converter are shown in the tables (i) below. for the

As there are seven states, three D flip-flops are required. Thus, a ROM with four inputs (24 words) and four outputs is required, as shown in figure (i). Using a straight binary state assignment, the transition table is constructed as shown in table (ii).This table gives the next state of the flip-flops as a function of the present state and input. As, D-Flip-Flops are used in the design , D1 = Q1+ , D2 = Q2+ , and D3 = Q3+ .

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The truth table for the ROM, shown in table(iii), is constructed from the transition table. This table gives the ROM outputs (Z, D1, D2, and D3) as functions of the ROM inputs (X, Q1, Q2, and Q3). Design of Sequential Circuits Using PLAs Code Converter Sequential circuits can also be realized using PLAs (programmable logic arrays) and flip-flops in a manner similar to using ROMs and flip-flops. But, in the case of PLAs, the state assignment may be important because the use of a good state assignment can reduce the required number of product terms and, hence, reduce the required size of the PLA. As an example let us consider the design of a code-converter.The state table shown above in Table(i)can be realized by using one PLA and three Flip-Flops as shown in figure (i) below.This circuit configuration is very similar to ROM based design ,except that ROM is replaced by the PLA of suitable size.The state assignment leads to the truth table given in table below. This

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table could be stored in a PLA with four inputs, 13 product terms, and four outputs, but this would offer little reduction in size compared with the 16-word ROM.

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If the state assignment of the code converter is considered , the resulting output equation and D flip-flop input equations, derived from the Karnaugh can be written the following equations D1 = Q1+ = Q2 D2 = Q2+ = Q1 D3 = Q3+ = Q1Q2Q3 + XQ1 Q3 + XQ1 Q2 Z = XQ3 + XQ3

The PLA table which corresponds to these equations is given in table above . This table can be realized by using a PLA with four inputs, seven product terms, and four outputs.
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To verify the operation of the above design initially, assume that X = 0 and Q1Q2Q3 = 000.This selects rows --0- and 0--0 in the table, so Z = 1 and D1D2D3 = 100. After the active clock edge, Q1Q2Q3 = 100. If the next input is X = 1, then rows --0- and -1--are selected, so Z = 0 and D1D2D3 = 110. After the active clock edge, Q1Q2Q3 = 110. Design of Sequential Circuits Using CPLDs : A typical CPLD contains a number of macro-cells that are grouped into function blocks. Connections between the function blocks are made through an interconnection array. Each macro-cell contains a flip-flop and an OR gate, which has its inputs connected to an AND gate array. Some CPLDs are based on PALs, in which case each OR gate has a fixed set of AND gates associated with it. Other CPLDs are based on PLAs, in which case any AND gate output within a function block can be connected to any OR gate input in that block. Figure below shows the structure of a Xilinx Cool Runner II CPLD, which uses a PLA in each function block. This CPLD family is available in sizes from two to 32 function blocks (32 to 512 macro-cells). Each function block has 16 inputs from the AIM (advanced interconnection matrix) and up to 40 outputs to the AIM. Each function block PLA contains the equivalent of 56 AND gates. Let us consider the implementation of a Mealy Machine using the CPLD.The figure (i) below shows how a Mealy sequential machine with two inputs, two outputs, and two flip-flops can be implemented by a CPLD.

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Here four macro-cells are required, two to generate the D inputs to the flip-flops and two to generate the Z outputs. The flip-flop outputs are fed back to the AND array inputs via the interconnection matrix . The number of product terms required depends on the complexity of the equations for the Ds and the Zs. Implementation of a Parallel Adder: The figure below shows how three bits of the parallel adder with accumulator of can be implemented using a CPLD. Each bit of the adder requires two macro-cells. One of the macro-cells implements the sum function and an accumulator flipflop. The other macro-cell implements the carry, which is fed back into the AND array. The Ad signal can be connected to the CE input of each flip-flop via an AND gate . Each bit of the adder requires eight product terms (four for the sum, three for the carry, and one for CE). If the flipflops are programmed as T flip-flops, then the logic for the sum can be simplified. For each accumulator flip-flop Then, the T input is Xi+ = Xi Yi Ci

Ti = Xi + Xi = Yi Ci which requires only two product terms.

The add signal can be ANDed with the Ti input so that the flip-flop state can change only when Ad = 1 .The resultant T input is given by the following equation. Ti = Ad (Yi Ci) = Ad Yi Ci+ Ad YiCi This explains the implementation of 3-bit parallel adder using a CPLD.
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Dr.Y.Narasimha Murthy., Ph.D yayavaram@yahoo.com

Design of Sequential Circuits Using FPGAs : An FPGA consists of an array of configurable logic blocks (CLBs) surrounded by a ring of I/O blocks. The FPGA may also contain other components such as memory blocks, clock generators, tri-state buffers, etc. A typical CLB contains two or more function generators, often referred to as look-up tables or LUTs, programmable multiplexers, and D-CE flip-flops.The I/O blocks usually contain additional flip-flops for storing inputs or outputs and tri-state buffers for driving the I/O pins. Let us consider the implementation of a Mealy sequential machine which has two inputs, two outputs, and two flip-flops by using a FPGA .For this implementation four LUTs ( FGs or function generators) are required, two to generate the D inputs to the flip-flops and two to generate the Z outputs. The flip-flop outputs are fed back to the CLB inputs via interconnections external to the CLB. The entire circuit fits into one CLB. This implementation works well because each D and Z is a function of only four variables (X1, X2, Q1, and Q2). If more flipflops or inputs are needed, the D or Z functions may have to be decomposed to use additional function generators .

The implementation of a Mealy Machine based on FPGA device using two flip-flops and four Function generators is shown in the above figure.
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FPGA Implementation of a Shift Register : Let us now consider the direct implementation of a shift register using an FPGA. The figure below shows how the 4-bit loadable right-shift register can be implemented using an FPGA. Four LUTs are used to generate the D inputs to the flip-flops, and a fifth LUT generates the CE input

. Implementation of 3-bit parallel Adder: The figure below shows how three bits of the

parallel adder with accumulator can be implemented using an FPGA. Each bit of the adder can be implemented with two 3-variable function generators, one for the sum and one for the carry.

The Ad signal is connected to the CE input of each flip-flop so that the sum is loaded by the rising clock edge when Ad = 1. The arrangement for generating the carries, is rather slow
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because the carry signal must propagate through a function generator and its external interconnections for each bit. Because adders are frequently used in FPGAs, most FPGAs have built-in fast carry logic in addition to the function generators. If the fast carry logic is used, the bottom row of function generators of the figure above is not needed, and a parallel adder with an accumulator can be implemented using only one function generator for each bit.

----------------xxxxxxxxxxx-----------Reference : Fundamentals of Logic Design Charles H.Roth.Jr - Cengage Learning.

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