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TUTORIAL ON FETs

Theoretical Questions:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Explain on the basic operation of the n-channel JFET. Draw the drain characteristics of the mentioned JFET type and denote the important parameters on the graph.

Explain why the JFET is called a unipolar device. Your explanation must be based on the n-channel or p-channel device which is biased to operate as an amplifier.

What is one advantage of FET over BJT?

What is the main advantage of using self-biasing in a JFET amplifier circuit? Draw the self-biasing circuit.

State the three basic configurations of the JFET circuit. Compare and give brief description on the circuits’ voltage gain, input and output impedances. State the main application for each configuration.

Describe in detail, with the help of appropriate illustrations, the operation of the n- channel E-MOSFET under the following biasing conditions:

(a) drain and source are grounded, no biasing voltage at the gate

(b) drain and source are grounded, small positive voltage at the gate

(c) small positive voltage at the gate, small positive voltage at the drain and source

(d) small positive voltage at the gate, V DS increased from the value in (c)

Q7.

Q8.

(i)

(ii)

(iii)

(iv)

Q9.

Q10.

Draw the schematic of the p-channel E-MOSFET in its typical operation. Explain on the drain and transfer characteristics of this circuit.

Draw the cross section and the drain characteristics of an n-channel E-MOSFET at the different biasing condition specified below:

V

GS

< V

GS(th)

and

V

DS

>0

V

GS

> V

GS(th)

and

V

DS

> V

DS(sat)

V

GS

> V

GS(th)

and

V

DS

= V

DS(sat)

V

GS

> V

GS(th)

and

V

DS

> V

DS(sat)

Draw the

the operating mode regions and write the I D expression for each region.

I

D

versus V

DS

curve for an ideal n-channel E-MOSFET (NMOS). Label

With the help of illustrations, explain briefly on the operation of the DE and E MOSFETs as amplifiers and comment on the differences.

1

Q11.

Q12.

For the circuit shown below, (a)give detailed explanation on the reason why

increment of

(b)what will happen if

V

GG

at a fixed V

DD

.

V

GG

= V

GS(off)

?

I

D will decrease with the

V GG

R

D

. V GG = V GS(off) ? I D will decrease with the V GG R
I D
I
D

V DD

How is the drain current controlled in the n-channel JFET? Use illustrations to help you in giving your explanations.

Calculations:

Q1.

The JFET in the following diagram has the following characteristics,

and V

GS(off)

= -3V . Determine

(a)

(b)

V

V

G

G

=0 V

=10 V

V

GSQ

and

V

O

if

+

V

-

G

+15 V

R D 3 kΩ R S 8 kΩ V 8 V
R
D
3 kΩ
R
S
8 kΩ
V
8 V

+

o

-

I

DSS

= 5mA

Q2.

Given the drain to ground voltage is equivalent to 5 V for the circuit below.

Calculate

I

D

,V

GS

,V

DS

and

V

S

for this circuit.

2

Q3.

Q4.

+V DD 9 V R R 1 D 10 MΩ 4.7 kΩ R R 2
+V
DD
9 V
R
R
1
D
10 MΩ
4.7 kΩ
R
R
2
S
2.2MΩ
3.3 kΩ

Calculate the voltage gain and the input and output impedances for the common

source circuit shown below.

.

Determine the voltage gain if C 2 is absent.

R

GS

=1000

M

,

g

m

= 4000

S

and

r

ds

= 80 k

V DD

R D C 3 4.7 k R C Supply 1 v R o G v
R
D
C
3
4.7
k
R
C
Supply
1
v
R
o
G
v
v
i
s
R
390 k
S
C
2
2.7
k

R

68 k

L

The JFET in the following diagram has V p = -3 V and

value of all the resistors so that

has 0.05 mA flowing through the voltage divider.

I DSS

= 9 mA . Calculate the

The design

V

G

= 5 V,I

D

= 4 mA and V =11V .

D

3

Q5.

The

V

DD

gate

current

can

= -20 V,I

DSS

=10 mA,I

determine

(i) V GG and

(ii) V

DSQ

+15 V R R G1 D R R G2 S be ignored for the JFET
+15 V
R
R
G1
D
R
R
G2
S
be
ignored
for
the
JFET
in
the
= 8 mA, V
= 4 V,R
= 0 Ω andR
DQ
GS(off)
S

V DD

D

circuit

=1.5 k,

below.

If

R D C 3 C 1 R v G o v i V R GG
R
D
C
3
C
1
R
v
G
o
v
i
V
R
GG
S

Q6.

For the circuit shown below,

R

G

R

S1

,R

S2

,I

DSS

=10 mA, V

Determine:

(a) V

(b) R

(c) R

S

S1

S2

GS(off)

= -4 V, V

4

DD

=15 V, V

DSQ

=10 V and V

GSQ

= -2 V.

Q7.

V DD

i i C C C C i L R G R S1 v R in
i i C
C
C
C
i
L
R
G
R
S1
v
R
in
L
V
S
R
S2
C
S
C C C i L R G R S1 v R in L V S R

v

C C C i L R G R S1 v R in L V S R

L

(a)Fixed-biasing is implemented on the following JFET circuit. Assume that the gate current can be neglected (I G = 0). Show that if V DD > 0, V GS < 0. This condition will enable correct device biasing.

(b)If

R

D

= 3 k

,

R

=

S

1 k

,

V

DD

=15 V and V

DSQ

= 7 V , calculate I DQ and V GSQ .

R

V DD R G R
V DD
R
G
R

D

S

Q8. Referring to the following circuits, determine the DE MOSFET’s mode of operation (depletion, enhancement or zero). Give explanation to your answer.

is very large that the current flowing through it can be neglected

Assume

R

G

resulting in

V

RG

0 .

5

Q9.

R

R

+V DD R D R G S
+V
DD
R
D
R
G
S

G

(a)

+V DD R
+V
DD
R

(c)

D

R

G

+V DD R
+V
DD
R

(b)

-V

DD

R
R
D R G S G (a) +V DD R (c) D R G +V DD R

R

(d)

D

D

S

The JFET in the following circuit has V p = -3 V. If V S = -1 V when the device is in its pinched-off region, calculate I DSS .

V SS 1mA V DD
V SS
1mA
V DD

6

V

S

= -1V

Q10.

Q11.

Q12.

For a JFET that is operating at V GS = -1 V, has V p = -2 V and I DSS = 8 mA, determine the variation required in the V GS to increase the I D by 0.4 mA. What is the variation required in the V GS to reduce the I D by 0.4 mA from the same initial value. Why is the variation in the V GS different for both cases? What is the JFET type? Give explanations for your answers.

For

D in the pinched-off region (also

known as the constant current region or saturation region), calculate the voltage

at the source of the transistor. Determine the operation mode of the device. Give

two reasons for your answer.

= -2 V andK = 2 mA/V . Given

the

[

=K V

circuit

shown

below,

V

DS

V

GS(off)

2

I

DSS

]

2

. Neglecting the

GS(off)

effect on

I

5 V

GS(off) 2 I DSS ] 2 . Neglecting the GS(off) effect on I 5 V 2

2 mA

(a)Determine the voltages at the terminal, the transconductance and the voltage gain for the following DE-MOSFET circuit. Given: gain, A v = g m x R D , g m0 = 2000 mho, V GS(off) = -4 V and I DSS = 4 mA.

(b)Determine the transistor’s mode of operation, i.e. whether it is in depletion or enhancement mode. Based on the results from the calculation in (a), give two reasons for your answer.

v in

11V

R R 1 D 100 MΩ 1kΩ R 2 10 MΩ
R
R
1
D
100 MΩ
1kΩ
R
2
10 MΩ

7

v out

Q13.

Each

R and

the required gate width for Q 1 and Q 2 to obtain the voltages and current as shown in the diagram.

has

of

= 2 V,

n

C

the

ox

= 20

transistor

A/V

2

,

in

the

=10

circuit

below

V

GS(th)

= 0 andL =L

1

2

m .

Find the value of

10 V

0.2 mA R 7 V Q 2 Q 1 3 V source amplifier
0.2 mA
R
7
V
Q 2
Q 1
3
V
source
amplifier

r

ds

= 30 k

Q14.

R

D

In

,

g

A

v

the

m

.

= 2

common

and

let

. Using the simplified, low-frequency small-signal

and then

of

the

circuit

A

v

= v

below,

o

/ v

in

= 3 k

10

-3

S

equivalent circuit, find an expression for the voltage-gain ratio

evaluate

V DD

R D v R R C i G S S
R
D
v
R
R
C
i
G
S
S

8

Q15.

E-MOSFETs are normally found operating as switches in digital ICs. Below is a typical switching circuit. Determine the waveform v out for the shown v in . Use the given drain characteristics to help you in your calculations. Repeat if R is changed to 10 k .

in your calculations. Repeat if R is changed to 10 k . V DD = 20

V DD

= 20 V

R = 4.7 k v out v in
R = 4.7 k
v
out
v
in

Q16.

Fixed biasing can be implemented on the E-MOSFET as shown in the diagram below. The drain characteristic of the E-MOSFET is included.

R

1

= 60 k

,R

2

= 40 k

R

D

= 3 k

,

V

DD

=15 V. Assume I G = 0.

,

(i) Calculate V GSQ .

(ii) Determine V DSQ and I DQ from the drain characteristic.

V DD

R 1 R 2
R
1
R
2

R

D

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