High Ip3, 700 MHZ To 2800 MHZ, Double Balanced, Passive Mixer, If Amplifier, and Wideband Lo Amplifier

High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADL5811
FEATURES
RF frequency: 700 MHz to 2800 MHz continuous LO frequency: 250 MHz to 2800 MHz, high-side or low-side inject IF range: 30 MHz to 450 MHz Power conversion gain of 7.5 dB at 1900 MHz SSB noise figure of 10.7 dB at 1900 MHz Input IP3 of 27.5 dBm at 1900 MHz Input P1dB of 12.7 dBm at 1900 MHz Typical LO drive of 0 dBm Single-ended, 50 RF port Single-ended or balanced LO input port Single-supply operation: 3.6 V to 5.0 V Serial port interface control on all functions Exposed paddle 5 mm 5 mm, 32-lead LFCSP package
FUNCTIONAL BLOCK DIAGRAM

32 31 30 29 28 27 26
COMM
25 24 NC 23 NC 22 NC 21 LOIP 20 LOIN 19 LE 18 DATA 17 CLK 16
IFGM
IFON
NC 1 RFCT 2 NC 3 RFIN 4 NC 5 NC 6 NC 7 NC 8
9 10 11 12 13 14 15
ADL5811
BIAS GEN
SERIAL PORT INTERFACE
VLO3
VLO2
VLO4
COMM
COMM
COMM
VLO1
IFGD
IFOP
VPIF
NC
NC
COMM
Figure 1.
APPLICATIONS
Multiband/multistandard cellular base station receivers Wideband radio link diversity downconverters Multimode cellular extenders and broadband receivers
GENERAL DESCRIPTION
The ADL5811 uses revolutionary new broadband, square wave limiting, local oscillator (LO) amplifiers to achieve an unprecedented radio frequency (RF) bandwidth of 700 MHz to 2800 MHz. Unlike conventional narrow-band sine wave LO amplifier solutions, this permits the LO to be applied either above or below the RF input over an extremely wide bandwidth. Because energy storage elements are not used, the dc current consumption also decreases with decreasing LO frequency. The ADL5811 uses highly linear, doubly balanced, passive mixer cores along with integrated RF and LO balancing circuits to allow single-ended operation. The ADL5811 incorporates programmable RF baluns, allowing optimal performance over a 700 MHz to 2800 MHz RF input frequency. The balanced passive mixer arrangement provides outstanding LO-to-RF and LO-toIF leakages, excellent RF-to-IF isolation, and excellent intermodulation performance over the full RF bandwidth. The balanced mixer cores also provide extremely high input linearity, allowing the device to be used in demanding wideband applications where in-band blocking signals may otherwise result in the degradation of dynamic range. Blocker noise figure performance is comparable to narrow-band passive mixer designs. High linearity IF buffer amplifiers follow the passive mixer cores, yielding typical power conversion gains of 7.5 dB, and can be used with a wide range of output impedances. For low voltage applications, the ADL5811 is capable of operation at voltages down to 3.6 V with substantially reduced current. Two logic bits are provided to power down (<1.5 mA) the circuit when desired. All features of the ADL5811 are controlled via a 3-wire serial port interface, resulting in optimum performance and minimum external components. The ADL5811 is fabricated using a BiCMOS high performance IC process. The device is available in a 32-lead, 5mm 5mm, LFCSP package and operates over a 40C to +85C temperature range. An evaluation board is also available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved.
09912-001
ADL5811 TABLE OF CONTENTS

Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 3.6 V Performance...................................................................... 16 Spurious Performance................................................................ 17 Circuit Description......................................................................... 20 RF Subsystem.............................................................................. 20 LO Subsystem ............................................................................. 21 Applications Information .............................................................. 22 Basic Connections...................................................................... 22 IF Port .......................................................................................... 22 Bias Resistor Selection ............................................................... 22 VGS Programming .................................................................... 22 Low-Pass Filter Programming.................................................. 23 RF Balun Programming ............................................................ 23 Register Structure ........................................................................... 24 Evaluation Board ............................................................................ 25 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28
REVISION HISTORY
7/11Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADL5811 SPECIFICATIONS
VS = 5 V, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = 10 dBm, LO power = 0 dBm, R1 = 910 , ZO = 50 , optimum SPI settings, unless otherwise noted. Table 1.
Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under Blocking Input Third-Order Intercept Input Second-Order Intercept Input 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage RF-to-IF Output Isolation IF/2 Spurious IF/3 Spurious POWER INTERFACE Supply Voltage, VS Quiescent Current Power-Down Current
1
Test Conditions/Comments Tunable to >20 dB broadband via serial port
Min
Typ 15 50
Max
Unit dB MHz ||pF MHz V dBm dB MHz dB dB dB dB dBm dBm dBm dBm dBm dB dBc dBc
700 Differential impedance, f = 200 MHz 30 Externally generated 6 VS 0 13 50 260||1.0
2800
450
+10
Low-side or high-side LO Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 , differential ZLOAD = 200 differential 5 dBm blocker present 10 MHz from wanted RF input, LO source filtered fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each RF tone at 10 dBm fRF1 = 1900 MHz, fRF2 = 2000 MHz, fLO = 1697 MHz, each RF tone at 10 dBm Unfiltered IF output
250 7.5 13.9 10.7 20.7 27.5 62 12.7 40 25 26 73 75 3.6 5 185 1.4
2800
10 dBm input power 10 dBm input power
5.5
Resistor programmable IF current
V mA mA
Supply voltage must be applied from external circuit through choke inductors.
ADL5811
TIMING CHARACTERISTICS
Low logic level 0.4 V, and high logic level 1.4 V. Table 2. Serial Interface Timing
Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns minimum ns minimum ns minimum ns minimum ns minimum ns minimum ns minimum Test Conditions/Comments LE setup time DATA-to-CLK setup time DATA-to-CLK hold time CLK high duration CLK low duration CLK-to-LE setup time LE pulse width
Timing Diagram
t4
CLK
t5
t2
DATA DB23 (MSB) DB22
t3
DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE
t7
t1
09912-002
Figure 2. Timing Diagram
ADL5811 ABSOLUTE MAXIMUM RATINGS

Table 3.
Parameter Supply Voltage, VPOS CLK, DATA, LE IF Output Bias RF Input Power LO Input Power Internal Power Dissipation JA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 5.5 V 6.0 V 20 dBm 13 dBm 1.1 W 25C/W 150C 40C to +85C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ADL5811 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPIF IFGM NC IFOP IFON NC IFGD COMM 32 31 30 29 28 27 26 25
NC RFCT NC RFIN NC NC NC NC
1 2 3 4 5 6 7 8
ADL5811
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
NC NC NC LOIP LOIN LE DATA CLK
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions

Pin No. 1, 3, 5 to 8, 22 to 24, 27, 30 2 4 9, 11, 13, 15 10, 12, 14, 16, 25 17, 18, 19 20 21 26 28, 29 31 32 Mnemonic NC RFCT RFIN VLO4, VLO3, VLO2, VLO1 COMM CLK, DATA, LE LOIN LOIP IFGD IFOP, IFON IFGM VPIF EPAD Description No Connect. Can be grounded. RF Balun Center Tap (AC Ground). RF Input. Should be ac-coupled. Positive Supply Voltages for LO Amplifier. Ground. Serial Port Interface Control. Ground Return for LO Input. LO Input. Should be ac-coupled. Supply Return for IF Amplifier. Must be grounded. IF Differential Open-Collector Outputs. Should be pulled up to VCC using external inductors. IF Amplifier Bias Control. Supply Voltage for IF Amplifier. Exposed pad must be connected to ground.
09912-003
NOTES 1. NC = NO CONNECT. CAN BE GROUNDED. 2. EXPOSED PAD MUST BE CONNECTED TO GROUND.
VLO4 COMM VLO3 COMM VLO2 COMM VLO1 COMM
9 10 11 12 13 14 15 16
ADL5811 TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = 10 dBm, LO power = 0 dBm, R1 = 910 , ZO = 50 , optimum SPI settings, unless otherwise noted.
220 210 200
TA = 40C TA = +25C TA = +85C
90 80 70
TA = 40C TA = +25C TA = +85C
SUPPLY CURRENT (mA)
190
INPUT IP2 (dBm)
180 170 160 150
60 50 40 30
140 130
20 10 700
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
09912-004
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
Figure 4. Supply Current vs. RF Frequency

10 9 8 7 6 5 4
Figure 7. Input IP2 vs. RF Frequency

20 18 16
TA = 40C TA = +25C TA = +85C
TA = 40C TA = +25C TA = +85C
CONVERSION GAIN (dB)
INPUT P1dB (dBm)
14 12 10 8 6 4
3 2 700
2
09912-005
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
Figure 5. Power Conversion Gain vs. RF Frequency

45 40 35
16
Figure 8. Input P1dB vs. RF Frequency
TA = 40C TA = +25C TA = +85C
15 14
TA = 40C TA = +25C TA = +85C
NOISE FIGURE (dB)
13 12 11 10 9 8
INPUT IP3 (dBm)
30 25 20 15 10 700
7
09912-006
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
Figure 6. Input IP3 vs. RF Frequency
Figure 9. SSB Noise Figure vs. RF Frequency
09912-009
6 700
09912-008
0 700
09912-007
120 700
ADL5811
235 225 215
SUPPLY CURRENT (mA)
RF = 1900MHz
VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V
80 75 70 65
RF = 1900MHz
205 195 185 175 165 155 145

09912-010
INPUT IP2 (dBm)
60 55 50 45 40 35
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 10. Supply Current vs. Temperature

10.0 9.5 9.0
20 18 16
Figure 13. Input IP2 vs. Temperature
RF = 1900MHz
RF = 1900MHz
INPUT P1dB (dBm)
8.5 8.0 7.5 7.0 6.5 6.0 5.5

09912-011
14 12 10 8 6 4 40 30 20 10
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. Power Conversion Gain vs. Temperature

35 33 31
15 14
Figure 14. Input P1dB vs. Temperature
RF = 1900MHz

SSB NOISE FIGURE (dB)
RF = 1900MHz
29
13 12 11 10 9 8 40 30 20 10
INPUT IP3 (dBm)
27 25 23 21 19 17
09912-012
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 12. Input IP3 vs. Temperature
Figure 15. SSB Noise Figure vs. Temperature
09912-015
15 40 30 20 10
09912-014
5.0 40 30 20 10
09912-013
135 40 30 20 10
30 40 30 20 10
ADL5811
200 195 190 185 180 175 170 165 160 30
TA = 25C
RF = 900MHz RF = 1900MHz RF = 2500MHz
80 70 60
TA = 25C
SUPPLY CURRENT (mA)
INPUT IP2 (dBm)
50 40 30 20 10 0 30 RF = 900MHz RF = 1900MHz RF = 2500MHz
09912-016
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 16. Supply Current vs. IF Frequency

11 10
18 16 14
Figure 19. Input IP2 vs. IF Frequency
TA = 25C
TA = 25C
INPUT P1dB (dBm)
12 10 8 6 4 2 30
8 7 6 5 4 30
09912-017
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. Power Conversion Gain vs. IF Frequency

30 39 28
20 18
Figure 20. Input P1dB vs. IF Frequency
TA = 25C
TA = 25C
27 26 25 24 23 22
16 14 12 10 8 6
INPUT IP3 (dBm)
09912-018
30
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 18. Input IP3 vs. IF Frequency
Figure 21. SSB Noise Figure vs. IF Frequency
09912-021
4 30
09912-020
09912-019
ADL5811
11 10 9 8 7 6 5 4 3 6
TA = 25C
20 18 16
TA = 25C
INPUT P1dB (dBm)

09912-022
14 12 10 8 6 4 6
10
10
LO POWER (dBm)
LO POWER (dBm)
Figure 22. Power Conversion Gain vs. LO Power

35 33 31
IF/2 SPURIOUS (dBc)
40 45 50 55 60 65 70 75 80 85
09912-023
Figure 25. Input P1dB vs. LO Power
TA = 25C
TA = 40C TA = +25C TA = +85C
29
INPUT IP3 (dBm)
27 25 23 21 19 17 15 6
10
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
LO POWER (dBm)
Figure 23. Input IP3 vs. LO Power

80 70 60
Figure 26. IF/2 Spurious vs. RF Frequency, RF Power = 10 dBm

55 60 65 70 75 80 85 90 700
TA = 25C
TA = 40C TA = +25C TA = +85C
50 40 30 20 10 6

09912-024
IF/3 SPURIOUS (dBc)
INPUT IP2 (dBm)
10
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
LO POWER (dBm)
Figure 24. Input IP2 vs. LO Power
Figure 27. IF/3 Spurious vs. RF Frequency, RF Power = 10 dBm
09912-027
09912-026
90 700
09912-025
ADL5811
100 MEAN: 7.5 SD: 0.12%
500
TA = 25C
10
80
PERCENTAGE (%)
400
8 CAPACITANCE (pF)
09912-033
60
RESISTANCE ()
300
40
200
20
100
09912-028
7.3
7.5 CONVERSION GAIN (dB)
7.7
7.9
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
Figure 28. Conversion Gain Distribution

100
Figure 31. IF Output Impedance (R Parallel C Equivalent)

0 5
MEAN: 27.5 SD: 0.36%

RF PORT RETURN LOSS (dB)
TA = +25C
80
PERCENTAGE (%)
10 15 20 25 30 35
60
40
20
09912-029
25.5
27.5 INPUT IP3 (dBm)
29.5
31.5
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
Figure 29. Input IP3 Distribution

100
Figure 32. RF Port Return Loss, Fixed IF vs. RF Frequency

0 3 6 9 12 15 18 21
MEAN: 11.68 SD: 0.36%
TA = 25C
80
LO RETURN LOSS (dB)
PERCENTAGE (%)
60
40
20
11.0
11.5 INPUT P1dB (dBm)
12.0
12.5
09912-030
0 10.5
24 500
700
900 1100 1300 1500 1700 1900 2100 2300 2500 LO FREQUENCY (MHz)
Figure 30. Input P1dB Distribution
Figure 33. LO Return Loss
09912-032
0 23.5
40 700
09912-031
0 7.1
0 30
ADL5811
0 10
TA = 40C TA = +25C TA = +85C
0 10 20 30 40 50 60 70 500
2LO-TO-IF 2LO-TO-RF
TA = 25C
RF-TO-IF ISOLATION (dB)
20 30 40 50 60 70 80 700
09912-034
2XLO LEAKAGE (dBm)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
700
900 1100 1300 1500 1700 1900 2100 2300 2500 LO FREQUENCY (MHz)
Figure 34. RF-to-IF Isolation vs. RF Frequency

0 10
LO-TO-IF LEAKAGE (dBm)
10 20 30 40 50 60 70 80 500
Figure 37. 2XLO Leakage vs. LO Frequency
TA = 40C TA = +25C TA = +85C
3LO-TO-IF 3LO-TO-RF
TA = 25C
30 40 50 60 70 80 500
09912-035
3XLO LEAKAGE (dBm)
20
700
900 1100 1300 1500 1700 1900 2100 2300 2500

LO FREQUENCY (MHz)
700
900 1100 1300 1500 1700 1900 2100 2300 2500 LO FREQUENCY (MHz)
Figure 35. LO-to-IF Leakage vs. LO Frequency

0 10
LO-TO-RF LEAKAGE (dBm)
14 13 12
Figure 38. 3XLO Leakage vs. LO Frequency

16 15 14 NOISE FIGURE 13 12 11 10 9 GAIN 8
VGS = 4 VGS = 5 VGS = 6 VGS = 7
TA = 40C TA = +25C TA = +85C
TA = +25C
11 10 9 8 7 6 5
30 40 50 60 70 80 500
700
900 1100 1300 1500 1700 1900 2100 2300 2500 LO FREQUENCY (MHz)
09912-036
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
Figure 36. LO-to-RF Leakage vs. LO Frequency
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency for All VGS Settings
09912-0139
4 700
VGS = 0 VGS = 1
VGS = 2 VGS = 3
20
09912-038
09912-037
ADL5811
35 30 25
VGS = 0 VGS = 1 VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = 7
TA = +25C
27 24 21 18 15 12 9
240 220
TA = 25C
INPUT IP3
SUPPLY CURRENT (mA)

09912-140
20 15 10 5 0 700
INPUT P1dB (dBm)
200 180 160 140 120 100 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800
INPUT IP3 (dBm)
INPUT P1dB 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
IF BIAS RESISTOR VALUE ()
Figure 40. Input IP3 and Input P1dB vs. RF Frequency for All VGS Settings
35 30
20 18 16 14 12 10 8 6
Figure 42. Supply Current vs. IF Bias Resistor Value

32 28 24 20 16 12
CONVERSION GAIN AND SSB NOISE FIGURE (dB)
TA = 25C
INPUT IP3
25 20 15 10 5 0 30
NOISE FIGURE
GAIN
8 4
TA = +25C
09912-141
25
20
15
10
10
BLOCKER POWER (dBm)
IF BIAS RESISTOR VALUE ()
Figure 41. SSB Noise Figure vs. 10 MHz Offset Blocker Level
Figure 43. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias Resistor Value
09912-043
4 0 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800
INPUT IP3 (dBm)
09912-042
ADL5811
11 10 9
RFB = RFB = RFB = RFB = RFB = RFB = RFB = RFB = 0 1 2 3 4 5 6 7
TA = +25C
18 17 16
INPUT P1dB (dBm)
8 7 6 5 4 3 2
15 14 13 12 11 10 9
RFB = RFB = RFB = RFB = RFB = RFB = RFB = RFB =
0 1 2 3 4 5 6 7
TA = +25C
09912-044
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
Figure 44. Conversion Gain vs. RF Frequency for All RFB Settings
32 31 30 29
Figure 46. Input P1dB vs. RF Frequency for All RFB Settings
16
0 1 2 3 4 5 6 7
TA = +25C
15 14 13 12 11 10 9 8 7
09912-045
0 1 2 3 4 5 6 7
TA = +25C
INPUT IP3 (dBm)
28 27 26 25 24 23 22 700
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
6 700
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
Figure 45. Input IP3 vs. RF Frequency for All RFB Settings
Figure 47. SSB Noise Figure vs. RF Frequency for All RFB Settings
09912-047
09912-046
1 700
8 700
ADL5811
12 10
LPF LPF LPF LPF
=0 =1 =2 =3
TA = +25C RFB0
21 19 17
LPF LPF LPF LPF
=0 =1 =2 =3 RFB0
TA = +25C
INPUT P1dB (dBm)
15 13 11 9 7 5 700 RFB7
6 4 2 0 2 700
RFB7
09912-048
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
Figure 48. Conversion Gain vs. RF Frequency for All LPF Settings at RFB7 and RFB0
35 33 31 29 RFB0 TA = +25C
Figure 50. Input P1dB vs. RF Frequency for All LPF Settings at RFB7 and RFB0
20 18 16
LPF LPF LPF LPF
=0 =1 =2 =3 RFB0
TA = +25C
INPUT IP3 (dBm)
14 12 10 8 6
27 25 23 21 19 17 15 700 LPF LPF LPF LPF =0 =1 =2 =3

09912-049
RFB7
RFB7
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
Figure 49. Input IP3 vs. RF Frequency for All LPF Settings at RFB7 and RFB0
Figure 51. SSB Noise Figure vs. RF Frequency for All LPF Settings at RFB7 and RFB0
09912-051
2 700
09912-050
ADL5811
3.6 V PERFORMANCE
VS = 3.6 V, TA = 25C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = 10 dBm, LO power = 0 dBm, R1 = 800 , ZO = 50 , optimum SPI settings, unless otherwise noted.
150 140 130 TA = 40C TA = +25C TA = +85C 80 70 60 TA = 40C TA = +25C TA = +85C
SUPPLY CURRENT (mA)
INPUT IP2 (dBm)

09912-052
120 110 100 90 80 70 700
50 40 30 20 10 0 700
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
Figure 52. Supply Current vs. RF Frequency at 3.6 V

14 12
Figure 55. Input IP2 vs. RF Frequency at 3.6 V

24 21 18
TA = 40C TA = +25C TA = +85C
TA = 40C TA = +25C TA = +85C
10
INPUT P1dB (dBm)
15 12 9 6 3 0 700
8 6 4 2 0 700
09912-053
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
Figure 53. Power Conversion Gain vs. RF Frequency at 3.6 V

35 30 25
24 21
Figure 56. Input P1dB vs. RF Frequency at 3.6 V
TA = 40C TA = +25C TA = +85C

TA = 40C TA = +25C TA = +85C
18 15 12 9 6 3 0 700
INPUT IP3 (dBm)
20 15 10 5 0 700
09912-054
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz)
900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
Figure 54. Input IP3 vs. RF Frequency at 3.6 V
Figure 57. SSB Noise Figure vs. RF Frequency at 3.6 V
09912-057
09912-056
09912-055
ADL5811
SPURIOUS PERFORMANCE
(N fRF) (M fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = 100 dBm.
5 V Performance
VS = 5 V, TA = 25C, RF power = 10 dBm, LO power = 0 dBm, R1 = 910 , ZO = 50 , optimum SPI settings, unless otherwise noted. Table 5. RF = 900 MHz, LO = 697 MHz
0 0 1 2 3 4 5 6 7 N 8 9 10 11 12 13 14 15 37.8 65.0 94.0 <100 <100 <100 1 54.2 0.0 54.4 86.7 <100 <100 <100 <100 2 31.4 38.7 69.6 <100 <100 <100 <100 <100 <100 3 41.5 19.6 53.4 91.0 <100 <100 <100 <100 <100 4 29.4 51.6 72.5 <100 <100 <100 <100 <100 <100 <100 5 58.5 38.0 82.3 95.3 <100 <100 <100 <100 <100 <100 <100 6 49.3 62.9 93.5 <100 <100 <100 <100 <100 <100 <100 <100 <100 7 70.5 52.4 97.4 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 M 8 52.9 70.2 93.0 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 9 57.9 98.8 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 10 11 12 13 14 15
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
Table 6. RF = 1900 MHz, LO = 1697 MHz

0 0 1 33.2 2 75.0 3 <100 4 5 6 7 N 8 9 10 11 12 13 14 15 1 34.9 0.0 78.5 <100 <100 2 30.7 56.6 71.5 <100 <100 3 66.0 51.3 85.2 89.5 <100 <100 4 77.8 80.3 94.8 <100 <100 <100 5 6 7 M 8 9 10 11 12 13 14 15
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100
ADL5811
0 0 1 32.5 2 91.2 3 4 5 6 7 N 8 9 10 11 12 13 14 15 1 28.6 0.0 82.8 <100 2 45.7 53.0 60.5 <100 <100 3 52.4 80.8 87.7 <100 <100 4 5 6 7 M 8 9 10 11 12 13 14 15
97.3 <100 <100 <100 <100
<100 <100 <100 <100
<100 <100 <100 <100
<100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100
3.6 V Performance
VS = 3.6 V, TA = 25C, RF power = 10 dBm, LO power = 0 dBm, R1 = 800 , ZO = 50 , optimum SPI settings, unless otherwise noted. Table 8. RF = 900 MHz, LO = 697 MHz
M 0 0 1 2 3 4 5 6 7 N 8 9 10 11 12 13 14 15 41.0 59.2 90.0 <100 <100 <100 1 45.5 0.0 54.7 81.9 <100 <100 <100 <100 2 35.1 37.3 78.2 <100 <100 <100 <100 <100 <100 3 44.1 18.9 54.8 73.9 <100 <100 <100 <100 <100 4 30.2 54.8 62.8 89.6 <100 <100 <100 <100 <100 <100 5 49.9 40.4 83.1 79.4 <100 <100 <100 <100 <100 <100 <100 6 48.7 62.4 78.3 <100 <100 <100 <100 <100 <100 <100 <100 <100 7 66.6 53.2 96.1 95.3 <100 <100 <100 <100 <100 <100 <100 <100 <100 8 66.5 73.0 79.5 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 9 66.8 96.2 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 10 11 12 13 14 15
96.2 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100
ADL5811
M 0 0 1 33.4 2 68.9 3 <100 4 5 6 7 N 8 9 10 11 12 13 14 15 1 46.6 0.0 77.2 <100 <100 2 30.5 57.0 69.2 <100 <100 3 78.5 53.8 72.8 74.4 <100 <100 4 79.5 75.2 94.0 <100 <100 <100 5 6 7 8 9 10 11 12 13 14 15
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100 <100
<100 <100 <100 <100 <100

M 0 0 1 32.1 2 89.0 3 4 5 6 7 N 8 9 10 11 12 13 14 15 1 30.0 0.0 78.0 <100 2 51.1 53.6 65.5 <100 <100 3 51.7 72.9 73.5 <100 <100 4 5 6 7 8 9 10 11 12 13 14 15
88.2 <100 <100 <100 <100
<100 <100 <100 <100
<100 <100 <100 <100
<100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100 <100
<100 <100 <100 <100
ADL5811 CIRCUIT DESCRIPTION

The ADL5811 consists of two primary components: the RF subsystem and the LO subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance device with excellent electrical, mechanical, and thermal properties. The wideband frequency response and flexible frequency programming simplifies the receiver design, saves on-board space, and minimizes the need for external components. The RF subsystem consists of an integrated, tunable, low loss RF balun; a double balanced, passive MOSFET mixer; a tunable sum termination network; and an IF amplifier. The LO subsystem consists of a multistage limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A block diagram of the device is shown in Figure 58.
COMM IFGM IFON IFGD IFOP VPIF NC NC
The resulting balanced RF signal is applied to a passive mixer that commutates the RF input in accordance with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all idler (M N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a programmable low-pass filter network between the IF amplifier and the mixer and in the feedback elements in the IF amplifier. The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced open-collector output of the IF amplifier, with an impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, a differential amplifier, or an analog-to-digital converter (ADC) input while providing optimum second-order intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 . If operation in a 50 system is desired, the output can be transformed to 50 by using a 4:1 transformer or an LC impedance matching network. The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the low-pass filter between the mixer and the IF amplifier. Further optimization can be made by adjusting the IF current with an external resistor. Figure 42 and Figure 43 illustrate how various IF resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing the IF resistor. It is permissible to reduce the IF amplifiers dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (Note that no performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.) Because the mixer is bidirectional, the tuning of the RF and IF ports is linked and it is possible for the user to optimize gain, noise figure, IP3, and impedance match via the SPI. This feature permits high performance operation and is achieved entirely using SPI control. Additionally, the performance of the mixer can be improved by setting the optimum gate voltage on the passive mixer, which is also controlled by the SPI to enable optimum performance of the part. See the Applications Information section for examples of this tuning.
32
31
30
29
28
27
26
25 24 NC 23 NC 22 NC 21 LOIP 20 LOIN 19 LE
NC 1 RFCT 2 NC 3 RFIN 4 NC
5
ADL5811
NC 6 NC 7 NC 8
9 10 11 12 13 14 15 16
BIAS GEN
SERIAL PORT INTERFACE
18 DATA 17 CLK
VLO4
VLO3
VLO2
COMM
COMM
COMM
VLO1
COMM
Figure 58. Block Diagram
RF SUBSYSTEM
The single-ended, 50 RF input is internally transformed to a balanced signal using a tunable, low loss, unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 700 MHz to 2800 MHz. This balun is tuned over the frequency range by SPI controlled switched capacitor networks at the input and output of the RF balun.
09912-162
ADL5811
LO SUBSYSTEM
The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation and compression performance. The resulting LO amplifier provides very high performance over a wide range of LO input frequencies. The ideal waveshape for switching the passive mixer is a square wave at the LO frequency to cause the mixer to switch through its resistive region (from on to off and off to on) as rapidly as possible. While it has always been possible to generate such a square wave, the amount of dc current required to generate a large amplitude square wave at high frequencies has made it impractical to create such a mixer. Novel circuitry within the ADL5811 permits the generation of a near-square wave output at frequencies of up to 2800 MHz with dc current that compares favorably with that employed by narrow-band passive mixers. The input stages of the LO amplifier provide common-mode rejection, permitting the LO input to be driven either single ended or balanced. For a single-ended input, either LOIP or LOIN can be grounded. It is desirable to dc block the LO inputs to avoid damaging the part by the accidental application of a large dc voltage to the part. In addition, the LO inputs are internally dc blocked. Because the LO amplifier is inherently wideband, the ADL5811 can be driven with either high-side or low-side LO by simply setting the optimum RF balun and LPF inputs to the SPI. The LO amplifier converts a variable level, single or balanced input signal (6 dBm to +10 dBm) to a hard voltage limited, balanced signal internally to drive the mixer. Excellent performance can be obtained with a 0 dBm input level; however, the circuit continues to function at considerably lower levels of LO input power. The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. Blocking dynamic range can benefit from a higher level of LO drive, which pushes the LO amplifier stages harder into compression and causes them to switch harder and to limit the small signal gain of the chain. Both of these conditions are beneficial to low noise figure under blocking. NF under blocking can be improved several decibels for LO input power levels above 0 dBm. The LO amplifier topology inherently minimizes the dc current based on the LO operating voltage and the LO operating frequency. It is permissible to reduce the LO supply voltage down as low as 3.6 V, which drops the dc current rapidly. The mixer dynamic range varies accordingly with the LO supply voltage. No external biasing resistor is required for optimizing the LO amplifier. In addition, the ADL5811 has a power-down mode that can be used with any supply voltage applied to the part. All of the SPI inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All pins, including the RF pins, are ESD protected and have been tested up to a level of 2000 V HBM and 1250 V CDM.
ADL5811 APPLICATIONS INFORMATION

BASIC CONNECTIONS
The ADL5811 mixer is designed to downconvert radio frequencies (RF) primarily between 700 MHz and 2800 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 59 depicts the basic connections of the mixer. It is recommended to ac couple RF and LO input ports to prevent nonzero dc voltages from damaging the RF balun or LO input circuit. A RFIN capacitor value of 22 pF is recommended.
BIAS RESISTOR SELECTION

An external resistor, R1, is used to adjust the bias current of the integrated amplifier at the IF terminal. It is necessary to have a sufficient amount of current to bias both the internal IF amplifier to optimize dc current vs. optimum input IP3 performance. Figure 42 and Figure 43 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and input IP3 performance.
IF PORT
The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss. The real part of the output impedance is approximately 200 , as seen in Figure 31, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain. When a 50 output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 59.
VCC C1 0.1F L1 470nH L2 470nH C2 0.1F
VGS PROGRAMMING
The ADL5811 allows programmability for internal gate-to-source voltages for optimizing mixer performance over the desired frequency bands. The ADL5811 defaults the VGS setting to 0. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 39 and Figure 40.
C3 T1 120pF TC4-1W+ R20 OPEN C4 120pF R1 910 C5 120pF R21 0
IFOP
IFON
C8 0.1F PAD
32 31 30 29 28 27 26 25
C7 100pF RFIN C6 22pF
PAD VPIF IFGM NC IFOP IFON NC IFGD COMM
1 2 3 4 5 6 7 8
ADL5811
24 23 22 21 20 19 18 17
C17 22pF
LOIP
LE DATA CLK
VCC C23 10pF
9 10 11 12 13 14 15 16
VLO4 COMM VLO3 COMM VLO2 COMM VOL1 COMM
VCC VCC VCC C19 10pF C18 10pF
AGND BLK
VPOS RED VCC
C20 10pF
Figure 59. Basic Connections
09912-163
ADL5811
LOW-PASS FILTER PROGRAMMING
The ADL5811 allows programmability for the low-pass filter terminating the mixer output. This filter helps to block sum term mixing products at the expense of some noise figure and gain and can significantly increase input IP3. The ADL5811 defaults the LPF setting to 0. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 48 to Figure 51.
RF BALUN PROGRAMMING
The ADL5811 allows programmability for the RF balun by allowing capacitance to be switched into both the input and the output, which allows the balun to be tuned to cover the entire frequency band (700 MHz to 2800 MHz). Under most circumstances, the input and output can be tuned together though sometimes it may be advantageous for matching reasons to tune them separately. The ADL5811 defaults the RFB setting to 0. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 44 to Figure 47.
ADL5811 REGISTER STRUCTURE

Figure 60 illustrates the register map of the ADL5811. The ADL5811 only uses Register 5. Because of this, set all of the control bits to 5. When set to 0, the ENBL bit, DB7, enables the part. By setting this bit to 1, the mixer is powered down. The RFB IN CAP DAC and RFB OUT CAP DAC bits are used to tune the RF balun. In most cases, they are tuned together with the higher settings, 7, tuning for the low frequencies, and with the lower settings, 0, tuning for the high frequencies. There are times where it becomes advantageous to tune the input and output of the RF balun separately and that ability is provided. The LPF bits control the low-pass filter settings at the IF output. The ability to tune the low-pass filter allows some trade-off between gain, noise figure, and input IP3 with higher settings, 7, providing higher input IP3 at the cost of some gain and noise figure, and lower settings, 0, providing higher gain and lower NF at the cost of lower input IP3. The VGS bits control the VGS settings of the mixer core and allow further tuning of the device. Table 11 lists the optimum settings characterized for each frequency band. All register bits default to 0.
RESERVED
VGS
LPF
RFB OUT CAP DAC
RFB IN CAP DAC DB8 0
ENBL DB7 EN DB6 0
RESERVED DB5 0 DB4 0 DB3 0
CONTROL BITS DB2 DB1 DB0 C3(1) C2(0) C1(1)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 0 0 VGS2 VGS1 VGS0 LPF1 LPF0 0 CDO2 DCDO1 CDO0 0 CDI2 CDI1 CDI0
VGS2 VGS1 VGS0 0 0 0 ' ' ' 1 1 1
VGS SETTING 0 ' 7 MEN 0 1 MAIN ENABLE DEVICE ENABLED DEVICE DISABLED
LPF1 LPF0 LOW PASS FILTER SETTING 0 0 0 ' ' ' 1 1 3
CDI2 CDI1 CDI0 RF BALUN INTPUT TUNING 0 0 0 0 ' ' ' ' 1 1 1 7
CDO2 CDO1 CDO0 RF BALUN OUTPUT TUNING 0 0 0 0 ' ' ' ' 1 1 1 7
Figure 60. ADL5811 Register Maps
Table 11. Optimum Settings

RF Frequency (MHz) 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 LO Frequency (MHz) 497 597 697 797 897 997 1097 1197 1297 1397 1497 1597 1697 1797 1897 1997 2097 2197 2297 2397 2497 2597 VGS 3 1 2 1 3 3 3 3 3 3 3 3 3 3 3 2 3 2 3 3 1 3 LPF 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 2 2 3 2 2 2 RFB OUT CAP DAC 7 6 6 4 7 5 5 4 4 3 3 3 2 2 1 2 2 2 1 2 2 1 RFB IN CAP DAC 7 6 6 4 7 5 5 4 4 3 3 3 2 2 1 2 2 2 1 2 2 1
09912-160
ADL5811 EVALUATION BOARD

An evaluation board is available for the ADL5811. The standard evaluation board schematic is presented in Figure 61. The USB interface circuitry schematic is presented in Figure 64. The evaluation board layout is shown in Figure 62 and Figure 63.
L1 470nH C1 0.1F L2 470nH C2 0.1F C4 120pF R1 910
The evaluation board is fabricated using Rogers 3003 material. Table 12 details the configuration for the mixer characterization. The evaluation board software is available on www.analog.com.
VCC
C3 T1 120pF TC4-1W+
3 2 1 4 6
IFOP R20 OPEN
C5 120pF R21 0
IFON
C8 0.1F PAD
32 31 30 29 28 27 26 25
C7 100pF RFIN C6 22pF
PAD VPIF IFGM NC IFOP IFON NC IFGD COMM
1 2 3 4 5 6 7 8
ADL5811
24 23 22 21 20 19 18 17
C17 22pF
LOIP
LE DATA CLK
VCC C23 10pF
9 10 11 12 13 14 15 16
VLO4 COMM VLO3 COMM VLO2 COMM VOL1 COMM
VCC VCC VCC C19 10pF C18 10pF
AGND BLK
VPOS RED VCC
C20 10pF
Figure 61. Evaluation Board Schematic
Table 12. Evaluation Board Configuration

Components C1, C2, C8, C18, C19, C20, C23 C6, C7, RFIN C3, C4, C5, L1, L2, R20, R21, T1, IFOP, IFON Description Power supply decoupling. Nominal supply decoupling consists of a 0.1 F capacitor to ground in parallel with a 10 pF capacitor to ground positioned as close to the device as possible. RF input interface. The input channel is ac-coupled through C6. C7 provides bypassing for the center tap of the RF input balun. IF output interface. The open-collector IF output interfaces are biased through pull-up choke inductors, L1 and L2. T1 is a 4:1 impedance transformer used to provide a single-ended IF output interface, with C5 providing center-tap bypassing. Remove R21 for balanced output operation. LO interface. C17 provides ac coupling for the LOIP local oscillator input. Bias control. R1 sets the bias point for the internal IF amplifier. Default Conditions C1, C2 = 0.1 F (size 0402), C8, C18, C19, C20, C23 = 10 pF (size 0402) C6 = 22 pF (size 0402), C7 = 100 pF (size 0402) C3, C4, C5 = 120 pF (size 0402), L1, L2 = 470 nH (size 0603), R20 = open, R21 = 0 (size 0402), T1 = TC4-1W+ (Mini-Circuits) C17 = 22 pF (size 0402) R1 = 910 (size 0402)
C17, LOIP R1
09912-060
ADL5811
09912-062
Figure 62. Evaluation Board Top Layer
Figure 63. Evaluation Board Bottom Layer
09912-063
ADL5811
Y2 24.000000MHZ
1
CASE
3 2 4
DGND
C40 22PF
DGND
C41 22PF
DGND
5V_USB
J6
C34
1
3V3_USB
10PF C35 C36
DGND
3V3_USB
2 3 4 5
G1 G2 G3 G4
55
U7 8 R7 2K R8 2K
1
VCC A0 A1 A2 SCL SDA WC_N GND
0.1UF
11
17
27
32
43
2 3 6 7
24LC64-I-SN
10PF C37
DGND
3V3_USB
DGND
GND PINS
0.1UF
3 7
897-43-005-00-100001
P1
1
U6
AVCC
VCC
DGND
R9 3V3_USB
100K R10 100K C38 0.1UF C39 0.1UF
15 16
4 XTALOUT DPLUS 8 DMINUS 9 13 IFCLK 54 CLKOUT 29 CTL0_FLAGA CTL1_FLAGB 30 CTL2_FLAGC 31

33 34 35 36 37 38 39 40 18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52
2 3
SAMTECTSW10608GS3PIN
R11 R17
LE
0
R12
0
R18
SCL SDA
5 42
XTALIN RESET_N
PA0_INT0_N PA1_INT1_N PA2_SLOE PA3_W U2 PA4_FIFOADR0 PA5_FIFOADR1 PA6_PKTEND PA7_FLAGD_SLCS_N PB0_FD0 PB1_FD1 PB2_FD2 PB3_FD3 PB4_FD4 PB5_FD5 PB6_FD6 PB7_FD7 PD0_FD8 PD1_FD9 PD2_FD10 PD3_FD11 PD4_FD12 PD5_FD13 PD6_FD14 PD7_FD15
GND
12 26 28 41 53 56
DATA
0
R13
0
R19
CLK
0
R14 1K
DNI DGND
0
C49 TBD0402 R15 1K
DNI DGND
DGND
44 14
C50 TBD0402
WAKEUP RESERVED
330PF
DNI DGND
330PF
DNI DGND
R16 1K
DNI DGND
C51 TBD0402 330PF

DNI DGND
2
DGND
RDY0_SLRD RDY1_SLWR
DGND
AGND
6
10
PAD
PAD
CY7C68013A-56LTXC
DGND
3V3_USB 5V_USB
1
3P3V ORG
3V3_USB
DNI
R3 R4 2K
DGND DGND
C31 1.0UF
U5
0
SML-210MTT86
AGND
7 8 6
IN1
OUT1 FB GND
C32 1000PF
R6 140K
C33 1.0UF
DGND
DECOUPLING FOR U6
IN2 OUT2 SD_N PAD
2 3
DGND
DNI
ADP3334ACPZ
DGND
DGND
DGND
Figure 64. USB Interface Circuitry on the Evaluation Board
09912-161
A
D1
PAD
DGND
5
R5 78.7K
DGND BLK
C42 0.1UF
C43 0.1UF
C44 0.1UF
C45 0.1UF
C46 0.1UF
C47 0.1UF
C48 0.1UF
ADL5811 OUTLINE DIMENSIONS

PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.30 0.25 0.18
25 24 32 1
PIN 1 INDICATOR
0.50 BSC
EXPOSED PAD
3.45 3.30 SQ 3.15

8
17
TOP VIEW 0.80 0.75 0.70
0.50 0.40 0.30
16
BOTTOM VIEW
0.25 MIN
SEATING PLANE
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 65. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm 5 mm Body, Very Very Thin Quad (CP-32-13) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADL5811ACPZ-R7 ADL5811-EVALZ
1
Temperature Range 40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board
Package Option CP-32-13
033009-A
Quantity 1500
Z = RoHS Compliant Part.
2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09912-0-7/11(0)

High Ip3, 700 MHZ To 2800 MHZ, Double Balanced, Passive Mixer, If Amplifier, and Wideband Lo Amplifier

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High Ip3, 700 MHZ To 2800 MHZ, Double Balanced, Passive Mixer, If Amplifier, and Wideband Lo Amplifier

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Formati disponibili

High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier

FUNCTIONAL BLOCK DIAGRAM

SERIAL PORT INTERFACE

ADL5811 TABLE OF CONTENTS

Test Conditions/Comments Tunable to >20 dB broadband via serial port

700 Differential impedance, f = 200 MHz 30 Externally generated 6 VS 0 13 50 260||1.0

10 dBm input power 10 dBm input power

Resistor programmable IF current

Figure 2. Timing Diagram

ADL5811 ABSOLUTE MAXIMUM RATINGS

ADL5811 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC NC NC LOIP LOIN LE DATA CLK

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

NOTES 1. NC = NO CONNECT. CAN BE GROUNDED. 2. EXPOSED PAD MUST BE CONNECTED TO GROUND.

VLO4 COMM VLO3 COMM VLO2 COMM VLO1 COMM

ADL5811 TYPICAL PERFORMANCE CHARACTERISTICS

TA = 40C TA = +25C TA = +85C

TA = 40C TA = +25C TA = +85C

SUPPLY CURRENT (mA)

INPUT IP2 (dBm)

180 170 160 150

Figure 4. Supply Current vs. RF Frequency

Figure 7. Input IP2 vs. RF Frequency

TA = 40C TA = +25C TA = +85C

TA = 40C TA = +25C TA = +85C

CONVERSION GAIN (dB)

INPUT P1dB (dBm)

Figure 5. Power Conversion Gain vs. RF Frequency

Figure 8. Input P1dB vs. RF Frequency

TA = 40C TA = +25C TA = +85C

TA = 40C TA = +25C TA = +85C

NOISE FIGURE (dB)

INPUT IP3 (dBm)

Figure 6. Input IP3 vs. RF Frequency

Figure 9. SSB Noise Figure vs. RF Frequency

VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V

VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V

205 195 185 175 165 155 145

INPUT IP2 (dBm)

Figure 10. Supply Current vs. Temperature

Figure 13. Input IP2 vs. Temperature

VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V

VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V

CONVERSION GAIN (dB)

INPUT P1dB (dBm)

8.5 8.0 7.5 7.0 6.5 6.0 5.5

Figure 11. Power Conversion Gain vs. Temperature

Figure 14. Input P1dB vs. Temperature

VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V

VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V

INPUT IP3 (dBm)

Figure 12. Input IP3 vs. Temperature

Figure 15. SSB Noise Figure vs. Temperature

RF = 900MHz RF = 1900MHz RF = 2500MHz

SUPPLY CURRENT (mA)

INPUT IP2 (dBm)

50 40 30 20 10 0 30 RF = 900MHz RF = 1900MHz RF = 2500MHz

Figure 16. Supply Current vs. IF Frequency

Figure 19. Input IP2 vs. IF Frequency

RF = 900MHz RF = 1900MHz RF = 2500MHz

RF = 900MHz RF = 1900MHz RF = 2500MHz